Hybrid switching converter for and SoCs
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Hybrid switching converter architectures for powering processors and SoCs Yogesh Ramadass Kilby Labs Texas Instruments, Santa Clara 1
Transcript of Hybrid switching converter for and SoCs
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Hybrid switching converter architectures for powering processors and SoCs
Yogesh RamadassKilby LabsTexas Instruments, Santa Clara
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Mobile applications
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• Higher charging currents
• Processors with more power
• Thin profile, Heavily space constrained
M. Halpern, HPCA, 2016
~8A
~4A
Dongbin Hu, CPES, 2016
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Automotive applications
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Source: PwC analysis• Electronics heavy
• Higher current demands with low EMI
• 3V - 42V input support
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Increasing switching frequency
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Inductors are usually the largest component.
1) Smaller size
2) Faster response 3) Lower BOM cost
Converter volume: 1,270 mm3 Converter volume: 157 mm3
Inductor volume: 232 mm3 Inductor volume: 19.2 mm3
High frequency operation 15 times smaller inductors!
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High frequency (HF) buck converter limitations
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• High side switch (Q1) on‐time is very short at HF– 5 MHz 200ns period– 10‐to‐1 voltage ratio 20ns high side on‐time
Switch timing diagram
HF converters on the market today have low conversion ratios (<5-to-1) and low current (<1A)
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Buck converter loss breakdown
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Conduction
QRRSwitching
IV-Overlap
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BUCK HYBRID RESONANT
Lo
Co
S1
S2Vin
+
Vo
-
Ro
iLo
+
vsw
-
Topology Options
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Three‐Level Buck Converter (D < 0.50)
Slide 8
VIN
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VIN
VSW
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VIN
VSW
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VSW
VIN
VSW
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VSW
VIN − VFLY ≈ VIN/2 VFLY ≈ VIN/2
iL
TSW
t
t
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VIN
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VIN
VSW
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VIN
VSW
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VSW
VIN
VSW
CFLYCO
VOUTVFLY
Q1
Q2
Q3
Q4
iL
VSWVIN − VFLY ≈ VIN/2 VFLY ≈ VIN/2
iL
TSW
t
t
VIN VIN
Three‐Level Buck Converter (D > 0.50)
Slide 9
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Resonant Switched Capacitor Converter
Slide 10
• Extension of 3-level converter with very low inductance
• Constant inductor current traded off for small form factor
K. Kesarwani, APEC 2015
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3‐level converter advantages
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• Q1, Q3 gate‐drives interleaved and 180⁰ out of phase. 2X switching frequency
• Peak inductor ripple current is ¼ of 2L converter
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Power density improvements
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• >2.5X area density and >5X volume density benefits• Reduction in height and ability to handle larger currents with smaller
inductors
Figure removed for public release
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Switch Rsp and FoM
• Lower voltage switches have inherent Rsp and FoMbenefits
• Ability to use lower voltage rated FETs crucial in nano‐meter scale CMOS processes
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Device Voltage Ratings
VIN
0
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3‐Level Loss Breakdown
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Conduction
QRR
IV-Overlap
Switching
Passive
Savings
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3‐Level with Lower Voltage Top Switch
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Conduction
QRR
IV-Overlap
Switching
Passive
Savings
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SW
I_HS
VGS_HS
• Loop parasitics cause ringing forcing the slowdown of drives and increasing overlap losses
Power Loop Inductance ‐ Buck
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SW
I_HS
VGS_HS
• Increased number of switches and external passives – increase in loop inductance
• Effective on‐chip passives needed to take peak currents
Power Loop Inductance – 3‐Level
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SW
I_HS
VGS_HS
Board routing ‐ Buck
LP8758
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SW
I_HS
VGS_HS
Board routing – 3‐Level
FB1N
VT1 VIN12
INTB
SW2 PGND1
IM1 VB1
PGND1 VB1
AGND FB1P
SW2
SW1
SW1
GPIO1
SDA
VT1M2
M2
M62 M1
VIN12
CflyCim
PGND1
M52
• Increased number of switches and external passives –complicated floor planning and board routing
• Effective on‐chip passives needed to take peak currents
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Gate drive and boot capacitor management
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Gate drive and boot capacitor management
• Complicated boot‐capacitor management• Increased level shifting complexity
Figure removed for public release
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Conclusions
• Power density and efficiency becoming ever more crucial in automotive and consumer systems
• Hybrid and Resonant topologies provide distinct advantages in reducing magnetics size and improving efficiency
• Increased device/passive/pin count and control complexity
• Provides opportunities to circuit and system designers to come up with innovative circuit architectures and control techniques to mitigate problems
