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EE141 EECS141 1 Lecture #11

EE141 EECS141 2 Lecture #11

  HW 4 due on Friday   No re-grades on MT1 after next Wednesday   Project to be launched in week 7 – stay tuned

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EE141 EECS141 3 Lecture #11

0

2

4

6

8

10

12

12-1

4

15-1

7

18-2

0

21-2

3

24-2

6

27-2

9

30-3

2

33-3

5

36-3

8

39-4

1

Score Histogram

Max: 40 Mean: 27.9 Median: 28.1 Stdev: 5.97

EE141 EECS141 4 Lecture #11

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EE141 EECS141 5 Lecture #11

= CGCS + CGSO = CGCD + CGDO

= CGCB = Cdiff

G

S D

B

= Cdiff

EE141 EECS141 6 Lecture #11

 Capacitance (per area) from gate across the oxide is W·L·Cox, where Cox=εox/tox

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EE141 EECS141 7 Lecture #11

Cgate vs. VGS (with VDS = 0)

Cgate vs. operating region

EE141 EECS141 8 Lecture #11

Off/Lin/Sat CGSO = CGDO = CO·W

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EE141 EECS141 9 Lecture #11

 COV not just from metallurgic overlap – get fringing fields too

  Typical value: ~0.2fF·W(in µm)/edge

n + n +

Cross section

n + n +

Cross section

Fringing fields

EE141 EECS141 10 Lecture #10

Bottom

Side wall

Side wall Channel

Source

Substrate

W

NA+

NA LS

ND

xj

  Bottom – Area cap – Cbottom = Cj·LS·W

  Sidewalls – Perimeter cap – Csw = Cjsw·(2LS+W)

 GateEdge – Cge = Cjgate·W – Usually automatically included in the SPICE model

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EE141 EECS141 11 Lecture #10

  SPICE model equations:

–  Area CJ = area × CJ0 / (1+ |VDB|/φΒ)mj

–  Perimeter CJ = perim × CJSW / (1 + |VDB|/φΒ)mjsw

–  Gate edge CJ = W × CJgate / (1 + |VDB|/φΒ)mjswg

  How do we deal with nonlinear capacitance?

  Junction caps are nonlinear

–  CJ is a function of junction bias

EE141 EECS141 12 Lecture #10

Replace non-linear capacitance by large-signal equivalent linear capacitance

which displaces equal charge over voltage swing of interest

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EE141 EECS141 13 Lecture #10

  Gate-Channel Capacitance   CGC ≈ 0 (|VGS| < |VT|)   CGC = Cox·W·Leff (Linear)

–  50% G to S, 50% G to D   CGC = (2/3)·Cox·W·Leff (Saturation)

–  100% G to S

  Gate Overlap Capacitance   CGSO = CGDO = CO·W (Always)

  Junction/Diffusion Capacitance   Cdiff = Cj·LS·W + Cjsw·(2LS + W) + CjgW (Always)

EE141 EECS141 14 Lecture #10

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EE141 EECS141 15 Lecture #10

EE141 EECS141 16 Lecture #10

V in V out

V DD

Wp = βWn

Wn

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EE141 EECS141 17 Lecture #10

EE141 EECS141 18 Lecture #10

  For DC VTC, IDn = IDp   Graphically, looking for intersections of NMOS and

PMOS IV characteristics   To put IV curves on the same plot, PMOS IV is

“flipped” since |VDSp| = VDD – Vout   Also, |VGSp| = Vdd - Vin I

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EE141 EECS141 19 Lecture #10

EE141 EECS141 20 Lecture #10

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EE141 EECS141 21 Lecture #10

10 0 10 1 0.8 0.9

1

1.1 1.2 1.3

1.4 1.5 1.6

1.7 1.8

M

V (V

)

W p /W n

EE141 EECS141 22 Lecture #10

10 0 10 1 0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

M

V (V

)

W p /W n

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EE141 EECS141 23 Lecture #10

A simplified approach

EE141 EECS141 24 Lecture #10

Gain=-1

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EE141 EECS141 25 Lecture #10

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5

V in (V)

V out (V

) Wider PMOS

Wider NMOS

Symmetrical

EE141 EECS141 26 Lecture #10

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5

V in (V)

V out (V

)

Fast PMOS Slow NMOS

Fast NMOS Slow PMOS

Nominal

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EE141 EECS141 27 Lecture #10

Not all transistors are alike Impacts parameters such as reliability and performance

Define process corners: SS, FF, SF, FS

EE141 EECS141 28 Lecture #10

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EE141 EECS141 29 Lecture #10

•  We modeled this with:

C

•  Discharging a capacitor

tp = ln (2) RC

EE141 EECS141 30 Lecture #10

 Real transistors aren’t exactly resistors   Look more like current sources in saturation

 Two questions:  Which region of IV curve determines delay?  How can that match up with the RC model?

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EE141 EECS141 31 Lecture #10

•  With a step input: ID

VDS

VDD VDD /2

VGS = VDD VDD VDD/2

VVSAT

•  Transistor is in (velocity) saturation during entire transition from VDD to VDD/2

EE141 EECS141 32 Lecture #10

•  In saturation, transistor basically acts like a current source:

IDSAT C

VOUT

VOUT = VDD - (IDSAT/C)t

VOUT

t

VDD

VDD/2

tp

tp = C(VDD/2)/IDSAT

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EE141 EECS141 33 Lecture #10

EE141 EECS141 34 Lecture #10

•  Including output conductance:

•  For “small” λ:

IDSAT C

VOUT

1/(λIDSAT)

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EE141 EECS141 35 Lecture #10

•  Transistor current not linear on VOUT – how is the RC model going to work?

•  Look at waveforms:

•  Voltage looks like a ramp for RC too

EE141 EECS141 36 Lecture #10

•  Match the delay of the RC model with the actual delay:

•  Often just:

•  Note that the book uses a different method and gets 0.75·VDD/IDSAT instead of ~0.72·VDD/IDSAT.

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EE141 EECS141 37 Lecture #10

EE141 EECS141 38 Lecture #10

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EE141 EECS141 39 Lecture #10