High Volume Photonics Manufacturing

High Volume Photonics Manufacturing Bob Pfahl, Principle Investigator

[email protected] Lionel Kimerling, Principle Investigator

[email protected] Jim McElroy, Executive Director

[email protected] http://photonicsmanufacturing.org/

Common Pla)orms – Common Interfaces Cost – Integra3on – Cost

INEMI Webcast 2-‐19-‐15

communications technology roadmap

Connectivity and Society

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Security, Efficiency, Convenience, Presence, Education, Culture

Compute system performance has increased at a steady rate of 1000x/10 yr with ~constant cost for 20 yrs. The same scaling rate is needed for the next 20 years.


Migration of optics from board edge…eliminates interfaces: devices, drivers and transmission lines

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Transmission Line Electrical Connection Optical Connection

OE Optronics

Linecard/PCB CPU

CPU

CPU

CPU

Cage

Embedded

Integrated

Cage AOC

CPU CPU

Pluggable

Board Level

Agilent

Reflex

Fujitsu

MSA

Altera

CTR III TWG Report, Semicon West (2013), Roe Hemenway, Photonic Controls


Pervasive Photonic Integration §  The number of photonic components deployed in IT

systems is increasing. §  The contribution of photonics to system cost is becoming

significant. §  Manufacturing cost reduction is directly related to the

number of units produced. §  If a common manufacturing platform is shared across the

industry, one can expect that cost reduction will scale with manufacturing volume.

§  Integrated Silicon Microphotonics is today the only platform capable of high volume production (>10 million units) and high levels of integration.

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Deployment of Optical Interconnection Design Rule: photonics at BxD=1Tb/s x cm

Monolithic, chip-level photonic integration: solution to cost, energy bandwidth density. 5


iNEMI

SYSTEMS END USERS COMPONENTS COMPONENTS SERVICES CONTENT COMPONENTS

MATERIALS & PROCESS EQUIPMENT NETWORKS

cost revenues

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MIT

PSMC Technical Working Groups

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•  Monolithic Integration TWG Lionel Kimerling, MIT

•  Hybrid Integration TWG Dick Otte, Promex Industries

•  Packaging of Electronic Photonic Systems TWG Bill Bottoms, 3MTS

•  Circuit boards, Backplanes and Connectors TWG John MacWilliams, Bishop

•  Functions and Markets TWG Richard Grzybowski, MACOM

You are invited to par.cipate: [email protected]


Electronic-Photonic Systems Functionality and Architecture §  Functionality is the ability of a technology to

perform a complete task: r  IT: communication, computation, imaging r  and to scale to future needs r  with reducing cost, energy and footprint, latency.

§  Architecture is evolving to distributed, self-aware topologies and convergence: r  electronic-photonic r  hardware-software-architecture

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Function and Architecture Performance Objectives

§ Bandwidth: as close to ∞ as possible § Physical Density: as close to ∞ as possible § Latency: as close to 0 as possible § Power Required: as close to 0 as possible § Cost: as close to 0 as possible §  I/O Port Count: as close to ∞ as possible 9


Scaling Functionality Roadblock: Assembly and Packaging Design: increased component density, constant power density, chip-to-package-to-board §  electronic-photonic partitioning §  waveguide/fiber attach §  ‘fiber-to-the-user’ interface/architecture

Manufacturing: throughput, yield, utilization §  known good die §  photonic test §  chip repair §  reliability and redundancy

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Large Scale Integration History §  VLSI Consortium (Japan)

r  Silicon wafer specification r  Defects: crystal growth and processing

§  SEMATECH (US) r  Tool and fab standardization r  Software (materials, tools, scheduling, design), Yield, Throughput

§  ITRS r  Function transition from DRAM to Microprocessor r  Consolidation to foundry structure

§  PETRA (Japan) r  Silicon Photonics r  Electronic-Photonic Synergy

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Commercial Entry of Silicon Photonics Board-level photonic interconnection: 2015

§  Initial penetration is in HPC and Core Routers, then to Datacenters §  Factors of speed, energy, density come together for optical solution

at board level.

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Interconnect Time Frame

Reach BW BW Density (G/cm2)

Energy (pJ/bit)

Rack ~2000 20-100m 40-200 G ~100 1000 à 200

Chassis ~2005 2-4 m 20-100 G ~100-400 400 à 50

Backplane ~2010 1-2 m 100-400 G ~400 100 à 25

Board ~2015 .01-1 m 0.3 – 1T ~1250 25 à 5 Module ~2020 1-10 cm 1 – 4 T >10000 1 à .1

Chip ~2025 0.1-3 cm 2-20T >40000 .1à.01

CTR III TWG Report, Semicon West (2013), Roe Hemenway, Photonic Controls

PETRA: 30000


Integrated Microphotonics manufacturing and performance

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Scaling with a standard, modular platform: •  increases: yield, reliability, density •  reduces: cost, time to market, power, latency


Photonic System Disaggregation §  Computation systems have become

communication-centric. §  Communication systems have become

heterogeneous. §  Application efficiency optimization requires disaggregated, special purpose hardware.

r  modularity r  retrofit updated hardware resources r  ‘PC model’: commoditize components r  silicon photonics focus: transceiver and switch

single mode silicon photonics is “future-proof” 14


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Silicon Photonics for Disaggregation

In Jan. 2013, Intel announced a collaboration with Facebook on a new disaggregated, rack-scale server architecture that enables independent upgrading of compute, network and storage subsystems

The disaggregated rack architecture includes Intel’s new photonic architecture, based on high-bandwidth, 100Gbps Intel® Silicon Photonics Technology, that enables fewer cables, increased bandwidth, farther reach and extreme power efficiency compared to today’s copper based interconnects.

Mezzanine Options

Intel Ethernet chip and Intel Silicon Photonics

Optical PCIe via Intel Silicon Photonics

Intel® Xeon ® processor based tray

Mezzanine fiber

Intel® AtomTM

Micro-server tray

Source: Justin Rattner, Intel


Switching Platform Analysis §  Problem: communication and computation scaling

r  data center revolution: ‘everything is computation’ r  cost, capacity, energy, latency: 2x/yr = 1000x/10yrs r  efficient hardware, software and architecture

§  Constraints: supply chain coordination r  change guided by an inclusive Roadmap r  hardware/architecture/software convergence

§  Switches in parallel architectures r  minimize: energy, latency r  maximize: utilization, capacity, interoperability, control r  Dis-aggregation; Internet of Things; Virtualization

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§  High-yield arrays of parallel VCSELs, PINs, IC’s and fiber §  Array level IC’s with integrated and shared functions §  Electrical connector with short electrical traces §  Low cost MMF Parallel fiber alignment

The VCSEL Array E-O-E Matrix Switch

image compliments of Finisar


Optical Path Switching IP to circuit switching for large files

18 VICTORIES Project, AIST Japan

•  103 reduction in cost •  103 increase in data rate •  no need to match data rates •  congestion reduction •  multiple access by broadcast


Silicon Photonics for Functionality LSI Silicon Photonics

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26x26 Quantum Photonic Processor Dirk Englund, MIT

Silicon Phased Arrays for LIDAR Michael Watts, MIT

and routing, sensing, imaging, ...


Design-Tools-Processes and COST Process-based Cost Modeling (PBCM)

§ Objective: Map from description of technology to process cost.

§ Purpose: Inform technical decisions BEFORE investment.

Process Model

Operations Model

Financial Model

Pro

duct

D

escr

iptio

n

Pro

duct

ion

Cos

t

Pro

cess

ing

Req

uire

men

ts

Operating Conditions Factor Prices R

esou

rce

Req

uire

men

ts

Current Model Captures ~60 Processes

Kirchain, MIT (2005)


Cost is Highly Volume Dependent §  Integration provides cost savings at high volume. §  Cost at Low Volume

r  hybrid InP/Si chip < monolithic Si photonic chip, but r  hybrid backend > integrated backend due to assembly

of discrete components.

§  Summary of findings: r  Low (<1.3 M units): DML VCSEL array r  Medium (1.3 M~2.5 M units): Hybrid InP/Si r  High (>2.5 M units): Monolithic Si r  Backend (packaging and assembly) is the major factor.

Kirchain, MIT


Cost is Lower for Larger Wafer Size

22 Kirchain, MIT


Manufacturing History 1980s

• Vertically-integrated firms. • Research, development, design, production and marketing promote innovation, quality and efficiency. • Core firm activities located close to lead customers and best suppliers to promote JIT & mutual learning.

TODAY

•  Core-competence firms. •  Massive fragmentation of

production systems. •  Functions distributed between

‘home’ societies and ‘host’ societies.

•  Networks of production chains link brands, product definition and design, contract manufacturers, assemblers, distributors, retailers.

Elisabeth Reynolds, MIT Industrial Performance Center


Challenge: the Industrial Ecosystem §  When innovation grew out of large firms, resources ($

$, skills, plants) were available for scale up.

§  Where do those resources come from today?

§  Large employers provided skills and training.

§  How do we educate the workforce we need?

§  Integrated Silicon Photonics is a transformative manufacturing technology.

§  How will it be adopted by and diffused into the firms who might use it?

17 Elisabeth Reynolds, MIT Industrial Performance Center


Integrated Photonics Manufacturing Institute Innovation and Manufacturing Institute IP-IMI $110M US + $110M industry for 5 years

r  Each manufacturing innovation institute serves as a regional hub, bridging the gap between applied research and product development by bringing together companies, universities, and Federal agencies to co-invest in key technology areas that encourage investment and production in the U.S.:

r  education and training of students and workers at all levels,

r  provide the shared assets to help companies, most importantly small manufacturers, access the cutting-edge capabilities and equipment to design, test, and pilot new products and manufacturing processes.

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Monolithic Silicon Microphotonics Roadmap

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E-‐P hybrid

Matrix Switch

Monolithic-‐embedded Monolithic-‐embedded Monolithic-‐embedded

Comm/Comp/Imaging Embedded

$0.01/Gbps

128Tbps

Small Commercial Demand for Technically Viable OpGcal SoluGons

No Technically Viable OpGcal SoluGons Exist

FuncGon

TxRx

Processor

Cost

BW density

Energy

Reach

I/O Capacity

NOW NEXT LIMITS

8x8 hybrid 32x32

$1/Gbps $0.1/Gbps

30 Tb/s/cm2

10pJ/b

1000km 100m 1cm

40 Gbps 400Gbps

Commercially Viable OpGcal SoluGons Deployed

WDM coherent

Signal CondiGoning FFT

1pJ/b 100fJ/b

A Revolution in Packaging Is Needed

At the leading edge everything will change to allow high reliability SiP products meeting

market needs at low cost. This requires:

ü  New design and simulation tools ü  New materials ü  New device designs and architectures ü  New package architectures ü  New network architectures ü  New manufacturing processes

Photonic System Packaging Roadmap

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Package substrates

Materials properGes

Electrical ProperGes

Photonic ProperGes

Supply chain

Volume manufacturing

Into/out of package

Heterogeneous Integra6on by material and component

Small Commercial Demand for Technically Viable OpGcal SoluGons

No Technically Viable OpGcal SoluGons Exist

Components

NOW NEXT LIMITS Commercially Viable

OpGcal SoluGons Deployed

Energy/thermal

Electronic-‐Photonic Substrates required

Packaging is oVen the limiGng factor

Increase system performance

Supply Chain is Key to product cost


Summary: Scaling IT to 2050

§  Technology drivers r  Component performance will scale with integration. r  Parallelism is architectural scaling paradigm. r  Virtualization is functional scaling paradigm. r  All drivers will not scale at the same pace. r  Programming has to keep up. Architecture/Hardware/Software must be co-designed.

§  Vision for “World Wide Data Center” 2035 §  ‘Internet’ = one interconnected ‘data center’

§  Resources virtualized and provisioned as services 29


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Targets for Photonic Integration •  Video •  Data Centers, High Performance Computing •  IoT: sensors, imagers, ... •  Poorest Roadmap Vision

–  scaling: switch/router port count scaling –  architecture: hybrid packet/circuit networks –  management: high connectivity complexity –  control: self aware functionality

•  The Biggest Problems to Solve –  Manufacturing: cost, energy, density, reliability, T-to-M –  Locality: control and programming

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High Volume Photonics Manufacturing

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