High Transconductance Surface Channel In 0.53 Ga 0.47 As MOSFETs Using MBE Source-Drain Regrowth and...
14
IPRM 2013 1 High Transconductance Surface Channel In 0.53 Ga 0.47 As MOSFETs Using MBE Source-Drain Regrowth and Surface Digital Etching Sanghoon Lee 1* , C.-Y. Huang 1 , A. D. Carter 1 , J. J. M. Law 1 , D. C. Elias 1 , V. Chobpattana 2 , B. J. Thibeault 1 , W. Mitchell 1 , S. Stemmer 2 , A. C. Gossard 2 , and M. J. W. Rodwell 1 1 ECE and 2 Materials Departments University of California, Santa Barbara, CA 2013 Conference on Indium Phosphide and Related Materials Kobe, Japan 05/22/2013 *[email protected]
description
High Transconductance Surface Channel In 0.53 Ga 0.47 As MOSFETs Using MBE Source-Drain Regrowth and Surface Digital Etching. - PowerPoint PPT Presentation
Transcript of High Transconductance Surface Channel In 0.53 Ga 0.47 As MOSFETs Using MBE Source-Drain Regrowth and...
IPRM 20131
High Transconductance Surface Channel In0.53Ga0.47As MOSFETs Using MBE Source-Drain Regrowth and
Surface Digital Etching
Sanghoon Lee1*, C.-Y. Huang1, A. D. Carter1, J. J. M. Law1, D. C. Elias1, V. Chobpattana2, B. J. Thibeault1, W. Mitchell1, S. Stemmer2, A. C. Gossard2, and
M. J. W. Rodwell1
1ECE and 2Materials DepartmentsUniversity of California, Santa Barbara, CA
2013 Conference on Indium Phosphide and Related MaterialsKobe, Japan05/22/2013
IPRM 20132
Outline Motivation: Why III-V MOSFETs?
Key Design Considerations- Device Structure : Gate-last with S/D regrowth
- Damage during regrowth : surface digital etching
Process Flow Measurement Results
- I-V Characteristics
- TLM measurement
Conclusion
IPRM 20133
Why III-V MOSFETs in VLSI ?
more transconductance per gate widthmore current (at a fixed Vdd )→ IC speedor reduced Vdd (at a constant Ion)→ reduced poweror reduced FET widths→ reduced IC size
increased transconductance from:low mass→ high injection velocitieslower density of states→ less scatteringhigher mobility in N+ regions → lower access resistance
Other advantagesheterojunctions→ strong carrier confinementwide range of available materialsepitaxial growth→ atomic layer control
IPRM 20134
Key Design Considerations
Gate Dielectric:Thinner EOT : scaled high-k dielectricLow Dit : surface passivation5), minimized process damage6)
Channel Design:Thinner wavefunction depth: Thin channel, less pulse doping.More injection velocity: high In-content channel4)
Device structure: Scalability (sub 20 nm-Lg,<30 nm contact pitch) : self-aligned S/D, very low ρc 2) Carrier supply: heavily doped N+ source region3)
Shallow junction: regrown S/D3) or Trench-gate
1) M. Wistey et al. EMC 2009; 2) A. Baraskar et al. IPRM 2010 ; 3) U. Singisetti et at. EDL 2009 ; 4) S. Lee et al. EDL 2012 (accepted); 5) A. Carter et at. APEX 2011; 6) G. Burek, et al, JVST 2011.
IPRM 20135
Device Structure : Gate-Last process
Gate-First Fully self-aligned transistor at nm dimensions
Process damage during gate metal deposition and definition
Large ungated region: High pulse doing Large leakage current and increase in wavefunction depth
Gate-Last (substitutional-gate)Low-damage process: Thermal gate metal, No plasma process after gate dielectric deposition
Rapid turn-around rapid learning.
A. Carter et at., DRC 2011
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
N+ InAs (Regrown S/D)Capping layer
Ti/Pd/Au
S/D metalNi/Au
IPRM 20136
SiO2 Capped, 500 oC anneal
-2 -1 0 1 2Voltage (V)
0
0.2
0.4
0.6
0.8
1
1.2
-2 -1 0 1 2
Control
1 KHz10 KHz100 KHz1 MHz
Cap
acita
nce
(F/
cm2 )
Voltage (V)
Evidence of Surface Damage During RegrowthLong-channel FETs: consistently show >100 mV/dec. subthreshold swing
Indicates high Dit despite good MOSCAP data. Suggests process damage.
Experiment: SiO2 capping + high temp anneal + strip MOSCAP Process
Finding: large degradation in MOSCAP dispersion. Confirms process damage hypothesis.
Large dispersion Large Dit
IPRM 20137
Post-Regrowth Surface Digital Etching for Damage Removal
- Surface removed by digital etch process2’ in BOE (dummy gate removal) , # cycles: 15’ UV ozone (surface oxidation)
1’ dilute HCl (native oxide removal) 13 - 15 Ȧ/cycle, ~0.16 nm RMS roughness
- Etch significantly improves subthreshold swing and gm
- Using this technique, we can easily thin the channel thickness.
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
HSQ
N+ InAs (Regrown S/D)5 nm n+ InGaAs (Capping layer)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
N+ InAs (Regrown S/D)Capping layer
IPRM 20138
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
HSQ
5 nm n+ InGaAs (Capping layer)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
HSQ
N+ InAs (Regrown S/D)
5 nm n+ InGaAs (Capping layer)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
HSQ
N+ InAs (Regrown S/D)
5 nm n+ InGaAs (Capping layer)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
N+ InAs (Regrown S/D)Capping layer
Ti/Pd/Au
S/D metalNi/Au
1 nm/ 4 nm Al2O3/HfO2
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
N+ InAs (Regrown S/D)Capping layer
Ni/Au
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
N+ InAs (Regrown S/D)Capping layer
3 nm 3.9e12/cm2 Pulse doping
Process Flow
- Epitaxial layer growth- Dummy gate definition
- InAs Source/Drain regrowth - Mesa isolation- InAs debris wet-etching
- Dummy gate removal- Capping layer digital etching
- High-k deposition- Annealing- Gate metal deposition
- S/D metal deposition
IPRM 20139
-0.2 0.0 0.2 0.4 0.6 0.80.00.20.40.60.81.01.21.41.61.82.0
VDS = 0.05 V
VDS = 0.5 V
Gm
(mS/m
)Cu
rren
t Den
sity
(mA/
m)
Gate Bias (V)0.00.20.40.60.81.01.21.41.61.82.0
-0.2 0.0 0.2 0.4 0.6 0.810-5
10-4
10-3
10-2
10-1
100
101
VDS = 0.5 V
VDS = 0.05 V
SS ~ 120 mV at VDS=0.05 V
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)
I-V Characteristics for short and long channel devices
-0.2 0.0 0.2 0.4 0.6 0.8 1.00.0
0.1
0.2
0.3
0.4
0.5
0.6
VDS = 0.1 V to 0.7 V 0.2 V increment G
m (m
S/m)
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.0
0.1
0.2
0.3
0.4
0.5
0.6
-0.2 0.0 0.2 0.4 0.6 0.8 1.010-6
10-5
10-4
10-3
10-2
10-1
100
101
VDS = 0.1 V to 0.7 V 0.2 V increment
SS ~ 95 mV at VDS=0.1V
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)
- 1.6 mS/μm at Vds=0.5 V for a 65 nm-Lg device. - 95 mV/dec SS for a 530 nm-Lg device.
IPRM 201310
Experimental : with surface digital etching , 75 nm-Lg
Control : without capping layer and surface digital etching, 75 nm-Lg
Comparison with a control sample (short channel)
-0.2 0.0 0.2 0.4 0.6 0.80.00.20.40.60.81.01.21.41.61.8
VDS = 0.1 V to 0.7 V 0.2 V increment G
m (m
S/m)
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.00.20.40.60.81.01.21.41.61.8
-0.2 0.0 0.2 0.4 0.6 0.810-5
10-4
10-3
10-2
10-1
100
101
VDS = 0.1 V to 0.7 V 0.2 V increment
SS ~ 124 mV at VDS=0.1V
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4VGS = 0 V to 1.6 V 0.2 V increment
Curr
ent D
ensi
ty (m
A/m
)
Drain Bias (V)
-0.4 -0.2 0.0 0.2 0.4 0.6 0.80.0
0.2
0.4
0.6
0.8
1.0
1.2
VDS = 0.1 V to 0.7 V 0.2 V increment G
m (m
S/m)
Curr
ent D
ensi
ty (m
A/m
)Gate Bias (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-0.4 -0.2 0.0 0.2 0.4 0.6 0.810-5
10-4
10-3
10-2
10-1
100
101
VDS = 0.1 V to 0.7 V 0.2 V increment
SS ~ 258 mV at VDS=0.1 V
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4VGS = -0.4 V to 1.8 V 0.2 V increment
Curr
ent D
ensi
ty (m
A/m
)
Drain Bias (V)
- ~75 % increase in peak transconductance at Vds = 0.5 V - significantly better short channel characteristic with surface digital etching
IPRM 201311
Experimental : with surface digital etching, 535 nm-Lg
Control : without surface digital etching, 500 nm-Lg
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0
0.1
0.2
0.3
0.4
0.5
0.6VGS = 0 V to 1.8 V 0.2 V increment
Curr
ent D
ensi
ty (m
A/m
)
Drain Bias (V)-0.2 0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VDS = 0.1 V to 0.7 V 0.2 V increment G
m (m
S/m)
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.0
0.1
0.2
0.3
0.4
0.5
0.6
-0.2 0.0 0.2 0.4 0.6 0.8 1.010-6
10-5
10-4
10-3
10-2
10-1
100
101
VDS = 0.1 V to 0.7 V 0.2 V increment
SS ~ 95 mV at VDS=0.1V
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)
-0.2 0.0 0.2 0.4 0.6 0.8 1.00.0
0.1
0.2
0.3
0.4
0.5
0.6
VDS = 0.1 V to 0.7 V 0.2 V increment G
m (m
S/m)
Curr
ent D
ensi
ty (m
A/m
)Gate Bias (V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
-0.2 0.0 0.2 0.4 0.6 0.8 1.010-5
10-4
10-3
10-2
10-1
100
101
VDS = 0.1 V to 0.7 V 0.2 V increment
SS ~ 240 mV at VDS=0.1 V
Curr
ent D
ensi
ty (m
A/m
)
Gate Bias (V)0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6VGS = -0.4 V to 1.4 V 0.2 V increment
Curr
ent D
ensi
ty (m
A/m
)
Drain Bias (V)
- Similar on-state characteristics (~0.4 V Vt shift) - Better short channel effect
Comparison with a control sample (long channel)
IPRM 201312
TLM Measurement for S/D metal contact
0 5 10 15 20 250
100200300400500600700800
Ti /Pd/Au
5 nm n++ InGaAs (Capping layer)
50 nm n++ InAs(regrown contact layer)
Gap
InGaAs Channel
400 nm In0.52AlAs (UID)
S.I. InP
Gate metal
3 nm 3.9e12/cm2
Pulse doping
Ti/Pd/Au
5 nm n++ InGaAs
50 nm n++ InAs(regrown)
~1.2 μm
- 0.15 ohm-μm2 Contact resistivity and 25 ohm/sq. sheet resistance. - 64 ohm-μm S/D access resistance (~5 % transconductance degradation)
IPRM 201313
Conclusion
Using digital etching, damaged surface can be effectively removed in a nanometer precision without etch-stop.
The removal of the damaged surface significantly improves both on- and off-state performance.
gm = 1.6 mS/μm at Vds=0.5 V for a 65 nm-Lg device 95 mV/dec for a 530 nm-Lg device
InAs regrown S/D provides very low contact resistivity of 0.15 ohm-μm2 .
IPRM 201314*[email protected]
Thanks for your attention!Questions?
This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006). A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.
