Design of Operational Transconductance

Amplifiers for Filtering Applications

A Project Report Submitted

in Partial Fulfillment of the Requirements

for the Degree of

Bachelor of Technology

in

Electronics and Communication Engineering

by

Monalisha Saikia (Gau-C-15/L-286)

Sonu Kumar (Gau-C-15/012)

Amit Anand (Gau-C-15/013)

Jyotishna Kurmi (Gau-C-15/017)

Binita Brahma (Gau-C-15/032)

Under the Guidance of

Mr. Antaryami Panigrahi

Department of Electronics and Communication Engineering

CENTRAL INSTITUTE OF TECHNOLOGY-KOKRAJHAR,

ASSAM, INDIA

May-2019

ABSTRACT

In the wireless transreceiver, the analog baseband section is responsible for adjacent

channel selectivity, anti-aliasing and dynamic range maximization. A channel filter

with high linearity, tunable Band Width, low noise etc. is important for the performance

of the whole RF front-end.Frequency and gain programmability, as well as power

efficiency and silicon area are key aspects for the baseband filter. In this thesis, a detail

comparison of various OTAs with respective small signal models are presented and

simulated in 250nm CMOS technology. A 3rd order passive Buttorworth filter has been

implemented using OpAmp-RC and Gm-C integrators using Ladder synthesis and

biquad respectively. 2nd Order biquads are cascaded to the 1st order sections to make

3rd filter. 3rd order filter using Opamp-RC integrators are simulated in Multisim

Environment, transistor level simulation based on Gm-C biquad has been implemented

in Tanner v.15 Software. Opamp-RC based filter offers a band width of 425 kHz, pass

band gain of 0 dB, where as Gm-C integrator based filter offers 85 MHz, pass band

gain of 0 dB . Over-all power dissipation of the 3rd order Gm-C filter is 4.3mW with

1.8V DC Supply.

ACKNOWLEDGEMENT

We would like to express our profound sense of gratitude to the Head, department of

Electronics and Communication Engineering, Central Institute of Technology,

Kokrajhar for the providing the access to the facilities, tools and all the resources for

successful completion of the project work. We wish to convey our gratitude to all the

faculties of department of Electronics and Communication Engineering who have

enlightened us during entire career of our technical studies. The cooperation received

from the technical staff of Electronics and Communication Engineering is thankfully

acknowledged. Lastly, we would like to thanks the researchers of various articles and

books that we have referred for making our knowledge finer and stronger.

Monalisha Saikia (Gau-C- 15/L-286)

Sonu Kumar (Gau-C-15/012)

Amit Anand (Gau-C-15/013)

Jyotishna Kurmi (Gau-C-15/017)

Binita Brahma (Gau-C-15/032

LIST OF FIGURES

1. Figure 1 : Interferer levels in received GSM Signal. Pg.1

2. Figure 2: OTA symbol representation and equivalent

model.

Pg.4

3. Figure 3: Different types of Transconductors. Pg.5

4. Figure 4: Small signal model of different OTAs for

calculating Gm (left), Rout (Right): (a), (b), (c).

Pg.6

5. Figure 5: Miller OTA and its small signal equivalent. Pg.8

6. Figure 6: Telescopic Cascode OTA and its small signal

equivalent.

Pg.8

7. Figure 7: Folded Cascode OTA and its small signal

equivalent.

Pg.9

8. Figure 8: Folded Cascode OTA and its small signal

equivalent.

Pg.10

9. Figure 9: Differential OTA circuits in CMOS : (a) Single

ended output, (b)Feed forward OTA, (c) Fully differential

OTA

Pg.11

10. Figure 10: Telescopic Cascode OTA Schematic in S-Edit. Pg.15

11. Figure 11: AC Response of Telescopic Cascode in W-Edit. Pg.16

12. Figure 12: Folded Cascode OTA in S-Edit. Pg.16

13. Figure 13: AC Response of Telescopic Cascode in W-Edit. Pg.17

14. Figure 14: Schematic of Miller OTA in S-Edit Pg.17

15. Figure 15: AC Response of Miller Cascode in W-Edit Pg.18

16. Figure 16: Folded cascode OTA in s edit Pg.20

17. Figure 17: AC Figure 16: Response of folded cascode OTA in W-

edit Pg.21

18. Figure 18: Butterworth 3rd order LPF and its magnitude

response of various order Pg.22

19. Figure 19: Diagram for writing equations Pg.23

20. Figure 20: Gm-c implementation of 3rd order butter LPF Pg.24

21. Figure 21. implementing inductor using gyrator

Pg.25

22. Figure 22: The complete filter (3rd order Butterworth using

gyrator) Pg.25

23. Figure 23: signal flow diagram of a practical biquad (LPF) Pg.26

24. Figure 24: signal flow graph of the biquad using Gm-c

integrator for LPF Pg.27

25. Figure 25: 3rd order Butterworth LPF (biquad) Pg.28

26. Figure 26: circuit diagram of biquad using op-amp in Multisim Pg.29

27. Figure 27: 3rd order Butterworth LPF in s edit Pg.31

28. Figure 28: Ac response of 3rd order Butterworth LPF in w-edit Pg.32

29. Figure 29: Ac response of 3rd order Butterworth LPF due to

transconductance variations in w-edit Pg.32

30. Figure 29: Ac sweep of biquad of op-amp and Active RC

integrator Pg.33

31. Figure 30: DC sweep analysis in s edit Pg.34

32. Figure 31: 𝒊𝒐𝒖𝒕 𝒗𝒔 𝑽𝒊𝒅 Pg.34

33. Figure 32: Test bench for noise analysis folded cascode OTA Pg.35

34. Figure 33: Noise simulation folded cascode OTA Pg.35

LIST OF TABLES

Table

No

Description of Table Pg.No

1 : Summary of Expressions of gain different transconductors

(single ended)

7

2: Summary of the different differential OTA structures.

10

3: Comparison of Simulation Results of OTAs

19

4: Simulation Results of Folded Cascode (Differential) in Tanner 21

5: Equations describing the Passive RLC Network 23

6 Comparison of the Equations of 3rd Order Passive and Active

Filters

30

7 All Simulation Results of 3rd Order Butterworth Low Pass Filter. 36

TABLE OF CONTENTS

I. Abstract

II. Acknowledgement

III. List of Figures

IV. List of Tables

1 Motivation & Introduction ......................................................................................... 1

1.1 Filters in CMOS

Technologies………………………………………………………. 2

1.2 Scope of the

Report:…………………………………………………………………. 3

1.3 Organisation of the

Thesis:………………………………………………………….. 3

2 OTA and its architectures ......................................................................................... 4

2.1 Conventional Architectures of

OTA………………………………………………... 5

2.1.1 Small signal parameters ............................................................................... 7

2.2 Classification of different types of OTA 7

2.3 Nonideal perfomances of OTA 12

2.3.1 Harmonic Distortion ................................................................................... 12

2.3.2 Intermodulation Distortion ......................................................................... 12

2.3.2 Distortion in MOS Differential OTA .......................................................... 13

3 Comparison of various architecture of OTA ........................................................... 15

3.1 Telescopic Cascode Simulation and Results .............................................. 15

3.2 Folded Cascode Simulations and Results ................................................... 16

3.3 Miller OTA Simulation and Results ........................................................... 17

4 Folded Cascode OTA........................................................................................... .... 20

4.1 Folded Cascode Simulations and Results ................................................... 21

5 Filter........................................................................................... .............................. 22

5.1 Butterworth Filter ....................................................................................... 22

5.2 Ladder Synthesis of Active filter ................................................................ 23

5.3 Gyrator based Synthesis for Gm-C filter .................................................... 24

5.4 Synthesis using Biquad ............................................................................... 26

5.5 Biquad Implemetation using Active-RC and Gm-C integrators ................. 29

6 Simulations and Results........................................................................................... 31

6.1 AC Response of 3rd Order Butterworth Filter ............................................. 31

6.2 AC Simulation of Op-Amp based Biquad .................................................. 32

6.3 Transconductance simulations .................................................................... 33

6.4 Noise Analysis of the Biquad ..................................................................... 34

Conclusion .................................................................................................................. 36

References ................................................................................................................... 37

Appendix ..................................................................................................................... 38

CHAPTER 1 Introduction

In Modern day receivers, the received signal may contain other adjacent channels with

significantly higher power level than the desired channel. A typical GSM scenario is

shown below, where the specification for the possible power levels of the neighboring

channels as a function of frequency offset (In MHz) [1].

If the adjacent channel which is 600kHz offset from the desired channel must be

attenuated by 10 dB below the desired channel to detect the information, the adjacent

channel must be attenuated by 65 dB. Since the desired channel is -98 dBm, the power

of adjacent channel, -43 dBm, should be attenuated to -108 dBm. In the case of GSM,

the desired channel has a bandwidth of only 200KHz located around 900 MHz. For the

detection of the transmitted information, the required filter must have a quality factor

Q as; 𝑄 =𝑓0

𝐵𝑊=

900𝑀𝐻𝑧

200𝑘𝐻𝑧= 4500. [1] which is impossible to realize with modern

technology. So frequency translation (down conversion) is necessary for easier

detection with feasible filters. In modern receivers, detection of information is usually

done in low IF or zero IF. The analog filters in low IF or zero IF separate the desired

channel from undesired ones and interferers, which may be orders of larger than the

Figure 1 Interferer levels in received GSM Signal.

desired signal. Accomplishing the same job without analog filters would require analog

to digital converters (ADCs) with much larger number of bits to properly digitize and

process large interferers. Therefore, analog baseband filters are needed for the proper

detection of the desired signal in radio receivers. In the design of the high-performance

electronic circuits, the use of analog filters is unavoidable. The receiver’s ability to

suppress adjacent channel interference and in-band blocking signals is directly

dependent on the channel selection filtering. As pointed out in the previous section, the

received signal contains not only the desired channel but a multitude of neighboring

channels or other interferers which must be attenuated before the detection can be done.

1.1 Filters in CMOS Technologies:

In CMOS technologies, Active RC, MOSFET-C and Gm-C filters are the most popular

baseband filters for wireless communication.

Active RC filters usually apply lossy and lossless integrators to attenuate

interferers and are still widely used in low frequency application.

MOSFET-C filters have similar architecture as active RC filters but replace

passive resistors with a triode region transistor.

Gm-C filters use transconductors and capacitors to attenuate interferers.

Because of their open loop nature, Gm-C filters have been used for high

frequency application. Each filter mentioned has its own advantages and

disadvantages in terms of speed, linearity, and tunability.

1.2 Challenges in Implementations of Filters in CMOS Technology in CMOS

Technologies:

1. For the realization of fully integrated analog filters, there are many things

which must be considered. First, the size of capacitor and resistor should be

limited. Since integrated capacitors such as poly insulator poly capacitors

or metal insulator metal capacitors occupy a large area, the size of capacitor

must be limited.

2. Frequency response of the filter should be stable, since the quality factor of

the filter is highly affected by small errors in the phase and component

variation. This means that every element in the filter should have accurate

and stable values in the presence of fabrication tolerances and temperature

variations, but this is almost impossible in an integrated circuit.

3. Analog continuous time filters should be able to handle large signal. For a

wide dynamic range required in radio receiver, large signal swings are

essential. However, these are increasingly difficult to achieve as power

supply voltages are reduced and bandwidth is increased.

4. CMOS filters are often located with data converters and digital circuits on

the same chip. In this case, noise due to clock or switching is transferred to

the analog filters through substrate or power supply line. This noise highly

degrades dynamic range and signal to noise ratio of the analog filter.

Therefore, special design and layout techniques are required to minimize

the effect of the noise.

1.4 Scope of the Report:

In this report we discuss the various topologies of CMOS OTAs for the application in

filters. Individual performance of the OTA are analysed using their small signal

parameters i.e. 𝐺𝑚 and 𝑅𝑂𝑈𝑇, Band width , Linearity. Each topology is designed in

250nm CMOS technology and their simulation results are presented.

1.5 Organization of this Thesis:

Chapter 2: Architectures of OTA in CMOS technology.

Chapter 3: Simulation and discussion of different OTAs in 250nm CMOS

Technology.

Chapter 4: Summary and Conclusion: summarizes the report and gives

concluding comments on the presented concept.

Chapter 5: Synthesis of Active filters from the Passive RLC section

Chapter 6: Simulation of 3rd order Gm-c Filter in Tanner EDA.

CHAPTER 2 An OTA is a voltage controlled current source (VCCS) type of amplifier where output

current is proportional to the input voltage. The basic difference of an OTA from an

Op-Amp is that output node of the OTA provide very high output resistance, where as

Op-Amp gives low output impedance. OTAs are used in open loop manner, where as

Op-Amps are mostly used in closed loop [2]. More comparative features are listed in

the Appendix.

Some of the key features of the OTA are their fast speed in comparison with the

conventional low output impedance op-amp and their transconductance tunability

(Since 𝐺𝑚 ∝ √2. 𝐼𝐵𝐼𝐴𝑆). For a filter to be designed for multi-standard wireless

applications tunability of the filter is highly desired which is achieved easily through

the tunable 𝐺𝑚.The Internal nodes of an OTA i.e. nodes except input and output nodes

offer low impedance, so it can operate upto very high frequencies (upto GHz), however

these low impedance and parasitic capacitance cause a nonzero phase shift known as

excess phase shift (𝜑).Out of all these merits, OTAs offer limited linearity performance

compared to Op-Amps as is a since the transconductors operate in an open loop.

The main characteristics of practical OTA are:-

1. Limited linear input voltage range.

2. High bandwidth.

3. Finite signal to noise ratio (S/N) ratio.

4. Very high output impedance.

V2

G m

V1 i abc

i o

GND1

V1

V2 G m ( V 1 - V2)

i o

Figure 2 OTA symbol representation and equivalent model

The transconductance bias dependence allows several decades of tuning for

transconductance with MOS transistor operating in weak inversion and about two

octaves for transistor operating in strong inversion. For open loop application OTAs

are used as multipliers, nonlinear circuits and for closed loop applications discrete-time

based (switched-capacitors) circuits [2].

2.1 Conventional Architectures

An ideal transconductance amplifier is an infinite bandwidth voltage controlled current

source , with an infinite input and output impedance [2], however the CMOS OTAs

provide limited output impedance due finite value of 𝑟𝑑𝑠 = (1𝜆. 𝐼𝐷𝑆

⁄ ) 𝑜𝑟 [𝑔𝑑𝑠1 =

𝜆. 𝐼𝐷𝑆] and limited value of transconductance 𝐺𝑚 limited by power dissipation (𝐼𝐵𝐼𝐴𝑆)

and size of the chip (W/L of all MOSFETs). We will now discuss some of the basic

OTAs implemented in CMOS and compare their performances as in the figures shown

in below (Fig. 3).

ioIb

M1vin

io

M1

M2

Ib

vb

vin

io

M1

M2

Ib

vb

vin

A

vo1

(a) (b) (c)

ioM1

M2

Ib

Ib2

vin vb

1:1io

Ib

(d) (e)

Figure 3 Different types of Transconductors [2]: (a) Single transistor (Inverting ), (b) Cascoded, (c) Gm-

boosted Cascode, (d) Folded Cascode, (e) Current Mirror Cascode.

To compare the performances of the different OTAs shown above, we take the help of

the small signal models to calculate the short circuit transconductance parameter and

output resistance. In Figure 4 (a), small signal model for single transistor

transconductor in Figure 3. (a) is shown, where the left part of the figure shows the

method of calculating the short-circuit transconductance and right part shows the

method of deriving the output resistance [4].

(a)

(b)

Figure 4 Small signal model of different OTAs for calculating Gm (left), Rout (Right): (a), (b), (c)

(c)

Small signal parameters:-

To find the transconductance , we evaluate the ratio of small signal output current to

that of the small signal input voltage applied and can be expressed as;

𝐺𝑚= 𝑖𝑜𝑢𝑡

𝑣𝑖𝑛|

𝑂𝑢𝑡𝑝𝑢𝑡 𝑛𝑜𝑑𝑒 𝑖𝑠 𝑠ℎ𝑜𝑟𝑡𝑒𝑑 𝑡𝑜 𝑔𝑟𝑜𝑢𝑛𝑑 (1)

Similarly the output resistance (𝑅𝑂𝑈𝑇) is derived by connecting a voltage source 𝑉𝑋 at

the output node by deactivating all the independent small signal sources and measuring

the current 𝐼𝑋 flowing into the output node.

𝑅𝑂𝑈𝑇 =𝑉𝑋

𝐼𝑋|

𝑖𝑛𝑑𝑒𝑝𝑒𝑛𝑑𝑒𝑛𝑡 𝑠𝑚𝑎𝑙𝑙 𝑠𝑖𝑔𝑛𝑎𝑙 𝑠𝑜𝑢𝑟𝑐𝑒𝑠 𝑑𝑒𝑎𝑐𝑡𝑖𝑣𝑎𝑡𝑒𝑑 (2)

Following these methods and taking the help of respective figure shown in Figure 4,

we have summarised the expressions for all the basic architectures.

Table 1 Summary of Expressions of Gain of Transconductors

Structure/Fig. 𝑹𝒐𝒖𝒕 Gm Gain(Gm × 𝑹𝒐𝒖𝒕)

Simple/3(a) 1/gds1 𝑔𝑚1 𝑔𝑚1

𝑔𝑑𝑠1

Cascode/3(b) 𝑔𝑚2

𝑔𝑑𝑠1𝑔𝑑𝑠2 𝑔𝑚1

𝑔𝑚1𝑔𝑚2

𝑔𝑑𝑠1𝑔𝑑𝑠2

Enhanced/3(c) 𝐴𝑔𝑚2

𝑔𝑑𝑠1𝑔𝑑𝑠2

𝑔𝑚1 (1+A) 𝐴 𝑔𝑚2𝑔𝑚1 (1 + A)

𝑔𝑑𝑠1𝑔𝑑𝑠2

Folded/3(d) 𝑔𝑚2

𝑔𝑑𝑠1𝑔𝑑𝑠2 𝑔𝑚1 𝑔𝑚2𝑔𝑚1

𝑔𝑑𝑠1𝑔𝑑𝑠2

In fig 1a, the single input real transconductor is a MOS driver transistor M1 operating

in saturation region and it has a drawback of low output impedance .

2.2 Classification of different types of OTAs:

Group of transconductance amplifier is discussed below.

Miller OTA:

The circuit diagram is shown in Fig. 6 in which NMOS M1 & M2 are acting as a input

of the differential pair and the PMOS transistors M2 and M3 forming a current mirror

circuit acting as active load. The main reason behind this current mirror load instead of

resistor is to reduce chip area. The tail current is used to control the biasing.

Telescopic OTA:

Telescopic OTA shown in Figure 7 comprises of 8 MOSFETS and a tail current source,

out of which M1,M2,M3,M4 are pMOS and M5,M6,M7,M8 are nMOS. It consists of

M7 and M8 as the driver transistors which carry the differential input signal. The

Telescopic OTA is biased with 𝐼𝐵𝐼𝐴𝑆 current.Vbias2 and Vbias3 are biasing voltages

for the pMOS transistors and Vbias4 is used for nMOS pair M5 and M6.

Folded Cascode OTA (Figure 8):

It consists of two differential input pairs with the same type of transistors, M1-M2. The

amplification can be obtained with signal applied to M1 and M2 of the OTA ensuring

M1

M2

GND2

Vin+

Vout

Iout

Vin-

Itail

gm1vgs1 r02

GND1

1/gm3

GND2

+

-

Vin

vgs2

r01

vx

Figure 6 Miller OTA and its small signal equivalent.

Vout-

Vbias3

GND4

Vbias2

Vbias4

Vbias1

Vout+

Vin+Vin-

Telescopic cascode

M5 M6

M7

M4

M1

M3

M2

M8

M9 gm7vgs7 r07

GND1

gm5vgs5 ro5

GND2

+

-

Vin

vgs1

Isc

X

y

Figure 7 Telescopic Cascode OTA and its small signal equivalent to calculate the Gm.

all transistors in the saturation region . Transistors MP3 and MP4 work as Common

Gate amplifiers which are of PMOS type and folding is achieved with the current

source implemented using MP1 and MP2. It is cascade of a differential

transconductance stage which is designed by connecting the output of a Common

Source stage to a Common Gate stage.

Since the folded-cascode OTA presents a single parasitic pole and relatively large DC

gain, it is commonly used for high-frequency applications. For high speed applications,

fast settling OTAs are required, which demand both high UGB and Power.

The small signal model of the left half of the circuit is shown below in Figure 9.

MP1 MP2

MP3 MP4

M3 M4

M5 M6

M1 M2

M0

GND1GND2

Vbias1

Vbias2

Vbias3

Vbias4

Vout-

Vin- Vout+Vin+

Vb

P-1

Figure 8 Folded Cascode OTA

Table 2 Summary of Expressions for the differential OTA structures

Topology Output resistance Gm Voltage Gain

Miller (𝑔𝑚2𝑟02𝑟01)||

1

𝑔𝑚3

𝑔𝑚2 𝑔𝑚2(𝑔𝑚2𝑟02𝑟01)||

1

𝑔𝑚3

Telescopic

cascode

(𝑔𝑚5𝑟05𝑟07)||

(𝑔𝑚3𝑟03𝑟01)

𝑔𝑚7 𝑔𝑚7(𝑔𝑚5𝑟05𝑟07)||

(𝑔𝑚3𝑟03𝑟01)

Folded

cascode

(𝑔𝑚3𝑟03𝑟05)||

(𝑔𝑚𝑝3𝑟0𝑝3(𝑟0𝑝1 ||𝑟01))

𝑔𝑚2 𝑔𝑚2(𝑔𝑚3𝑟03𝑟05)||

(𝑔𝑚𝑝3𝑟0𝑝3(𝑟0𝑝1 ||𝑟01))

gm2vgsro2 ro p1

GND1

gmp3vgs

ro p3

Isc,out

GND2

+

Vgs

-

+

Vgs

-

ro1

GND3

2

r0p3

R0p1||r02

GND6

gm3Vgs3 r03

GND7

r05

vx

GND8

P

Q

vs1

vs2

Ix

gmp3Vgsp3

Figure 9 Folded Cascode OTA and its small signal equivalent to find Gm and Rout.

(b)

(c)

a. Simple differential OTAs

b. Balanced OTAs

c. Conventional fully differential OTA

M1

M2

GND2

Vin+

Vout

Iout

Vin-

Itail

(a) (b)

(c)

Figure 9 Differential OTA circuits in CMOS : (a) Single ended output, (b)Feed forward OTA, (c) Fully

differential OTA

2.3 Non-Ideal Performances of OTAs:

2.3.1 Harmonic Distortion (HD)

If the fully differential transconductor with inputs; 𝑉2 = 𝑉1+ and 𝑉1 = 𝑉1−presents

nonlinear characteristics, the output current, , can be expressed by the following

expansions:

𝑖𝑜− = 𝑖𝑜1= 𝐼𝐵1

+ 𝑎1(𝑉1 − 𝑉2) + 𝑎2(𝑉1 − 𝑉2)2 + 𝑎3(𝑉1 − 𝑉2)3 + … … … … … .. (3)

𝑖𝑂+ = 𝑖𝑜2= 𝐼𝐵1

+ 𝑎1(𝑉2 − 𝑉1) + 𝑎2(𝑉2 − 𝑉1)2 + 𝑎3(𝑉2 − 𝑉1)3 + … … … … … .. (4)

Where 𝐼𝐵1 is the amplifier bias current. It is evident from these expressions that the

even harmonic distortion components appear at the output with the same amplitude and

same phase, and they ideally cancel each other when the differential output current is

processed. The main advantage of fully differential topology are due to

symmetry,making the structure less sensitive to common mode signals.

The 𝑛𝑡ℎ harmonic distortion (𝐻𝐷𝑛)component in the output current can be defined as

the ratio of the component of frequency n𝜔 to the one at the fundamental 𝜔.

𝑯𝑫𝟐 =𝟏

𝟐

𝒂𝟐

𝒂𝟏 𝑼 (5)

𝑯𝑫𝟑 =𝟏

𝟒

𝒂𝟑

𝒂𝟏𝑼𝟐 (6)

It is important to note that HD is proportional to U, where U is the peak or maximum

value of the signal applied and𝐻𝐷3 to 𝑈2. These relationships hold true for all values

of U, which are not too large and this is the region where the so-called low-distortion

conditions are valid. For even larger values of U, the values of 𝐻𝐷2and 𝐻𝐷3flatten off

with increasing U.

2.3.2 Inter-Modulation Distortion (IMD):

Application of the sum of two cosine (sine) waveforms of frequencies 𝜔1 and 𝜔2which

are close enough in the frequency spectrum and both of same amplitude U at the input

gives rise to output signal components at all combinations of 𝜔1, 𝜔2 and their

multiples.

Second-order intermodulation distortion (𝐼𝑀2) is defined by the ratio of the component

at frequency 𝜔1 ± 𝜔2 to the one at 𝜔1 or 𝜔2. Under low-distortion conditions:

𝑰𝑴𝟐 =𝒂𝟐

𝒂𝟏 𝑼 (7)

Third-order intermodulation distortion (𝐼𝑀3) can be detected at the frequencies

2𝜔1 ± 𝜔2 and2𝜔2 ± 𝜔1. It is given by the ratio of the component at frequency

2𝜔3_𝜔1 (or one of the other three frequencies), which is 3𝑎3𝑈3, to the fundamental,

which is 𝑎1U, as given by

𝑰𝑴𝟑 =𝟑

𝟒.

𝒂𝟑

𝒂𝟏.𝑼𝟐 (8)

Comparison of the four equations above shows that:

𝑰𝑴𝟐 = 𝟐𝑯𝑫𝟐& 𝑰𝑴𝟑 = 𝟑𝑯𝑫𝟑 (9)

For a MOS transistor, the transfer characteristic 𝐼𝐷𝑆~𝑉𝐺𝑆 is quadratic and not

exponential unlike BJT. Less distortion is thus expected. The drain current 𝐼𝐷𝑆 and gate

to source voltage 𝑉𝐺𝑆 of a MOS transistor is written as;

𝐼𝐷𝑆 = 𝛽(𝑉𝐺𝑆 − 𝑉𝑇𝐻)2 (10)

in which 𝛽 is the process parameter, which includes thesize(𝑊

𝐿), and µ𝑛. 𝐶𝑜𝑥 and

𝑉𝑇𝐻is the threshold voltage.The transistor is biased at a specific dc value of 𝑉𝐺𝑆 .

A small variation of this voltage causes a small variation in drain current. Therefore,

the small signal current 𝑖𝑝 can be written in terms of its Taylor's Series expansion around

its DC current 𝐼𝐷𝑆 as;

𝑖𝑝 =𝐼𝑑𝑠𝑝

𝐼𝐷𝑆=

2𝑉𝐺𝑆𝑃

𝑉𝐺𝑆−𝑉𝑇+

1

4(

2𝑉𝐺𝑆𝑃

𝑉𝐺𝑆−𝑉𝑇)

2 (11)

Comparing this equation with equation(5),we get

𝑰𝑴𝟐 = 𝟐𝑯𝑫𝟐 =𝟏

𝟐.

𝑽𝑮𝑺𝑷

𝑽𝑮𝑺−𝑽𝑻=

𝑰𝑷

𝟒and, IM3=0 (12)

2.3.3 Distortion in MOS Differential OTA:

The transfer characteristic of a differential pair with MOST is symmetrical around

the origin. No second-order distortion can thus occur. Since a single MOST amplifier

does not generate third-order distortion, it will be interesting to examine what distortion

performance can be obtained with a MOST differential amplifier. The differential

output current 𝑖0𝑑is again twice the ac current in each transistor. Thus ,the relative

current swing is given by;

𝑖𝑝 =𝐼𝑜𝑑𝑝

𝐼𝐵=

𝑉𝑖𝑑𝑝

𝑉𝐺𝑆−𝑉𝑇−

1

8(

𝑉𝑖𝑑𝑝

𝑉𝐺𝑆−𝑉𝑇)

3

(13)

Comparing this with equation(2),we getthe following expression;

𝑰𝑴𝟑 = 𝟑𝑯𝑫𝟑 =𝟑

𝟑𝟐(

𝑽𝑰𝒅𝒑

𝑽𝒈𝒔𝟏−𝑽𝑻)

𝟐

=𝟑

𝟑𝟐𝒊𝒑

𝟐 (14)

All the above equations give the relation between the bias parameters and the signal

amplitude levels. These relations can be applied to the individual amplifiers shown

above to get the Harmonic and Intermodulation distortion terms. In this report we focus

on the small signal performance of the above topologies of differential input OTAs in

CMOS, so small signal equivalent of the respective OTAs are shown below.

CHAPTER 3

Comparison of various Architectures of OTA:

In order to understand the theoretical expressions and have a fair comparison between

the different OTA topologies simulation are performed using the Tanner S-EDIT

simulator and BSIM3v3 transistor model(level 49) for the AMS 0.25μm CMOS

technology.

3.1 Telescopic cascode Simulation:

Figure 10 Telescopic Cascode OTA Schematic in S-Edit

AC ANALYSIS:

3.2 Folded cascode:

3.4 AC ANALYSIS

Figure 11 AC Response of the TelescopicCascoded OTA

Figure 12 Folded Cascode OTA in S-Edit

3.4 Miller’s OTA:

AC Analysis of Miller OTA:

Figure 13 AC Response of Folded Cascode OTA in w-edit.

Figure 14 Schematic of Miller OTA in S-Edit

Discussions:

Figure 11, 13 and 14 shows the frequency response of 3 different topologies of the

OTA The DC gain of folded cascode is (shown in Fig 13) 33.4 dB with unity Gain

Bandwidth of 255.99 MHz for a load capacitor value of 1pF, -3dB Bandwidth of

360 MHz while achieving the phase margin of 82º. The DC gain of telescopic cascode

shown in Figure 11 15 dB with unity Gain Bandwidth of 159 MHz for a load capacitor

value of 10 pF, -3dB Bandwidth of 245 MHz while achieving the phase margin of

95º.By increasing the value of (W/L) ,we can further increase the gain of these OTA

with the low power consumption area will be increased and increased parasitic

capacitance will also cause the fall in BW.

From these simulations we can observe that the telescopic cascode OTA provide high

output resistance and high band width, but it requires the double the transistors to that

of a Miller OTA. So area of the OTA will increase and also voltage swing will be less.

Folded cascode can operate with higher swing and same gain but Power dissipation

increases due to the folding node. Miller OTA gives lesser gain , but has a simpler

design. The linearity aspect of these OTA would be studied in future.

Figure 15 AC response of miller OTA in W-edit

Table 3 Comparison of Simulation Results

Parameters Miller OTAs Telescopic OTAs Folded OTAs

Unity gain

frequency (MHz)

401.13 159 255.99

Phase margin (º) 71 95 82

Gain (dBV) 9.4 14.14 33.4

Power (mW) 23 8 0.739

CHAPTER 4

Folded Cascode OTA

The folded Cascode OTA is in a way a compromise between the miller OTA and the

telescopic Cascode OTA. It permits low supply voltage, still having a rather high output

voltage swing and the input and output common mode levels can be designed to be

equal. Its gain is higher than for the miller OTA and its speed is lower than for the

telescopic Cascode OTA, which makes it a good compromise between these two

OTAs.

The applied voltage is 1.8 v (vdd) which having power consumption of 739.08𝜇𝑤. The

input voltage which have applied in folded cascode OTA is vdd/2 ie; 0.9 v.Load

capacitor used is 1pf.

Figure 16 Folded Cascode OTA in S-Edit

Table 4Simulation Results of Folded Cascode (Differential) in Tanner

Parameters Descriptions

Technology 250nm CMOS

Unity gain frequency 255.99 MHZ

Phase margin 𝟏𝟖𝟎° − 𝟗𝟖° = 𝟖𝟐°

-3db frequency 10 MHZ

Power(mW) 739.08µW

Figure 17 AC response of Folded cascode OTA in W-edit

CHAPTER 5

5.1 Butterworth filter

Butterworth filters [5] are suitable for applications in which ripples in the pass and stop

band are intolerable. For this reason, the Butterworth filter is also called a “maximally

- flat amplitude” filter. It exhibits a nearly flat passband with no ripple. The roll-off is

smooth and monotonic, with a low-pass or high pass roll-off rate of ±20 dB/decade (±6

dB/octave) for every pole. Thus, a 5th-order Butterworth low-pass filter would have an

attenuation rate of 100 dB for every factor of ten increase in frequency beyond the

cutoff frequency. It also has a reasonably good phase response.

5.2 Ladder synthesis [6]:-

Using MOSFET-C integrators, the ladder simulation method for the MOSFET-C

approach is entirely similar to the active-RC. Ladder synthesis is realized by the LC

ladder structure with known component values. The LC active simulation proceeds by

deriving the signal flow graph equation or by writing the branch currents and node

equations of the ladder along with the respective V-I relationships. The scaling factor

in this case is the design Transconductance 𝑔𝑚. The source and the load resistors of the

LC ladder network have the value of 1

𝑔𝑚. The equations are implemented with the

integrators in fully differential form and all the integrators capacitors grounded. All the

Figure 18 -Butterworth 3rd Order Low Pass Filter and its Magnitude Response for various Orders

signals in the MOSFET-C circuits are voltages, which in turn produce current summed

at the op-amp inputs, and that the integration constant must be time rather than

capacitance. This is achieved scaling the equation by a resistor R. An often cited

advantage of the MOSFET-C techniques is the reduced sensitivity to parasitic

capacitor. MOSFET-C circuits promise to become increasingly attractive in the future.

Table5 Equations describing the Passive RLC Network

Parameter Scaled equation Remarks

𝐼𝐿1 =𝑉𝑆 − 𝑉2

𝑠𝐿1 𝑉𝐿1 =

𝐼𝐿1

𝑔𝑚=

𝑔𝑚. 𝑉𝑆 − 𝑔𝑚. 𝑉2

𝑠𝐿1𝑔2𝑚

𝑔𝑚𝑣 form is easy for

transconductor implementation.

𝐼𝐿3

=𝑉2 − 𝑉𝑜𝑢𝑡

𝑠𝐿3

𝑉𝐿3 =𝐼𝐿2

𝑔𝑚=

𝑔𝑚. 𝑉2 − 𝑔𝑚. 𝑉𝑜𝑢𝑡

𝑠𝐿3𝑔2𝑚

Current integrated to voltage

through integrator (𝑔𝑚 − 𝑐).

𝑉2 =𝐼𝐿1 − 𝐼𝐿3

𝑠𝐶2

𝑉2 =𝑔𝑚 (

𝐼𝐿1

𝑔𝑚−

𝐼𝐿3

𝑔𝑚)

𝑠𝐶2

=𝑔𝑚. 𝑉𝐿1−𝑔𝑚. 𝑉𝐿3

𝑠𝐶2

No internal nodes are available in

current form.

𝑉𝑜𝑢𝑡 = 𝐼𝐿3. 𝑅𝐿 𝑉𝑜𝑢𝑡 =

𝐼𝐿3

𝐺𝐿=

𝑉𝐿3. 𝑔𝑚

𝐺𝐿

Resistor 𝑅𝐿 is using 𝑔𝑚 block in

unity feedback.

The implemented Gm−C filter from the LC ladder (shown above in Fig. 1) is shown in

Fig. 2. The first gm yields a current gm.(Vs−V2) which gets integrated through the

capacitor of value L1.gm2 as written in Table, whereas the last gm works as a resistor

Figure 19 Diagram for Writing Equations

1. 𝑰𝑳𝟏 =𝑽𝑺−𝑽𝟐

𝒔𝑳𝟏

2. 𝑰𝑳𝟑 =𝑽𝟐−𝑽𝒐𝒖𝒕

𝒔𝑳𝟑

3. 𝑽𝟐 =𝑰𝑳𝟏−𝑰𝑳𝟑

𝒔𝑪𝟐

4. 𝑽𝒐𝒖𝒕 = 𝑰𝑳𝟑. 𝑹𝑳

ofvalueRL.

5.3 Gm-C filter synthesis using gyrator:-

We can have another simpler method of implementing LC filter, by replacing passive

inductor with active inductors which are also called gyrators. A gyrators is simply

represented as two transconductor connected back to back. A gyrator-C network is

said to be lossless when both the input and output impedances of the transconductor of

the network are infinite and the transconductances of the transconductors are constant.

When one port of the gyrator is connected to a capacitor, the network is called the

gyrator –C network[8]. The problem of these active inductor is that they have a limited

frequency range in which they can behave as inductors. In addition to this, they are

thought as linear, which they are not. Non idealities of the transconductors also affect

the performance of inductive behavior i.e. noise, Band width, finite output impedance,

etc.

- -

---

-

gm

gm gm

gm

gm

L1.gm2

L3.gm2

Vs

Vout

VL1 VL3

V2

C2

Figure 20 Gm-C implementation of 3rd Order Butterworth Low Pass filter

The inductors L1 and L3 in Fig 1 can be replaced as capacitively loaded gyrators

(Active Inductors). It is obtained by first converting the voltage source to a current

source (Norton transformation, which also converts series source resistor R into shunt

resistor. The first OTA (Gm block) in Figure 4 performs V-I conversion, where as last

one implements a resistor R.

+

- gm1

+

-gm2

C

VX

IX

ZIN

L= C/gm1.gm2VX

Vout

Figure 21 Implementing Inductor using Gyrators

-

+

+

-

-

+

+

-

-

+

+

-

-

+

+

-

-

+

+

-

-

+

+

-

-

+

+

-VS

L1.gm2

2C2

2C2

L1.gm2

L3.gm2

L3.gm2

Voutgm

gm gm gm gm gm gm

Figure 22 The complete filter (3rd Order Butterworth) using 2 gyrators

5.4 Synthesis using Biquad:-

The biquad is second-order Quadratic equation described generally as;

H(s) =𝑎1.𝑠2+𝑎2.s+𝑎3

𝑏1.𝑠2+𝑏2.𝑠+𝑏3 (5.1)

The coefficients of numerator a1, a2, a3 can be chosen to yield a low-pass, band-pass,

or high-pass filter responses. i.e. if a1, a2 both become 0, then a low pass filter (LPF)

transfer function is produced, if a2, a3 becomes 0, then a Band pass filter function is

realized, and for a1, a3= 0, an HPF is realized. To realize higher order filters, biquad

sections can be cascaded [4], [7]. i.e. a 3rd order filter can be implemented by making

cascade connection of a biquad (2nd order) and a 1st order filter. And a 5th order filter

can be made by cascading 2 biquads and a 1st order filter. Our focus to implement a

3rd order Butterworth LPF can also be achieved using a biquad and a first order

integrator.

By looking at the above signal flow graph we can have the expression for the

Output at 1st summing point as;

𝑣𝑥 = 𝑣𝑖𝑛 (𝑘𝑜

𝜔2𝑜) − 𝑣𝑜𝑢𝑡 (5.2)

, Output at 2nd summing point is given by;

𝑣𝑦 = (𝑣𝑖𝑛 (𝑘𝑜

𝜔2𝑜) − 𝑣𝑜𝑢𝑡)

𝜔𝑜

𝑠−

𝑣𝑜𝑢𝑡

𝑄 (5.3)

and the Output at last block is given by;

Vin

Vout

K0/w0

2w0/s

-1/Q

w0/s

-1

Fig 23 Signal flow diagram of a Practical Biquad (LPF)

biquad

𝑣𝑜𝑢𝑡 = {(𝑣𝑖𝑛 (𝑘𝑜

𝜔2𝑜) − 𝑣𝑜𝑢𝑡)

𝜔𝑜

𝑠−

𝑣𝑜𝑢𝑡

𝑄}

𝜔𝑜

𝑠 (5.4)

(𝑣𝑖𝑛𝑘𝑜

𝑠𝜔𝑜−

𝑣𝑜𝑢𝑡𝜔𝑜

𝑠−

𝑣𝑜𝑢𝑡

𝑄)

𝜔𝑜

𝑠= 𝑣𝑜𝑢𝑡 (5.5)

𝑣𝑖𝑛𝑘𝑜

𝑠𝜔𝑜−

𝑣𝑜𝑢𝑡𝜔𝑜

𝑠−

𝑣𝑜𝑢𝑡

𝑄=

𝑠𝑣𝑜𝑢𝑡

𝑄 (5.6)

𝑣𝑖𝑛𝑘𝑜

𝑠𝜔𝑜= 𝑣𝑜𝑢𝑡 (

𝜔𝑜

𝑠+

1

𝑄+

𝑠

𝜔𝑜) (5.7)

𝑣𝑖𝑛𝑘𝑜

𝑠𝜔𝑜= 𝑣𝑜𝑢𝑡 (

𝑄𝑠2 + 𝑠𝜔𝑜 + 𝜔𝑜2𝑄

𝜔𝑜𝑄𝑠)

𝑣𝑖𝑛𝑘𝑜 =𝑣𝑜𝑢𝑡

𝑄(𝑄𝑠2 + 𝑠𝜔𝑜 + 𝜔𝑜

2𝑄) (5.8)

𝒗𝒐𝒖𝒕(𝒔)

𝒗𝒊𝒏(𝒔)|

𝒃𝒊𝒒𝒖𝒂𝒅=

𝒌𝒐𝑸

𝑸𝒔𝟐+𝒔𝝎𝒐+𝝎𝒐𝟐𝑸

=𝒌𝒐

𝒔𝟐+𝒔𝝎𝒐

𝑸+𝝎𝒐

𝟐 (5.9)

For calculating the transfer function of Bi-quad LPF, we can write the currents for the

transconductors as;

𝑖1 = 𝑣𝑜𝑢𝑡(−𝑔𝑚3) = −𝑔𝑚3𝑣𝑜𝑢𝑡 (𝑖1 is the current at the output of 𝑔𝑚3 ) (5.10)

𝑖2 = 𝑣𝑖𝑛(−𝑔𝑚1) = 𝑔𝑚1𝑣𝑖𝑛 (𝑖2 is the current at the output of 𝑔𝑚1 ) (5.11)

At the output node applying KCL, we can have;

𝑖𝑠𝑢𝑚1 = 𝑖1 + 𝑖2 = 𝑔𝑚1𝑣𝑖𝑛 − 𝑔𝑚3𝑣𝑜𝑢𝑡 (5.12)

gm2

-

gm4

-

gm3

+gm1

+

-

-

+

Vout

Vin

isum1

i1

i2

i5

i4

isum2

Vint2+

C1

C2

Fig 24 Biquad using Gm-C integrators for LPF

So now we can we can pass this current through an integrating capacitor C1 to have an

equation given by;

𝑣𝑖𝑛1 =𝑖𝑠𝑢𝑚1

𝑐1𝑠=

𝑔𝑚1𝑣𝑖𝑛−𝑔𝑚3𝑣𝑜𝑢𝑡

𝑐1𝑠 (5.13)

(𝑖4 is the current at the output of 𝑔𝑚2)

𝑖4 = 𝑣𝑖𝑛1(𝑔𝑚2) = 𝑔𝑚2𝑣𝑖𝑛1 (5.14)

(𝑖5 is the current at the output of 𝑔𝑚4 )

𝑖5 = 𝑣𝑖𝑛2(−𝑔𝑚4) = 𝑔𝑚4𝑣𝑖𝑛2 (5.15)

Applying KCL at node2;

𝑖𝑠𝑢𝑚2 = 𝑖4 + 𝑖5 = 𝑔𝑚2𝑣𝑖𝑛1 − 𝑔𝑚4𝑣𝑖𝑛2 (5.16)

(voltage across output capacitor C2) 𝑣𝑖𝑛2 = 𝑣𝑜𝑢𝑡 =𝑖𝑠𝑢𝑚2

𝑐2𝑠 (5.17)

𝑣𝑜𝑢𝑡 =𝑔𝑚2𝑣𝑖𝑛1−𝑔𝑚4𝑣𝑖𝑛2

𝑐2𝑠=

𝑔𝑚2𝑣𝑖𝑛1−𝑔𝑚4𝑣𝑜𝑢𝑡

𝑐2𝑠 (5.18)

𝑣𝑜𝑢𝑡 (1 +𝑔𝑚4

𝑐2𝑠) =

𝑔𝑚2𝑣𝑖𝑛1

𝑐2𝑠=

𝑔𝑚2(𝑔𝑚1𝑣𝑖𝑛 − 𝑔𝑚3𝑣𝑜𝑢𝑡)

𝑐1𝑐2𝑠2

𝑣𝑜𝑢𝑡(𝑐1𝑐2𝑠2 + 𝑔𝑚4𝑐1𝑠 + 𝑔𝑚2𝑔𝑚3) = 𝑔𝑚1𝑔𝑚2𝑣𝑖𝑛

𝑣𝑜𝑢𝑡(𝑠)

𝑣𝑖𝑛(𝑠)=

𝑔𝑚1𝑔𝑚2

𝑐1𝑐2𝑠2+𝑔𝑚4𝑐1𝑠+𝑔𝑚2𝑔𝑚3 (5.19)

We can simplify above equations as;

gm2

-

gm4

-

gm3

++

-

Vin

isum1

i1

i2

i5

i4isum2

Vint2+

C1

C2

+gm5

gm6

--

+

Vout

C3

-

V

V

V

gm1

2nd

Order (Biquad) 1st Order

Figure 25 3rd order Butterworth low pass filter (biquad)

𝑯(𝒔)|𝒃𝒊𝒒𝒖𝒂𝒅 =𝒈𝒎𝟏𝒈𝒎𝟐

𝒄𝟏𝒄𝟐⁄

𝒔𝟐+𝒔𝒈𝒎𝟒

𝒄𝟐+

𝒈𝒎𝟏𝒈𝒎𝟑𝒄𝟏𝒄𝟐

(5.20)

5.5 Biquad using Op-Amp and Active-RC

Integrator [7]:

Circuit Diagram for Opamp based biquad which is cascaded with first order filter to

get a 3rd order LPF circuit is shown below in Fig. 24. Here three Inverting Amplifiers,

two Summing Amplifiers and two Integrators are used for Biquad filter (based on

signal flow diagram of Biquad in fig 21) and one integrator at last is working as first

order filter.

Figure 26 circuit diagram of 3rd Order filter using Op-Amp-RC biquad and 1st order integrator in MULTISIM

Table 6 Comparison of the Equations of 3rd Order Passive and Active Filters

FILTERS TF(S) PASS BAND GAIN 𝒇𝒄

PASSIVE 𝑹

𝒔𝟑(𝑳𝟏𝑪𝟐𝑳𝟑) + 𝒔𝟐(𝑳𝟏𝑪𝟐𝑹) + 𝒔(𝑳𝟏 + 𝑳𝟑) + 𝑹

𝑹𝑹⁄ 251

MHZ

GM-C (𝑔𝑚1𝑔𝑚2𝑔𝑚5 𝑐12𝑐2⁄ )

𝑠3 + 𝑠2 (𝑔𝑚4

𝑐2+

𝑔𝑚6

𝑐1) + 𝑠 (

𝑔𝑚4𝑔𝑚6

𝑐1𝑐2+

𝑔𝑚3𝑔𝑚4

𝑐1𝑐2) +

𝑔𝑚4𝑔𝑚3𝑔𝑚6

𝑐12𝑐2

𝒈𝒎𝟏𝒈𝒎𝟐𝒈𝒎𝟓

𝒈𝒎𝟒𝒈𝒎𝟑𝒈𝒎𝟔

85M

HZ

ACTIVE

- RC

−𝑹𝟗𝑹𝟏𝟑𝑹𝟏𝟏𝑹𝟐𝑹𝟒𝑹𝟓𝑹𝟖𝑹𝟏𝟔

(𝟏 + 𝑺𝑹𝟏𝟔𝑪𝟑)(𝑹𝟑𝑹𝟏𝑹𝟏𝟓)(𝑺𝟐𝑪𝟏𝑪𝟐𝑹𝟏𝟎𝑹𝟏𝟑𝑹𝟏𝟏𝑹𝟒𝑹𝟔𝑹𝟐𝑹𝟖 + 𝑺𝑪𝟏𝑹𝟏𝟏𝑹𝟒𝑹𝟔𝑹𝟕 + 𝑹𝟏𝟑𝑹𝟖)

−𝑹𝟗𝑹𝟏𝟑𝑹𝟏𝟏𝑹𝟐𝑹𝟒𝑹𝟓𝑹𝟖

𝑹𝟑𝑹𝟏𝑹𝟏𝟑𝑹𝟖

424K

HZ

CHAPTER 6 Simulations and Results: 6.1 AC Analysis

In figure 27, the Butterworth LPF (biquad) response for 1.8v supply voltage and 𝑐𝑙 =

1.35𝑝𝐹 is shown. Here the open loop gain is approximately 0dB and attenuation rate

is 51dB/decade In this circuit it consists folded cascode OTA. Each symbol represents

a folded cascode OTA.

Figure 27 3rdorder Butterworth LPF in S-edit

Fig 28 are the frequency response of 3rd order Butterworth LPF which having -3dB

frequency of 85 MHz.

6.2 SIMULATION OF OP-AMP BASED BI-QUAD:

The simulation of 3rd order LPF using Op-amp is shown above. After simulation we

Figure 28 AC response of 3rd order Butterworth LPF in W-edit

Figure 29 AC sweep of Biquad of Op-Amp and Active RC Integrator

got Cut Off frequency(fc) of about 424 kHz, Stopband of 1.67 MHz and Attenuation rate is -60 dB/decade.

6.3 DC SIMULATION In order to know the output current without the presence of signal we give only one

input of 0.9v to M5 and 0v to M7 .The output is taken from drain terminal of the

PMOS3 and NMOS2.An Ammeter is connected at the output which, we measure the

output current of 200µA.

Figure 30 DC sweep analysis in S-Edit

6.4 NOISE SIMULATION Here noise simulation is done to measure the input referred noise in the band of interest

i.e. upto 250MHz. The maximum rms noise voltage obtained from the simulation is is

8.31nv/√𝐻𝑧 at 7 GHz.

Figure 31 𝑰𝒐𝒖𝒕 Vs Vgs

Figure 32 Test bench for Noise analysis folded cascade OTA

Table 7 All Simulation Results of 3rd Order Butterworth Low Pass Filter.

TECH ACTIVE(GM-C) PASSIVE

PASS BAND EDGE 85MHz 251MHz

STOP BAND

EDGE

660MHz ----

ATTENUATION

RATE

-60 dB/decade -60 dB/decade

POWER

DISSIPATION

4.37𝑚W NA

INPUT REFERRED

NOISE

8.31 (𝑛𝑉√𝐻𝑧

⁄ ) ----

Figure 31 Noise Simulations folded cascade OTA

CONCLUSION

In this report we have studied various architectures of OTA and filter synthesis

methods. A passive 3rd order Butterworth low pass filter based on typical specs for

MHz band i.e. 250MHz is taken from literature and its active synthesis using various

methods is studied. Biquad based synthesis is taken up for the implementation of the

filter. The 3rd order Butterworth LPF is designed using a 2nd order biquad and a first

order integrator. The biquad using Op-Amp RC integrator and Gm-C integrators are

also studied. Simulations for the Op-amp-RC based filter is performed in the NI

Multisim environment which shows the cut-off frequency 424kHz. The filter using

Gm-C biquad is simulated at transistor level in Tanner S-Edit using 250nm CMOS

which achieves a pass band of 85MHz. The Gm-C filter has an attenuation rate of

60dB/decade. The power consumed for the fiilter is 4.37mW at 1.8V dc supply. The

biquad using Op-amp RC integrators, Gm-C integrators are, Passive 3rd order filters

have been compared.

REFERENCES

[1] S. J. Yoo,‘Design of Analog Baseband Circuits for Wireless Communication

Receivers’, Ph.D Thesis, The Ohio State University, 2004.

[2] E. Sanchez- Sinencio and J. Silva-Martinez, "CMOS transconductance amplifiers,

architectures and active filters: tutorial", IEE Proceedings - Circuits, Devices and

Systems, Vol. 147, Issue. 1, pp. 3-12, Feb 2000.

[3] W. Sansen, "Distortion in Elementary Transistor Circuits", IEEE Transactions on

Circuits and Systems II: Analog and Digital Signal Processing, Vol.46, Issue 3, pp.

315-323, Mar 1999.

[4] B. Razavi, Fundamentals of Microelectronics, 2nd Edition, John Wiley, 2008

[5] A. S. Sedra, K.C. Smith, Microlectronics Circuits, Oxford Publications, Ch. 11.

[6] W. K. Chen, Passive, Active, and Digital Filters, CRC Publications, Ch. 16.

[7] B. Razavi, ‘A Circuit for All Seasons: The Biquadratic Filter’, IEEE Solid-State

Circuits Magazine, Spring 2018.

[8] A Panigrahi, "Notes on Design of Gm-C Filters for Channel Selection”. 2019

APPEDNIX

Comparison of OTA and Op-Amp:

Features of OTA- OTAs are simple Voltage input Current output (VCCS) building blocks useful for

tunable or controllable analog operations performed usually in open loop, as their

transconductance can be tunable by varying the Bias current.

OTA are good at driving capacitive loads i.e. modern CMOS circuits.

They can be used in tunable signal processing e.g. tunable filters, Automatic gain

control etc.

They can be used as Voltage controlled Resistors (Tunable resistors) with unity

(negative) feedback around it.

Both Gain and Bandwidth is tunable. Behave like first order systems so stable and

no compensation is necessary unlike Op-amp.

Since they are designed to produce current output, so output impedance is usually

very high.

Since operated in open loop, they are prone to linearity problems.

Features of Op-amp: -

OpAmps are simple Voltage input voltage output (VCVS) building blocks useful

for many analog operations performed usually by adding some components

around it using feedback.

Opamp can drive high capacitive loads and resistive loads.

Since they are designed to produce voltage output, so output impedance is usually

very small.

Opamps offer limited Band width i.e. upto few 10's of MHz and might require

some compensation for stability.

Limited Slew Rate.