High-resolution, fast and radiation-hard silicon tracking station

CBM collaboration meeting March 2005

STS working groupSTS working group

Silicon Tracking Station: Working group

"Real" design

What is the best design?

Version used in present simulations Not really surprising results from simulations including

realsitic detector response

Pixel

Strip

Problems:• MAPS

• Event pile-up• Radiation

tolerance• Hybrids

• Pixel size• Material budget

Problems:• Ghost tracks

To be defined:• Configuration

• But also• Granularity• Material

budget

Challenging tasks of the tracking station (I)

Micro vertex reconstruction (main task of the ITS) Secondary vertex reconstruction better 50m (z-

coordinate) Extremely high track density

GeV1%09.0

GeV3%8.0

μm10

MeV102

0

0

021

pX

x

pX

xx

X

x

pd

x

Both high resolution Both high resolution andand a respectively a respectively low material budget low material budget are needed.are needed.

D0→K

Challenging tasks of the tracking station (II)

Background rejection in low mass dielectron spectroscopy Reconstruction of "incomplete" tracks Needs probably much more redundancy

ee 0 ee

If these are not reconstructed ..

.. those will form a fake open pair

What is the best design?

Version discussed in the TSR Vacuum chamber with small (and hence thin) window Outer part of station 3 by strip technology?

Pixel

Strip

Basic Elements: Inner : 6x2 cm Middle : 6x4 cmOuter : 6X12 cm

Feature Value/Quantity

Angular coverage 50 to 500 mrad

Number of super layers

4

Detector modules per plane

28-60

Detector thickness ≤ 100-150 µm

Sensitive detector area

20x20 cm2 to 50x50 cm2

Operational temperature

≤40°C

Strip pitch 25 µm

Strip configuration

Valeri's talk

What is the best design?

Option proposed by Valeri

Pixel

Strip(x,u and y,v)

Strip (r,)

Could be likeLHCb-VELO

Possible configuration (B-TeV inspired)

Outer section of plane 3 outside the vacuum!

Highest granularity not needed there

Allows using thin vacuum window

Detectors can be moved in two halfs.

Remove sensors from beam area during focusing

Only two different module geometries

Optional for MAPS or Hybrids

Generic designs for simulation

Hybrid-like Material budget Resolution

MAPS-like Radiation hardness Read-out speed

MAPS material budget a first assessment by Michael Deveaux

Stacking of sensors due to inactive read-out area

Design VELO (LHCb) inspired

0.29 %

What is the best design?

Possible direction for future What is the maximum material budget acceptable? Third technology needs additional manpower!

MAPS

Strip

Hybrids

Should deliver unambiguous seeds

High resolution tracking With large coverage

Ultimate vertex resolution

Assessment for GIGATRACKER

NA48: CERN-SPSC-2004-029 (K+→) Concept (only small area needs to be covered)

High rate: 40 MHz / cm2 100 ps time resolution Fluence 4.5 1014 cm2 (12 Mrad) 0.13 m envisaged

http://na48.web.cern.ch/NA48/NA48-3/groups/gigatracker/

x/X0 < 0.6%

MAPS R&D

Dense program of chip submission in 2005 MIMOSA 9 → factor 2 lower signal than expected MIMOSA 10 → MIMOSTAR1 first prototype for STAR IT MIMOSA 11 → Various sensor geometries for studying

aspects of radiation tolerance MIMOSA 12 → Multiple charge storage on-pixel,

aspects of capacitor performance MIMOSA 13 → Current readout

faster, better noise immunity

Transfer of one test station to Frankfurt Support R&D efforts starting with MIMOSA11 Aspects of cryogenic operation

R&D: MIMOSA 13 Topology

- Technology : AMS 035.- (4 metal layer).- Substrate : low doped Hi resistivity

substrate (8-10 Ω.cm).- Chip Area : 5,1mm²- Nb of pads : 44- Pads spacing : 50µm

- Current mode maybe adapted to the high speed and high granularity requirements.

- Sensor matrix- Matrix control logic- Preamplifier, multiplexer

VDDA B2

B ias idc

sel am p

sel d ir

sel m ux

BIAS B2

out9

out10

G ND

VDDA fast

out8

ou

t3

ou

t2

ou

t4

VD

DA

ou

t1

VD

DA

pixb

BIA

S B

2

BIA

S B

1

BIA

S A

1

VD

DA

pixa

sf

VD

DA

pixa

GN

D

D IG signalCLK 100

DIG signal

D IG signal

D IG signalB2

VDD

DIG signal

D IG signal

D IG signal

D IG signal

G ND

VDD

DIG signalB0

DIG signalB1

DIG signal

M ATRICE20 x 64

1850µm

27

50

µm

20 Am plificateurs

M ultip lexeur2 vers 1

B locNum erique

decom m ande

de lam atrice

ou

t7

ou

t5

ou

t6B

IAS

CA

SC

B IAS AM P1

BIAS AM P2

BIAS A1

Talk by Sébastien HEINI (IReS)

Strip R&D

Sensor (M. Merkin's talk) First steps towards a thin double-sided sensor Oxygenation seems unavoidable to reach radiation

tolerance needed Wafers are being ordered

FEE (S. Voronin's talk) Started investigation of technologies for micro

interconnection (i.e. 25 m pitch) Provide VA readout for prototype sensors

Design optimization

Design Optimization

Mainframe

Algorithms Digitizers

Final configuration

Tracking groups

STS group

MAPSHitProducer

(Michael)

Strip HitProducer

(Valeri)

Physics benchmarks:

Open charm

• i.e. 10.000 D0/run

Low-mass dielectrons

• S/B < 1/5

• ?

STS working packages

STS

ITS SIT

MAPS Hybrid

Overall configuration

R&D

Module design

R&D

Module design

Sensor design

FEE R&D

Module design

Readout interface

Integration & Infrastructure

Towards a Design Proposal

Vertex tracker (ITS) Main tracker (SIT)

MAPS fall back Strip

Design optimization Granularity Resolution Configuration

GSI, IReS GSI, IKF Obninsk

Choice of technology Sensor Readout Module/plane design

IReS MSU/MEPHI

R&D IReS, IKF MSU/MEPHI

Infrastructure/Environment

Management