High-End Performance Packaging: 3D/2.5D Integration 2020
46
From Technologies to Markets © 2020 High-End Performance Packaging: 3D/2.5D Integration 2020 Market and Technology Report Sample
Transcript of High-End Performance Packaging: 3D/2.5D Integration 2020
From Technologies to Markets
© 2020
High-End Performance
Packaging: 3D/2.5D
Integration 2020Market and Technology
Report
Sample
2
Table of contents 2
Scope of report 4
Report methodologies & definitions 6
Key features of this report 5
About the author 7
Yole Group of companies related reports 9
Glossaries 11
Companies cited in this report 12
3-Page summary 13
Executive summary 17
Context 66
o Semiconductor industry – players pursuing Moore’s law 67
o High-end performance packaging definition 71
o Scope of report 72
o High-end performance packaging market segment 73
o High-end performance packaging introduction 74
Market forecasts 75
o Market Revenue 76
o Total market revenue
o Split by end-market
o Split by technology
o Market Units 80
o Total market units
o Split by end-market
o Split by technology
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TABLE OF CONTENTS
Part 1/2
o Package ASP split by technology 85
o Market value split by technology 88
o 3D SoC
o 3D stacked memory
o 2.5D interposers
o UHD FO
o Embedded Si bridge
o Chapter conclusion 94
Market trends 96
o Cloud & edge computing 97
o Cloud computing and networking 103
o High-Performance Computing (HPC) 111
o Artificial intelligence for autonomous vehicles 119
o Chapter conclusion 125
Commercialized products and its supply chain 127
o Product launches 130
o 3D stacked memories
o (x)PU
o GPU for HPC
o Supply chain for high-end performance packaging 156
o Global mapping of high-end packaging
o Global mapping based on technology
o Supply chain for high-end packaging products
o Latest progress of key players 175
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o Supply chain analysis in high-end performance packaging 188
o Packaging supply chain analysis
o Analyst’s point of view on supply chain 192
o It is a new battlefield for technology supremacy
o Impact within big players
o Impact on OSATs & substrate suppliers
o What is TSMC strategy exactly?
o Who are the winners/losers?
o Chapter Conclusion 201
IP Analysis: 3D SoC – hybrid bonding 203
o Patent overview 204
o Supply chain IP position (examples) 208
o Chapter conclusion 212
Technology trends 214
o Technology roadmap 215
o Semiconductor packaging roadmap
o Advanced packaging roadmap
o High-end packaging roadmap: iO pitch vs IO density
o High-end packaging roadmap: application-technology
o Key player’s technology roadmap 221
o Short description of chiplet 227
o 3D SoC 230
o Hybrid bonding 234
o Key players’ technologies: hybrid bonding for 3D SoC
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TABLE OF CONTENTS
Part 2/2
o TSV process 254
o 3D stacked memory 260
o HBM
o 3D Stacking (3DS) DRAM
o 3D SRAM
o 3D NAND
o Others: HMC, DRAM stacked memory
o 2.5D interposer 284
o Ultra-high-density Fan-Out (UHD FO) 295
o Embedded Si bridge 301
o Other high-end packaging technologies 310
o Chapter conclusion 315
Report conclusion 318
Appendix 320
o OSATs high-end packaging technologies 321
Yole corporate presentation 330
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The main objectives of this report are:
• To identify and describe which technologies can be classified as ‘high-end performance packaging’
• To define high-end performance packaging
• To analyze key market drivers, benefits and challenges of high-end performance packaging by application
• To describe the different existing technologies, their trends and roadmaps
• To analyze the supply chain and high-end performance packaging landscape
• To update the business status of high-end performance packaging technology markets
• To provide a market forecast for the coming years, and estimate future trends
Fan-out packaging markets are studied from the following angles:
• Top-down based on end-systems demand
• Market valuations based on top-down and bottom-up models
• Market shares based on production projections
• Supply value chain analysis
• State-of-the-art technologies and trends
• End-user application adoptions
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SCOPE OF THE REPORT
Are your needs
beyond this
report’s scope?
Contact us for a custom:
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• Yole Développement’s definition of high-end performance packaging
• High-end performance packaging market segmentation
• Market valuation in terms of package units, revenue and wafer production volumes
• Market valuation of key high-end packaging technologies
• Includes COVID-19 impact in all forecasts
• High-end performance packaging market trends: end-system drivers
• Commercialization of high-end performance packaging products
• Global mapping of high-end performance packaging supply chain
• Supply value chain analysis in high-end performance packaging
• Application-technology roadmap of high-end performance packaging
• Key Player’s technology roadmap of high-end performance packaging : Intel,TSMC and Samsung
• IP Analysis: 3D SoC – hybrid bonding
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KEY FEATURES OF REPORT
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REPORT METHODOLOGIES & DEFINITIONS
Market
Volume (in Munits)
ASP (in $)
Revenue (in $M)
Yole Développement’s market forecast model is based on the matching of several sources:
Information
aggregation
Preexisting
information
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ABOUT THE AUTHOR
Biographie & contact
Favier SHOO
Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole
Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the
production of custom consulting reports.
During 7 years at Applied Materials as a Customer Application Technologist in the advanced packaging marketspace, Favier
developed an in-depth understanding of the supply chain and core business values. As an acknowledged expert in this field,
Favier has provided training and held numerous technical review sessions with industry players. In addition, he has obtained 2
patents.
Prior to that, Favier worked at REC Solar as a Manufacturing Engineer to maximize production capacity. Favier was also the
co-founder of a startup company where he formulated business goals, revenue models and marketing plans.
Favier holds a Bachelor’s in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological
University (NTU) (Singapore).
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ABOUT THE TEAM
Packaging, assembly and substrate
Favier ShooTechnology & Market Analyst
Vaibhav TrivediSr. Technology & Market Analyst
Santosh Kumar Principal Analyst
Emilie JolivetDivision Director
Semiconductor & Software
Experience:
8 years in Technology, Packaging and
Manufacturing
Experience:
17 years in Emerging Semiconductors and
Devices
Experience
15 years in semiconductor industry
Experience:
12 years in semiconductor industry
At Yole:
Packaging, Materials & Manufacturing
At Yole:
Packaging, Assembly and Substrates
At Yole:
Is Principal analyst for the division and
analyst in packaging, assembly and substrates
At Yole:
Manages Semiconductor and Software team
Previous companies:
Applied Materials, REC
Previous companies:
Amkor, Intel
Previous companies
MK Electron, CCI Inc
Previous companies:
EV Group, Solarforce, Freescale
Education:
Bachelor in Materials Engineering (Hons)
Minor in Entrepreneurship
Education:
MBA
M.Sc in Materials Science and Engineering
Education:
M.Sc in Materials Science and Engineering,
Electronics Packaging
Education:
MBA
M.Sc in Electronic Materials
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ADI, AMD , Amkor, Annapurna/Amazon, ARM, ASE, Atmel, Broadcom/Avago, Broadpak, CEA-Leti, Cerebras, Cisco, Cray , Cypress, eSilicon, Facebook, Fraunhofer IZM, Freescale, Fujitsu, GlobalFoundries,
Gloway, Google, Hitachi, HLMC, Huawei, Ibiden, IBM, IME, IMEC, Infineon, Intel, JCET, Juniper Networks, Kyocera, Micron, Mitsubishi, Nhanced,
Nvidia, ON Semiconductor, Oracle, Panasonic, PTI, Qualcomm, Rambus, Renesas, Rohm, Samsung, Sanyo, SEMCO, Sharp, Shinko, SK hynix,
Skywater, SMIC, Sony, SPIL, STMicroelectronics, Tesla, Tezzaron, TI, Toshiba, TSMC, UMC, Xilinx, Xperi, YMTC
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COMPANIES CITED IN THIS REPORT
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SEMICONDUCTOR INDUSTRY
Chronological order of players pursuing Moore’s Law
Moore’s law has guided the global semiconductor industry for past decades (since 1965), improving both performance and cost through node scaling.
After 2002 (130nm), the industry has been consolidating extensively. Limitations in scaling has disrupted companies competing in this business.
Presently, it is an oligopoly market, with a handful of key players remaining.
High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020
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18
14 14
10
76
3 32
0
5
10
15
20
25
130nm 90nm 65nm 45nm/40nm 32nm/28nm 22nm/20nm 16nm/14nm 10nm 7nm 5nm/3nm
2002-2003 2004-2006 2006-2008 2008-2012 2010-2012 2012-2014 2014-2016 2017-2019 2020-2022 2023-2025
Nu
mb
er
of
Pla
yers
Technology Node [Moore’s Law*]
Year
ADI
AMD
Atmel
Cypress
Freescale
Fujitsu
Hitachi
HLMC
IBM
Infineon
Intel
Mitsubishi
ON
Panasonic
Renesas
Rohm
Samsung
Sanyo
Sharp
SMIC
Sony
STM
TI
Toshiba
TSMC
UMC
AMD
Cypress
Freescale
Fujitsu
IBM
Infineon
Intel
Panasonic
Renesas
Samsung
Sharp
SMIC
Sony
STM
TI
Toshiba
TSMC
UMC
Fujitsu
GF
HLMC
IBM
Intel
Panasonic
Renesas
Samsung
SMIC
STM
TI
Toshiba
TSMC
UMC
Fujitsu
GF
HLMC
IBM
Intel
Panasonic
Renesas
Samsung
SMIC
STM
TI
Toshiba
TSMC
UMC
GF
HLMC
IBM
Intel
Panasonic
Samsung
SMIC
STM
TSMC
UMC
Intel
Samsung
TSMC
GF
Intel
Samsung
SMIC
TSMC
UMC
Intel
Samsung
TSMC
?
?
GF
HLMC
IBM
Intel
Samsung
SMIC
TSMC
* Moore’s law states that the number of transistors in an integrated circuit chips doubles every 2 years
Data referenced from Intel and WikiChip
Number of Players with leading-edge manufacturing capabilities
Only 3 players left
[2020]
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IC Substrate: BGA Balls
IC Substrate: BGA Balls
Fan-Out (Core)
Flip Chip: QFN
Fan-In
Flip Chip: Bump
Fan-Out (HD FO)
Fan-Out (UHD FO)
2.5D Si Interposer
Flip-Chip: µbumps/Cu Pillars
Embedded Si bridge: µbumps
Flip-Chip: µbumps/Cu Pillars
Flip-Chip: µbumps/Cu Pillars
Hybrid Bonding: Bumpless
Hybrid Bonding: Next-Gen
1/mm2
2/mm2
4/mm2
8/mm2
16/mm2
32/mm2
64/mm2
128/mm2
256/mm2
512/mm2
1024/mm2
2048/mm2
4096/mm2
8192/mm2
16384/mm2
32768/mm2
65536/mm2
131072/mm2
0,5µm1,0µm2,0µm4,0µm8,0µm16,0µm32,0µm64,0µm128,0µm256,0µm512,0µm1024,0µm
I/O
Den
sity
* (
I/O
per
mm
2)
Lo
g S
cale
IO Pitch (µm)
Log Scale
IO Density vs IO Pitch (Log Scale)
High-End performance Packaging
Presently, there is no acknowledged mainstream definition for high–end performance packaging within semiconductor industry.
If distinct advanced packaging technologies, including flip-chip, embedded die, 2.5D Si interposers, 3D-IC, fan-in, fan-out and hybrid bonding, are considered as high-end performance packaging, then this will be over generalizing high–end performance packaging.
This is because not all advanced packaging technology is high performing. For example, flip-chip and fan-out packaging can exist both in high-end and low-end applications.
In order to prevent such confusion, YoleDéveloppement clearly focuses and defines high-end performance packaging based on IO density and IO pitch.
--- DEFINITION ---
High-end performance packaging is defined as a
forefront packaging technology, which value-
adds device performance with high IO Density
(≥16/mm2) and fine IO Pitch (≤130µm)
--- TERMINOLOGY ---
In this report, “High-end Performance
Packaging” will be used interchangeable with
“High-end Packaging” and “HEP” abbreviation
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HIGH-END PERFORMANCE PACKAGING DEFINITION
Yole Développement’s definition of high-end performance packaging
*I/O Density refers to total number of IOs per package platform area
Plot is generated based Yole Développement’s and System Plus Consulting’s database, with reference to industry average value and assumptions.
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Clearly, transistor counts still follow the guidance of Moore’s Law. With the upcoming introduction of 7nm process nodes it is reasonable toassume that manufacturers will stay on the course for transistor counts growth for the next few years. In parallel, Manufacturing cost is stillbenefitting from Moore’s Law. However, the design cost has risen many times (e.g. 3nm design cost ~35-40X compared to 90nm) and monolithicSoC manufacturing has become extremely complex, leading to an increase in time-to-market.
Moore’s Law is still alive but reaching technical limitations and losing its cost reduction appeal with increasingly heavy design cost. There are stilldemands to innovate for better performance which can justify the investment for the top manufacturers. However, it has become more challengingfor these leading-edge manufacturers to generate revenues out of advanced nodes.
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THE END OF MOORE'S LAW ?
The pace has slowed down, if not the end
2002 2006 2010 2014 2018 2022
102
103
104
105
106
107
180nm 90nm 45nm 28nm 14nm 7nm
Microprocessor performance (FLOPS)
35Å
101
Transistor (k)
Single thread
performance
Frequency (MHz)
Typical power (W)
Number of cores
2002 2006 2010 2014 2018 2022
30
62
125
250
500
1,000
180nm 90nm 45nm 28nm 14nm 7nm
Design Cost ($M)
35Å
15
40nm $38M
28nm $51M
22nm $70M
16nm $106M
10nm $174M
7nm $300M
3nm $550M (?)
2002 2006 2010 2014 2018 2022
1
2
4
8
16
Mfg Cost (¢ per Million Transistors )
0.5
180nm 90nm 45nm 28nm 14nm 7nm 35Å
Moore’s Law
0.25
28nm 2.5¢/MTx
90nm 10¢/MTx
7nm 0.5¢/MTx (?)
90nm $15M
In this report, we will be using the term “slow down” when describing the status of Moore’s law
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HIGH-END PERFORMANCE PACKAGING MARKET SEGMENTATION
The market is divided into high-end & mid/low-end Segments
2.5D & 3D integration
High-end segment
HPC
Artificial Intelligence
Data mining (crypto &
other data)
Super computers
Data centers, hyper scale
Networking
Switch / Router
Gaming
Mid/Low-end segment
Sensing
MEMS & sensors
CIS
Lighting
LED
High-end segment is defined as the market where an application is less sensitive to
the cost, but requires reduced footprint in addition to high performance & reliability
Mid/Low-end segment is defined by a good
balance between cost sensitivity & performance
14
0.8%
Automotive
& Mobility
0.1%
Defense &
Aerospace
40.8%
Mobile &
Consumer
58.4%
Telecom &
Infrastructure
0.1%
Defense &
Aerospace11.6%
Mobile &
Consumer
88.2%
Telecom &
Infrastructure
2019-2025 HIGH-END PERFORMANCE PACKAGING MARKET FORECAST
2019 2025
$0.8 B $4.7 B
CAGR2019-2025 =32%
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MARKET REVENUE
Total High-End Performance Packaging Revenue
The high-end performance packaging market is expected to reach $4.7B by 2025 from $884M in 2019, with a CAGR of 32%.
High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020
2019 2020 2021 2022 2023 2024 2025 CAGR
Total 884,8 1179,3 2182,1 2800,6 3284,2 3886,6 4781,9 32%
0,0
1000,0
2000,0
3000,0
4000,0
5000,0
6000,0
Reve
nue ($M
)
High-End Packaging Revenue ($M): End-Market
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MARKET UNITS
Total high-end performance packages
The production units of high-end packaging will rise at a CAGR of 38% from 204.5M Units in 2019 to 1409.2M Units by 2025.
High-end performance Packaging: 3D/2.5D Integration 2020 | Sample | www.yole.fr | ©2020
2019 2020 2021 2022 2023 2024 2025 CAGR
Total 204,5 289,7 581,1 806,8 968,5 1156,0 1409,2 38,0%
0,0
200,0
400,0
600,0
800,0
1000,0
1200,0
1400,0
1600,0
No. of Pac
kag
es
(M U
nits)
High-End Packages (M Units): End-Market
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HIGH-END PERFORMANCE MARKET VALUATION FORECASTS
Market forecast split by end-markets and technology
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HIGH-END PERFORMANCE MARKET VALUATION FORECASTS
Market forecast for each high-end packaging technologies
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SUPPLY CHAIN OF HIGH-END PACKAGING
Example based on a 3D/2.5D package for high-end performing applications
xPU
2.5D INTERPOSER
IC Substrate
PCB Board
HBM
Final assembly: OSAT | Foundry | IDMThe final assembly (HBM, GPU, interposer, interposer on PCB, passives assembly and BGA balls) is performed by OSAT and Foundry (possibly IDM).
HBM packaging: IDM | Memory supplierThe HBM stack (memory dies, logic die) is made by a
Memory manufacturer.
xPU supplier: Foundry | IDMThe CPU or GPU die is manufactured by wafer
foundry.
2.5D interposer:
Foundry | IDMThe GPU die is manufactured by wafer
foundry.
IC substrate:
Substrate supplierThe PCB package substrate is
made by a substrate maker.
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HIGH-END COMMERCIAL PRODUCTS LAUNCH: STACKING TECHNOLOGY
3D/2.5D TSV
FPGA
DDR4 3D 64GB
GPU Fiji
DDR4 3D 128GB
DDR4 3D 128GB
Yole Développement, 2020
EMIB
Co-EMIB
* Expected product launch in near-term
GPU Pascal 100
Xeon Phi processor
based on Knight
Landing processor
FPGA Virtex
Ultrascale + 16nm
POST
FX10
NPU on
interposer
Hybrid bonding
NEW Newly Added in 2020’s Report
Technology
2011 2014 2015 2016 2017 2018 2019 2020 ≥2021*
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GLOBAL MAPPING OF HIGH-END PACKAGING SUPPLY CHAIN (HQ)
Package design
xPU supplier
Memory
supplier
Interposer
Substrate
Packaging
Chips supplier
Systems
End-customers
Non-exhaustive List of Players
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HIGH-END PACKAGING – FULL SUPPLY CHAIN
xPU Memory Interposer Substrate PackagingPackage
designChips Systems
End-
customers
Non-exhaustive List of Players
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GPU FOR HPC
Supply chain for AMD GPU Radeon™ Vega Frontier
• AMD is willing to switch to 7nm node
GPU’s. They announced the first 7nm GPU
in October 2018.
• AMD will switch from Global foundries to
TSMC to manufacture their 7nm GPUs as
Global foundries halted the development of
this advanced node.
SPIL Taiwan CoW chip last process
UMC
Taiwan
Ibiden
Japan
Samsung
Korea
Global
foundries
14nm node
GPU HBM2 Interposer Substrate
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PACKAGING SUPPLY CHAIN ANALYSIS
Go “head-to-head” or “along” with the Big Guys before the ship sails?
IDM/Foundry
OSAT/Substrate
Non-exhaustive List of Players
High-End
Packaging
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MAPPING OF HIGH-END PACKAGING PLAYERS BASED ON TECHNOLOGYI/O
Densi
ty*
( I/O
per
mm
2)
300 200 100 50 <5
15
20
100
300
>>10,000
UHD FO
2.5D interposers
Embedded Si bridge
Hybrid Bonding: bump-less
3D stacked memories:
TSV, micro-bumps
IO Pitch (µm)
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TIME EVOLUTION OF PATENT PUBLICATIONS
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Nu
mb
ero
f p
aten
t fa
mili
es*
(i
nve
nti
on
s)
1st publication year
More than 1,400 patents and patent applications grouped in more than 400 patent families*
related to 3D SoC have been published worldwide
2011, acceleration of the patenting activity
driven by image sensor applications
Since 2014, strong acceleration of TSMC
patenting activity
Note: The data
corresponding to
the year 2020 is
not complete
since patent
search was done
in Sep 2020.
* A patent family is a set of patents filed in multiple countries to protect a single invention by a common inventor(s). A first application is made in one country – the priority country – and is then extended to other countries.
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MAIN IP PLAYERS PER TARGETED APPLICATION
The following table shows the main applications described in players patents. Segmentation does not take the
players’ market position into account in this table.
CISDie-on-IC
(mainly memory-on-IC)
3D memory
(memory-on-memory)
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2.5D INTERPOSER: INTEL
Intel’s Foveros in Samsung Galaxy Book S (1/2)
Intel Core i5-L16G7 3D Package
Full teardown report is done by System Plus Consulting ©2020
Source: System Plus Consulting ©2020
PCB BoardSamsung Galaxy Book S TeardownSamsung Galaxy Book S
Cross Section (Optical View) of Intel Core i5-L16G7 3D package
Active Foveros
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HIGH-END PACKAGING ROADMAP: APPLICATION-TECHNOLOGY
TYPES OF
TECHNOLOGIES
Hybrid Bonding
Embedded Si bridge
TSV, Micro-bumps
2.5D Interposers
UHD FO
Stacked DRAM3DS
AMD GPUVega FrontierXilinx FPGA
Virtex Ultrascale
NVidia GPUPascal 100
Intel FPGA
Stratix 10
Intel HBM+GPU
Kaby Lake-G
Intel FPGA + Chiplets
Agilex
HiSilicon CPU (Storage) Hi1610 (Now known as Kunpeng)
Broadcom (x)PU + HBMJericho2
Google (x)PU
TPU V3
Intel (x)PU Ethernet Switch
Tofino2
Intel CPU + Active InterposerIntel Lakefield Foveros Core i5-L16G7
Samsung HBM2E
Flashbolt
Samsung HBM
Flarebolt
YMTC Periphery + Array
X-Stacking
Intel Exascale GPU - HPCPonte Vecchio: Co-EMIB
HPCs potentially for Tesla and CerebrasTSMC inFO_SoW
HPC (x)PU in ServersTSMC & Intel – 3D SoC
* From 2020 onwards, applications/technologies are presumed based on interviews with industry players and research.
Non-exhaustive list of applications/technologies
NVidia GPU Interposer HBM2EA100
2025≤2019 2020* 2021 2022 2023 2024
I/O
DEN
SIT
Y
TIMELINE
30
TSMC’s SoIC is one of the key technology pillars which provides front-end, 3D inter-chip (3D IC) stacking by re-integrating partitioned dies from a single monolithic System on Chip (SoC). This technology advance towards the field of heterogeneous chiplets integration with reduced size, increased performance. TSMC-SoIC service platform meets the ever-increasing compute, bandwidth and latency requirements in cloud, network and edge applications.
SoIC is applicable for both D2W and W2W schemes. Such dual scheme provides superb design flexibility in mixing andmatching different chip functions, sizes and technology nodes.
This also integrates active and passive chips into a new integrated-SoC system, which is electrically identical to nativeSoC, to achieve better form factor and performance. TSMC expects the resulting integrated chip outperforms theoriginal SoC in system performance.
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TSMC
TSMC-SoIC™
Monolithic SoC die TSMC’s SoICRe-integration of partitioned SoC dies through stacking with core circuits chip
Source: TSMCSource: TSMC
31
Latest technical breakthrough in 2020:
Interposer size has been increased in the past few years to extend thetechnology envelope of CoWoS, from 800mm2 to 1200mm2
In 2020, TSMC and Broadcom have collaborated to enhance Chip-on-Wafer-on-Substrate (CoWoS) platform to support the industry’s first andlargest 2X reticle size interposer. With an area of approximately1,700mm2, this next generation CoWoS interposer technologysignificantly boosts computing power for advanced HPC systems bysupporting more SoCs as well as being ready to support TSMC’s next-generation five-nanometer (N5) process technology.
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2.5D INTERPOSER: TSMC
Chip-on-Wafer-on-Substrate (CoWoS®) latest breakthrough
This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidthmemory (HBM), offering as much as 96GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7x faster than TSMC’spreviously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offeringadditional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield forcomplex ASIC designs in advanced process nodes.
Through the experience of multiple generations of development of the CoWoS platform, TSMC innovated and developed a unique mask-stitchingprocess enabling expansion beyond full reticle size, to bring this enhancement to volume production. In this TSMC and Broadcom CoWoS platformcollaboration, Broadcom defined the complex top-die, interposer and HBM configuration while TSMC developed the robust manufacturing processto maximize yield and performance and meet the unique challenges of the 2X reticle size interposer.
Source: TSMC CoWoS Production At Full Capacity As Demand Skyrockets – Nvidia,
AMD, And More Trying To Get Their Hands-On Interposers. [Online]. Available:
https://wccftech.com/tsmc-cowos-production-at-full-capacity-as-demand-skyrockets-
nvidia-amd-and-more-trying-to-get-their-hands-on-interposers/ [Accessed: 24-Sep-
2020].
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TSMC
TSMC-SoIC™: Holistic 3D system integration
Source: “System on Integrated Chips (SoICTM) for 3D Heterogeneous Integration,” 2019 IEEE 69th
Electronic Components and Technology Conference (ECTC)
Source: “Ultra High Density SoIC with Sub-micron Bond Pitch,” 2020 IEEE 70th Electronic Components and
Technology Conference (ECTC)
TSMC’s SoIC enabling technology combines the Front-End + Back-End holistic
3D heterogeneous integration. Such approach allows advantages to best
optimized system PPAC for More Moore and More-Than-Moore.
Such partition-reintegration is using a chip-to-chip interconnection with both
horizontal line/space and vertical bond pitch equivalent to global layers of Cu
back-end-of-line (BEOL) interconnect.
This is an innovative wafer level Front-End 3DIC chip stacking platform.
An SoIC integrated chip not only looks just SoC but also behaves like an
SoC in every aspect in terms of electrical and mechanical integrity. It can
then be assembled using conventional packages or new advanced
packaging. For 2.5D interposer, for example, TSMC’s CoWoS or Fan-Out
Packaging, for example, TSMC’s InFO.
Front-End 3D SoIC can mix-and-match with Back-End 3D InFO/CoWoS
to gain best performance and cost benefits, like a "3Dx3D" system-level
solution.
Novel Approach: FE + BE Integration into a single SoC-like chip
33
Second-generation EMIB
• High-density interconnect at lower cost compared to Si-interposer
• Flexible chip combination and reuse across different nodes
• Disaggregated transceiver tiles and HBM memory
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EMBEDDED SI BRDIGE: INTEL
EMIB technology in Intel® Agilex™
Enables monolithic fabric across full familyFabric ease of use while delivering multi-die heterogenous compute
Source: Intel
Source: Intel
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HIGH-END PERFORMING TECHNOLOGY: INTEL
Intel's Xe graphics "Ponte Vecchio" architecture: Co-EMIB
Source: Intel
Source: Intel
Source: Intel
This will be Intel’s first ‘exascale class’ graphics solution and is clearly using both chiplet technology(based on 7nm) and Foveros/die stacking packaging methods. Ponte Vecchio will also use Intel’sEmbedded Multi-Die Interconnect Bridge (EMIB) technology, joining chiplets together. Pulling all thechips into a single package is fine, meanwhile GPU-to-GPU communication will occur through aCompute eXpress Link (CXL) interface.
Source: Intel Source: Intel
35
At Intel Architecture Day 2020, one of the highlights is hybrid bonding being investigated for Intel’s future…
“…This new technology enables very aggressive bump pitches of 10 microns and below, delivering much higher interconnect density and bandwidth, along with lower power…”
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HYBRID BONDING: INTEL
Intel begins to focus on hybrid bonding for future
Source: Intel’s Newsroom. [Online]. Available: https://newsroom.intel.com/press-kits/architecture-day-2020/#gs.gcljq6 [Accessed: 23-Sep-2020].
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2.5D INTERPOSER: INTEL
Foveros technology in Lakefield chip
Foveros:• 2.5D Si interposers
• TSV
• Face-to-Face (F2F) bonding
Source: Intel Architecture Day 2020
37
In 2020, Samsung announces the immediate availability of its Silicon-proven 3D IC Technology, eXtended-Cube (X-Cube), for
high-performance applications in mobile, wearable and HPC devices.
The X-Cube is built on 7nm uses TSV technology to stack SRAM on top of a logic die, freeing up space to pack more memory
into a smaller footprint. Enabled by 3D TSV integration, the ultra-thin package design features significantly shorter signal paths
between the dies for maximized data transfer speed and energy efficiency. Desired specifications of memory bandwidth and
density can be scaled vertically.
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SAMSUNG’S X-CUBE
'X-Cube’ is the industry-first 3D SRAM-logic working silicon at 7nm
Source: Samsung
Source: Samsung
X-CubeTypical Package
2D (Side by Side)
3D IC Package
3D (Stacked)
SRAM
Logic
SRAM
Logic
SRAM
Logic
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HBM: MEMORY BANDWIDTH BENEFITS
Speed: memory bandwidth comparison
Samsung’s new HBM2E (commercially known as the Flashbolt)“E” stands for Evolutionary
Advantages of HBM2E over HBM2• 33% better performance over HBM2
• Doubling the density to 16 gigabits per die.
• DRAM transfer speeds per pin can reach 3.2 Gbps
• Single Package capable of 210 GB/s and 16GB of capacity
• Positioned for Al and ML applications
Source: Samsung
39
D2W and D2D hybrid bonding applications are 3D memory stacking and 2.5D/3D high-performance computing
• A single stacking solution for all DRAM products: 3DS, HBM2, HBM3, and beyond
• Enables wide range, coarse interconnect pitch to 1µm pitch for next-generation DRAM and 2.5D/3D logic and memoryintegration
• Allows integration of same or different die sizes
• Interconnect layers add no stand-off height, requires no copper pillars or under-fill
• Since no copper pillars or under-fill between the die in the stack, it enables better thermal performance
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XPERI
Applications of DBI® Ultra: D2W & D2D hybrid bonding
3D Stack Memories (D2D)2.5D Integration (D2W)
Source: Xperi
Source: Xperi
Source: Xperi
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YMTC
YMTC’s Xtacking®: hybrid bonding process flow
The periphery circuits
which handle data I/O as
well as memory cell
operations are processed
on a separate “Periphery
Wafer” using the logic
technology node that
enables the desired I/O
speed and functions.
Flip-Chip could be done
onto 3D NAND array
wafer. Periphery Wafer
CMOS wafer can be flipped
over to align the metal
interconnections with
Array NAND wafer.
The two wafers are
connected electrically
through billions of metal
VIAs (Vertical Interconnect
Accesses) that are formed
simultaneously across the
whole wafer in one process
step
This modular approach also
opens possibilities for
customized NAND flash
solutions by the
incorporation of innovative
functionalities in the
periphery.
Source: YMTC
Independent Wafers processing
Wafer Flipped Over
W2W Hybring Bonding
Xtacking® Technology
41
Hybrid bonding is defined as a permanent bond that combines a dielectric bond with embedded metal to forminterconnections It’s become known industry wide as direct bond interconnect or Direct Bond Interconnect(DBI®) from Xperi.
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HYBRID BONDING INTRODUCTION
Definition and process flow
The term “Hybrid”, in this context, comes from the fact the interface has two types of
co-planar materials, metal pads and dielectric surface.
42
Due to high-end performance application demands, industry players are now pursuing higher level ofinterconnect density. At system-level, three dimensional (3D) packaging has become a crucial platformto achieve this. Cu redistribution lines (RDLs) and Cu via are adopted for interconnects between chips.In addition, solder microbumps and through silicon vias (TSVs) are used as the vertical interconnectsbetween the stacked chips.
For partitioned 3D SoC to be packaged, the dimension of the interconnects is expected to drivetowards 10 μm and beyond. However, there are some manufacturing limitation for solder bumps withthe shrinkage of bump pitch. Bridging with neighbor bumps, and full intermetallic compounds joints areprone to necking or shorting, especially if bump pitch shrinks below 10 μm. In high-performanceapplication, the interconnect IO pitch requirement is now shrinking below what can be achieved withFlip-Chip solder joints.
Among the different packaging technologies being developed for heterogeneous integration of ICs,wafer-to-wafer (W2W) hybrid bonding is attracting interest due to its high integration densitycapability, allowing μm and sub-μm scale of interconnect pitches. It offers a z-axis direction ofintegration, enabling new 3D SoC architectures to benefit from improved interconnect density andreducing overall product x-y footprint.
Therefore, hybrid bonding emerges as the solution for next-generation fine-pitch interconnects.
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HYBRID BONDING
Why use hybrid bonding for 3D SoC integration?
43
Contact our
Sales Team
for more
information
(x)PU: High-End CPU and GPU for Datacenter Applications
2020
Status of the Advanced Packaging Industry 2020
System-in-Package Technology and Market Trends 2020
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YOLE GROUP OF COMPANIES RELATED REPORTS
Yole Développement
44
Contact our
Sales Team
for more
information
YMTC’s 3D-NAND Flash Memory
Intel Foveros 3D Packaging Technology
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YOLE GROUP OF COMPANIES RELATED REPORTS
System Plus Consulting
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