High Efficiency Power Amplifiers for Higgq ypph … … · · 2009-11-17Fundamentals of Microwave...

Short Course onShort Course on Fundamentals of Microwave Power Amplifier Design

High Efficiency Power Amplifiers for High Frequency Applicationg q y pp

Presenter: Franco Giannini, University of Roma Tor VergataPaolo Colantonio, University of Roma Tor Vergata

WORKSHOP AND SHORT COURSES

European Microwave Week, Rome, 28th Sept. – 2cd Oct. 2009

OutlineIntroductionClass of operation and load impedance techniques (LP)Class of operation and load impedance techniques (LP)Simplified design criteria (Cripps, Tuned Load)Power balance and efficiency improvement criteriay pReview of RF traditional classes of operation

Class FClass E

Advanced design criteria for high frequency PAOutput Harmonic TuningInput Harmonic tuningLi it ILinearity Issues

Experimental resultsConclusions



2/50Conclusions

IntroductionThe aim of a PA is to increase the power level of signals to betransmitted, without affecting the information content andincreasing the system efficiencyincreasing the system efficiency.

Mixer

Antenna

Mixer

Antenna

Mixer

Antenna

PA

IF/AGCVCO

PA

IF/AGCVCO

PAPA

IF/AGCIF/AGCIF/AGCVCOVCO

• To design a PA several features have to be considered…

LC Tank

PLL LC Tank

PLL LC TankLC Tank

PLLPLLPLL

To design a PA several features have to be considered…Application (frequency, modulation signal….)Packaging Impact Power lever requiredLinearity Issues Efficiency…



3/50

Amplifier Design

The design of an amplifier implies a suitable synthesis of both input and output active device matching networks, accomplishing design requirements and stability issues.

VGG VDDVGG VDD

50 Ω50 Ω

Output

Network

Input

Network 50 Ω50 Ω

Output

Network

Input

Network

Pin

ZS ZL

Pin

ZS ZL

Linear Approaches Non linear approachesS-parameter analysis Harmonic generationp y

Closed form design relationships (e.g. MAG or MSG)

No harmonic generation

g

Non linear (e.g. HB) analysis tools

No design relationships



4/50No harmonic generation

Linear vs. non linear design approachVGG VDD

ZL(f)ZS(f)Max. Gain Max. Power

id

Gain Stages

[ ]( )devMAG f S=*

*S in⎧Γ = Γ⎪

⎨Γ = Γ⎪⎩ vdsL outΓ = Γ⎪⎩

Power Stagesj0.5

j1

j2-1 dBj0.5

j1

j2j0.5

j1

j2-1 dB-1 dB

*

: maximize( )S in

L outPΓ = Γ

Γ0 0.2 0.5 1 2 5

j0.2 j5

-2 dB

-3 dB

0 0.2 0.5 1 2 5

j0.2 j5

0 0.2 0.5 1 2 5

j0.2 j5

-2 dB

-3 dB

-2 dB

-3 dB

Power Match Condition

-j0.2

-j0.5 -j2

-j5

Pmax

-j0.2

-j0.5 -j2

-j5-j0.2

-j0.5 -j2

-j5

PmaxPmax



5/50

j

-j1

-j2j

-j1

-j2j

-j1

-j2

Device power limiting mechanisms

Technological progress can improve d i h i l t i t

500 Imaxdevice physical constraints

Increase maximum current (Imax) and breakdown voltage (Vbr)300

400iD

(mA)

Decrease knee voltage (Vk)

Increase device thermal disposal (i.e. increase maximum device Pdiss)

100

200 Pdiss

diss)

0 2 4 6 8 10 12 140

vDD (V)Vk

Design strategies become mandatory to attain highest efficiency performances from the available device

S (C )Switched mode operating conditions (Class E)

Harmonic tuning approaches (Class F, HM, etc.)



6/50

PA Design Quantities (1)

Power Gain outPGP

≡ ( ) ( )1diss ds dP v t i t dt

T≡ ⋅ ⋅∫Dissipated power

Drain Efficiencyut

d

PP

η ≡

inP TT ∫

dcP

Power Added Efficiency1 11 1out in outP P PPAE

P P G Gη− ⎛ ⎞ ⎛ ⎞≡ = ⋅ − = ⋅ −⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠dc dcP P G G⎝ ⎠ ⎝ ⎠

Another definition… 20

30

56

70

2outPPAE

P P≡

0

10

28

42

Gain P

ae

Pout P

ae2

2dc inP P+

-10 -5 0 5 10 15 20 25

-10

0

0

14

Pi



7/50Pin

PA Design Quantities (2)

PAE is related to dissipated power by

( ) ( )

( )1

11

1diss out out

PAEPAE

GP P P PAE

PAE−

−⎡ ⎤− −⎢ ⎥

⎣ ⎦= ⋅ ≈ ⋅ −( )diss out outPAE

For a cascade of (matched) power stages:( ) p g

2 2

Pη ηη η= =Pin Pout

Pdc1 Pdc2

1 2

1 22

11 dc

dc

PGP

ηη

++G1 G2

Conversion efficiency is usually dominated by the final stage (Pdc2>>Pdc1), but if its gain is too low, driver efficiency becomes crucial !



8/50

g , y

Class of operation: a confusing topicBy such a generic term, a variety of different subjects are indicated.

d fi d b th l t d i tbiasing class

• class A

depending on the duty cycle of the device drain (collector) current

defined by the selected quiescent bias point

idclass A• class AB• class B• class C

AAB

B C A

vds

ABBC

α = 2⋅ππ < α < 2⋅π

α = π

Class-A

Class-ABClass-B

Id = Imax / 20 < Id < Imax / 2Id =0 , Vgg = Vpo

Class-A

Class-ABClass-Bα π

α < π

Class-B

Class-C Id =0 , Vgg < Vpo Class-C

The duty cycle depends on the quiescent bias point, on the drive level & on the output t i ti t i l t d fi iti



9/50termination: not equivalent definitions

Class of operation: a confusing topic

With the term Class can be also indicated

an operating mode• Class E• Class D

The active device is forced to operate as a switch

• …

h i i t/ t t Th ti d i t t ll d tan harmonic input/outputtuning strategy

• Tuned Load• Class F

The active device acts as a controlled current source (as an amplifier) and is loaded by suitable terminations at harmonic frequencies.

• Class F• …

A given device may be biased in a given biasing class and may adopt anharmonic tuning strategy : for instance, a Class AB - Class F amplifier stage



10/50

Power Amplifier Design Techniques

The microwave PA design techniques can be represented in two classes

I_METERID=AMP1

LTUNER2

Zo=Ang=Mag=

ID=

50 Ohm0 Deg0.95 LoadTuner1

PPH25NCF

NWu=

ID=

450 umT1

Experimental approaches (Load/Source Pull)

Circuit simulation

3:Bias

1 2

3:Bias

12

LTUNER2

Zo=Ang=Mag=

ID=

50 Ohm156 Deg0.86 SourceTuner1

DCVSID=VDD1

V_METERID=VM1

1

2

3

Via=N=

1 4

PORT1

Pwr=Z=P=

5 dBm50 Ohm1

PORT

Z=P=

50 Ohm2

V=5 VDCVS

V=ID=

-0.3 VVGate1

V_METERID=VM2

1.

0

6

0.

8

Load Pull Data Contour GraphSwp Max

110

0 1.

0

10

.0

10.0

5.

0

5.0

2.

0

2.0

3.

0

3.0

4.

0

4.0

0.

2

0.2

0.

4

0.4

0.

6

0.6

0.

8

1.

0

-10.0

-5.0

-2.0

-3.0

-4.0

-0.2

-0.4

-0.6

-0

.8 Swp Min

1

LPCS[16,14,0.5]Pout

LPCS[29,19,2]Pae



11/50

-1- 1

Load/Source Pull Measurements (1)

PowerMeter

PowerSensor

Power

j0.5

j1

j2

Power Levels in dBm

PowerSensor

j0.223

2221

Power Levels in dBm

Full characterisation of active devices

Optimum network terminations-j0.2

0

Power and efficiency contour plots

j0.2

-j0.5 -j2



12/50-j1

Load/Source Pull Measurements (2)

Devices must be available in the appropriate forms

Dedicated measurement system

Lengthy procedure (repeated for each frequency and biasing point)Lengthy procedure (repeated for each frequency and biasing point)

Harmonic load/source pull ?

D t ti t ?WORKSHOP AND SHORT COURSES


13/50Destructive measurements ?

Simplified Approaches

Need fewer information on the device (often already available)

Are extremely fast and absolutely cheapAre extremely fast and absolutely cheap

Supply information on the optimum bias and drive level, drasticallydecreasing the design effort (whatever is the preferred design strategy)decreasing the design effort (whatever is the preferred design strategy)

Supply a good starting point for targeted optimisations

Give a good physical insight into the power generation/saturationGive a good physical insight into the power generation/saturationphenomena

HARMONIC TERMINATIONS ?HARMONIC TERMINATIONS ?

NEGLECTED ACCOUNTED FOR- Cripps methodology- “Tuned Output” analysis

- Class E (Sokal theory) - Class F (Snider theory)



14/50- Harmonic Design

Tuned Load (1/3)The active device acts as a current source

g V

Rds

gmVi

CdsVi

+

The device output is short-circuited at all harmonic frequencies, therefore obtaining apurely sinusoidal drain (output) voltage.

IMaximum output power can be obtainedsimultaneously maximising voltage andcurrent swings

ID

At fundamental frequency, current andvoltage components must be in-phase toobtain the maximum active power: the

0 VDS

obtain the maximum active power: theload at the intrinsic terminals of the devicemust be purely resistive.



15/50

Tuned Load (2/3)For a Class A amplifier

max

2MII = 12 dd kV VR −2

kddM VVV −= max

2 dd kopt

opt

RI G

= =

2 2max1 1 1( ) ( )IP V V I R V V G2 2maxmax( ) ( )

2 2 8 8opt dd k opt dd k optP V V I R V V G= − = = −

Id

Imaxslope = 1/Rs

l /

Id

Imaxslope = 1/Rs

slope = 1/Rslope = 1/Roptslope = 1/Ropt

VdsVk Vdd VdsVk Vdd

Purely resistive load

Complex load



16/50

Tuned Load (3/3)

0.8Efficiency

0.3Output power and gain

P

0.65

ηd

0.25 1

Pout

B0.5 0.2 0.25

Gain

Bias ABBias AB

0.2

Pd

0.6dc power supplied

Normalised to

VDD·Imax

Pdc

0.4

AB0.2



17/50Bias AB

PA design trade-off

70

80Idc = 0.5 Imax

Idc = 0 25 Imax

Efficiency vs. Back-off

v]

Idc = 0.5 Imax

Idc = 0 25 Imax

Linearity vs. Back-off

40

50

60

η

Idc = 0.125 Imax

Idc = 0.25 Imax

Idc = 0.05 Imax

Idc = 0

scal

e:2d

B/d

iv

Idc = 0.125 Imax

Idc 0.25 Imax

Idc = 0.05 Imax

Idc = 0

10

20

30

Pou

t [s

0Pin [scale:2dB/div] Pin [scale:2dB/div]

Decreasing quiescent bias point

Highest back-off becomes mandatory to resurrect linear deviceidid

Highest back off becomes mandatory to resurrect linear device behaviour (except for ideal Class B bias condition)

Back-off operating condition rapidly decrease the efficiencyvdsvds



18/50

Power Balance in PA

VDD 0dc DDP V I= ⋅DC power

LRFC

i (t)

iout(t)IO

( ) ( )0

1 T

diss DS DP v t i t dtT

= ⋅∫Dissipated poweriD(t)

vDS(t)

0

( ),1 cos2out nf n n nP V I ψ= − ⋅ ⋅ ⋅Output Powers2

Vn

Ψn, ,dc diss out f out nfP P P P∞

= + + ∑

PP

In

n2n=

∑

∑∞

=

++==

2,,

,,

nnfoutfoutdiss

fout

dc

fout

PPP

PP

Pη



19/50=2n

High Efficiency Approaches

In order to achieve the maximum value1 t diti h t b== ,, foutfout PP

η η=1, two conditions have to besimultaneously fulfilled∑

∞

=

++2

,,n

nfoutfoutdissdc PPPP

η

No overlap between v (t) and i (t)( ) ( )1 0T

P v t i t dt= ⋅ =∫

&

No overlap between vDS(t) and iD(t)( ) ( )0

0diss DS DP v t i t dtT

= ⋅ =∫

&

1∞ ∞

( ),2 2

1 cos 02out nf n n n

n n

P V I ψ= =

= ⋅ =∑ ∑ Vn·In=0 ( Class F or Inverse Class F )

ψn=π/2 ( Class E )



20/50

ExampleAssuming squared drain current and voltage waveforms (purely resistive load at all harmonic frequencies)

P

iD(t)

vDS(t)0.4

Pout,nf

D( )

time

No overlap but …0.2

time

TT/2

0P f 3f 5f 7f 9f0

8 81 1%η = ≈max2 2

,

04 odd

diss

DD

out nf

PI V n

P nπ

=

⋅ ⋅⎧⎪= ⋅⎨⎪ 2 81.1%η

π= ≈,

max

0 even

2

out nf

dc DD

nIP V

⎨⎪⎩

= ⋅



21/502dc DD

Switching Mode: Class E

LC

+VDD

LRFC LTh ti d i i f d t

Sokal, 1975iSW

Active device

CR

LSCS LThe active device is forced tooperate as a switch.

vds itot

iC

SW

CoutSOutput load designed to properlyshape id(t) and vds(t) waveforms

itot(θ)iSW(θ)

i (θ)

OFF

Waveforms properties

Zero Voltage Switching (ZVS): Voltage has to be zero during conduction

θ

iC(θ)

ON

Voltage has to be zero during conduction phase (0-α)

Zero Voltage Derivative Switching (ZVDS):

θ

vC(θ)

α γ β

Voltage has to have null derivate (β)

Transitions ON-OFF e OFF-ON have to be instantaneous



22/50

θα γ β instantaneous

Class E Design Equations

+VCC+VCC

Bias ConditionsSchematic

C2LRFC L2 LSC2C2LRFCLRFC L2 LSL2 LS

max0.3494DCI I= ⋅

0 01771 I⎡ ⎤RL

S

C1

RLRL

S

C1C1

max0.01771min ,3.562DD BR

ds

IV V

f C⎡ ⎤⋅

= ⋅⎢ ⎥⋅⎣ ⎦490.28 jeZ

°

=

Network Design Equations

1 I

,11

EZCω

=

Class E limitations

0 577 DDVR ≈ ⋅

0.665 DDVL ≈ ⋅

1

S SL Cω =

⋅ 1DC

DD

IC

Vπ ω=

⋅ ⋅

1I

max 3.562 DD DSV V BV≈ ⋅ <Breakdown

Maximum0.577LDC

RI

≈ ⋅ SDC

LIω

≈ ⋅ maxmax

1

10.063BR

If

V C= ⋅ ⋅

Maximum Frequency

The high frequency behaviour is mainly driven by device parasitic elements



23/50Only few harmonics can be controlled

Class F – Ideal (1)The active device acts as a current source, controlled by the inputdriving signal.

Th d i f i ( ) i fi d hil h l dThe output drain current waveform id(t) is fixed, while the output loadnetwork is designed to shape the drain voltage vds(t) waveforms tominimise power dissipation Class B bias condition

IN Zmatch

@fo

VDD

@nf @nf+

iD(t)

Zmatch

@nfon≥2

@nfon odd@fo

@nfon

even

OUT

Z Z 0

+vDS(t)

vDS(t)n≥2

-VGG

Z1 Zodd=∞ Zeven=0iD(t)

ON OFFT/2T/2

η = 100%0=dissPNo overlapping

Vn·In=0, 0out nfP

∞

=∑

ON state

OFF stateT/2T/2



24/502

fn=∑

Class F – Ideal (2)From a Fourier analysis, that can be repeated for Class A bias conditionalso, and compared to classical Tuned Load results, the followingexpressions can be derivedexpressions can be derived

4V I4V I

Class A Class B

( )

( )4 1

0

TLR n

Z fα π

απ =

⎧⋅ =⎪

⎪⎪⎨

DDV I⋅ DDV I⋅

max, ,

4DDrf F rf TL

V IP Pπ π⋅

= = ⋅max, ,

4DDrf F rf TL

V IP Pπ π⋅

= = ⋅( ), , 0

DS F idealZ nf n even

n odd

⎪= ⎨⎪∞⎪⎪⎩

4η η= ⋅

1

η

max, ,2

DDdc F dc TL

V IP P= = max, ,

DDdc F dc TL

V IP Pπ

= =

2 63 7 %rfPη = = ≈

4 100%rfPη η= = =

0.637

F TLη ηπ

= ⋅η63.7 %dcP

ηπ

= = ≈ 100%TLdcP

η ηπ

= = =

Class B Class A

0.5



25/50Bias Class

Remarks on Class FA 100% drain efficiency depends on the particular terminations: perfectshort circuit at even and perfect open circuit at odd harmonics (i.e.PHM=0)PHM 0)

In actual cases, it is possible to control only the lower order harmonics( ll t th thi d ) All th i i ti ll h t d(usually up to the third one). All the remaining ones are practically shorted

Nothing is said about the voltage harmonic generation mechanism (in theclass B odd harmonics are not generated at all !)

The “phase” of the harmonics is not considered (class C amplifier, forThe phase of the harmonics is not considered (class C amplifier, forinstance, generates a third harmonic component which lowers theefficiency!)

The role of device output resistance RDS is not evidenced



26/50

Harmonic Tuning Approaches

+ i =g v Rd Cd

DVGG VDD

ZL(f)ZS(f)VGG VDD

ZL(f)ZS(f)

viiD=gm·vi

Rds Cds

S

ZL,nf

ZHypothesis 1) device acts as a current source

ZDS,nf

( ) ( )∞

∑2) voltage waveform shaped by Z

( ) ( )01

cosD nn

i t I I n tω=

= + ⋅ ⋅∑2) voltage waveform shaped by ZL,nf

( ) ( )cosDS DD DS f DS fv t V I Z n t Zω∞

= − ⋅ ⋅ ⋅ +∑At high frequencies, only the first few harmonics can be effectively

controlled !

( ) ( ), ,1

cosDS DD n DS nf DS nfn

v t V I Z n t Zω=

+∑



27/50controlled !

Current Mode: Output HT

ID( ) ( ) ( ) ( )1 2 3cos cos 2 cos 3DS DDv t V V t k t k tω ω ω= − ⋅ + ⋅ + ⋅⎡ ⎤⎣ ⎦( ) ( )1 cosDS DDv t V V tω= − ⋅ ⎡ ⎤⎣ ⎦

VV0

22

1

VkV

= 33

1

VkV

=

VDDVk

vDS

0 VDS

( ) 12 3

1,

,TL

Vk k

Vδ ≡

V

k2 k3 δ β Tuned Load 0 0 1 1 Class F 0 -0.17 1.15 1

d( ) ,max

2 3, DS

DD

Vk k

Vβ ≡ 2nd HT -0.35 0 1.41 1.91

2nd & 3rd HT -0.55 0.17 1.62 2.8

( )( ), , 2 3 ,, 1add HT add TL d TLk kη η δ η= + − ⋅⎡ ⎤⎣ ⎦

( ), , , , 2 3,out f HT out f TLP P k kδ= ⋅( )2 3,HT TLG G k kδ= ⋅

( )2 3,HT TL k kη η δ= ⋅

( )

( )

, 2 3

, 2 3

,

, 2,3

f HT TL

DDnf HT n

n

R k k R

VR k k k n

I

δ

δ

= ⋅

= ⋅ =Designguidelines



28/50tn

MMIC Class F PA for X-Band

Third Harmonic Load

Fundamental Load

30

35PA_F1

Poutsim 60

70

20

25

30 Poutmeas

Bm

)

40

50

60

%)

10

15

Pou

t (dB

20

30

PAEmeas

PA

E (

@1dBcp

Pout = 28 1 dBm

Second Harmonic Load

0 5 10 15 20 250

5

( )

0

10PAEsimPout 28.1 dBm

Gain = 10 dB

PAE = 44%



29/50Pin (dBm)

PAE 44%

MMIC Double Class F PA for X-BandThird Harmonic Load @1dBcp

Pout = 30 6 dBm

Fundamental Load

Pout = 30.6 dBm

Gain = 9 dB

PAE = 40%

35 PA_F2

70 Second Harmonic Load

PAE 40%

25

30

35

Poutsim

Poutmeas50

60

70

28

30

32

34

out (

dBm

)

10

15

20

Pou

t (dB

m)

20

30

40

PA

E (%

)

PAEsim40

45

50

9,0 9,2 9,4 9,6 9,8 10,0 10,226

28

Po

0 10 200

5

10

0

10

20 PAEmeas

9,0 9,2 9,4 9,6 9,8 10,0 10,220

25

30

35

40

PA

E (%

)



30/50Pin (dBm)frequency (GHz)

Comparison between PA_1 and PA_2

60

70

30

35

PoutPA_F1

Pout

30

40

50

15

20

25

(dB

m)

PoutPA_F2

E (%

)

10

20

30

5

10

15

Pou

t

PA

E

PAEPA_F1

PAE

0

10

0 5 10 15 20 250

5

Pin (dBm)

PAEPA_F2

Pin (dBm)

Pin (dBm) G (dB) PAE (%) Pout (dBm) area (mm2)

PA_F1 18.1 10 44 % 28.1 2.85

PA_F2 21.6 9 40 % 30.6 4.1

Increase + 120% - 20% - 10% + 78% + 44 %

P. Colantonio, F. Giannini, R. Giofrè, E. Limiti, “Combined Class F Monolithic PA Design” Microwave and Optical Technology Letters Vol. 49 Is 2 2007 Pages 360 362 Copyright © 2006 Wiley Periodicals Inc



31/5049, Is. 2, 2007. Pages 360-362 Copyright © 2006 Wiley Periodicals, Inc

7W GaAs X-Band Class F PAs4.7 x 4.7 mm2 Device & PA requirements

Two stages Ten GaAs PHEMT 1.5mm Frequency : 9 6 GHz

7040

TechnologyGaAs PHEMT 0.6µm 0 8 W/mm

Frequency : 9.6 GHz Bandwidth: >5%VDD=8 V , VGG=-0.5 V , IDD ~20%Imax

40

50

60

70

30

35

40

Gai

n (d

B)

Pout

%)Frequency Performance

0.8 W/mmVBR=18VImax=500mA

10

20

30

40

20

25

Pou

t (dB

m) &

G

Gain

PAE PAE

(%

50

60

70

30

35

40Frequency Performance

in (d

B)

Pout

00 5 10 15 20

15

Pin (dBm)

10

20

30

40

15

20

25

out (

dBm

) & G

a

Gain

PAE

PAE

(%)

Performance @1dBcp

0

10

9,0 9,2 9,4 9,6 9,8 10,0 10,210

15P

Frequency (GHz)

Gain

P. Colantonio, F. Giannini, R. Giofrè, E. Limiti C. Lanzieri; S. Lavanga; ”A two stage High Frequency Class F power amplifier” Integrated

Frequency 9.6GHzPout = 38.4 dBm

Gain = 18 dBPAE = 40%



32/50

, , , ; g ; g g q y p p gNonlinear Microwave and Millimetre-wave Circuits (INMMiC 2006), Aveiro, Portugal, Jan. 2006, pp 165-168 (ISBN: 88-88748-34-2)

GaAs X-Band Class F PAs1.5 x 1.9 mm2

Pout = 0.5W PAE = 44%30

35

40

60

70

80 MMIC1

MMIC2

MMIC3

1.8 x 2.3 mm2

Pout = 1W PAE = 40% 15

20

25

30

40

50

Pout

(dB

m)

PAE

(%)

0 10 1 20 20

5

10

0

10

20

4.7 x 4.7 mm2

Pout = 7W PAE = 40%0 5 10 15 20 25

Pin (dBm)

70% PHEMT HBT WP2 .2.D.170% PHEMT HBT WP2 .2.D.1

50%

60% USA - HughesAircraft Company

Raytheon

Selex SIPAE

(%)

50%

60% USA - HughesAircraft CompanyUSA - HughesAircraft Company

Raytheon

Selex SISelex SIPAE

(%)

30%

40%

20 25 30 35 40 45

FhG -IAF

UMS

Daimler -BenzTexas - Instruments-30%

40%

20 25 30 35 40 45

FhG -IAF

UMS

Daimler -BenzTexas - Instruments-Texas - Instruments-



33/50Output Power (dBm)Output Power (dBm)

Harmonic Tuning Remarks !!!For the output harmonic tuning design, the drain currentharmonic components have to fulfil proper phase relationships

Example: To design a 2nd HT PA, the following intrinsic impedances have tobe synthesised

DDV ( ) DDV

1

1.41 DDf

VRI

= ⋅ ( )22

1.41 0.35 DDf

VRI

= ⋅ − ⋅ 3 0fR =

I1 and I2 must be opposite in phaseI1 > 0 I2 < 0

iD2.5

3.0

I

%Imax=0.2

Wrong phase

iD2.5

3.0vDS

%Imax=0.2

Right phase

1.0

1.5

2.0

VDD

ImaxvDS

iD

1.0

1.5

2.0

VD IDD

Imax

I t h i t i ti l iti l l

0.0 T/2 T 3T/2 2T0.0

0.5D

ωt

IDD

0.0 T/2 T 3T/2 2T0.0

0.5D

ωt

IDD



34/50Input harmonic terminations play a critical role

Harmonic Load/Source Pull experimentGaAs MESFET (0.5µm x 1mm)Frequency: 1 GHz j0.5

j1

j2j0.5

j1

j2j0.5

j1

j2j0.5

j1

j2• Load Pull on ZL @ f0

Z @ f 40 0+6 3j ΩZL@fo

*

j0.2

0.2 0.5 1 20

j0.2

0.2 0.5 1 20

j0.2j0.2

0.2 0.5 1 20 0.2 0.5 1 20

ZL @ f0 = 40.0+6.3j Ωη@1dBcp = 46%

ZL@foL@fo

• Re-Load Pull on ZL @ f0 (1dBcp)ZL shifts along constant supsceptance from 40.0+6.3j Ω to 78.3+j23.1 Ωη increases from 49% to 60%

• Source Pull on ZS @ 2f0 (1dBcp)Source Pull on ZS @ 2f0 (1dBcp)Case 1 – maximum η = 49%Case 2 – minimum η = 36%

P. Colantonio, F. Giannini, E. Limiti, V. Teppati, “An Approach to Harmonic Load– and Source–Pull Measurements for High-Efficiency PA



35/50Design,” IEEE Trans. on Microwave Th. and Tech., vol.52, n.1, Jan. 2004, pp.191 - 198.

Harmonic PA Design

Device: GaAs MESFET (0.5µm x 1mm)

Frequency : 5 GHzFrequency : 5 GHz

Bias point : VDD=5 V , VGG=-1.5 V , IDD ~30%Imax)

Full non linear active device modelling (equivalent circuit based)

Design StrategiesTuned LoadClass EClass F2nd HT2 HT2nd & 3rd HT



36/50

Tuned Load vs. 2nd HT PAs

Tuned Load

2nd HT150

250

s [m

A]

2nd HT Id[A]

0.4

2nd HT Id[A]

0.40.4

12

0 0.1 0.2 0.3 0.4050

Ids

Tuned LoadTuned Load

4

8

12

Vds

[V]

0 20Vds [V]0.0

0 20Vds [V]0 20Vds [V]0.00.0

0 0 0.1 0.2 0.3 0.4time [ns]Using a proper 2fo input termination

0.70.80.9

1

Vgs 1

[V]

0.03Using a proper 2fo input termination

2 3 4 5 6 7 80.50.6 Shorting input harmonic terminations

0

0.01

0.02

Vgs 2

[V] Using a proper 2fo input termination

Shorting input harmonic terminations



37/502 3 4 5 6 7 8

Pin [dBm]

0

Class E vs. Harmonic Tuning0.3

Id

[A] 2nd & 3rd HT2 & 3 HT

Class E

fo= 5 GHz

0 5 10 15Vds [V]

0

MESFET (1mm) Class E simulated

2nd & 3rd HT simulated

2nd & 3rd HT measured

60

70

80

24

26

28

]

2nd & 3rd HT measured

30

40

50Class E

η (%

)

18

20

22Class E

Pout

[dB

m]

4 6 8 10 12 14 16 18 200

10

20

4 6 8 10 12 14 16 18 2014

16

18



38/50Pin [dBm] Pin [dBm]

Harmonic Tuning PAs

70 26

5 GHz measurements

50

60

70PAE [%]

24

25

26Pout [dB]

30

40

22

23

10

20

19

20

21

12 14 16 18 200

Pin [dBm]

Tuned Load

12 14 16 18 2019Pin [dBm]

fClass F

2nd HT

Increasing the number of controlled harmonics

increase device performance capabilities

increase circuit complexity and losses



39/502nd & 3rd HTincrease circuit complexity and losses

Two-tones measurements

fc = 5.0 GHz ∆f = 50 MHz

-10

IM3[dBc]

-203[ ]

Tuned Load

Class F-30

Class F

2nd HM

2 d & 3 d HM-40

2nd & 3rd HM

-15 -10 -5 0-50

OBO (output back-off)



40/50OBO (output back-off)

2nd HT on 20GHz PA

26 10020 GHz - 1 stage amplifier

ut (d

Bm

)

18

22

60

80

AE

(%)

20 GHz 1 stage amplifier

with 2nd harmonic termination

h t V i l tiPo

10

14

20

40

PA

26 100

short Vs. manipulation

Pin (dB)6

4 8 12 16 200

18

22

B (d

Bm

)

60

80

E (%

)

10

14P1dB

20

40 PAE

Performances

P1dB 22.8 dBm

618,5 19 19,5 20 20,5

Freq. (GHz)0

PAE 52 %

Bandwidth 1 GHz



41/50

C-Band GaN 2nd HT PA

0

5

10 S_Parameter

er (d

B)

Device physical FeaturesAlGaN/GaN .5 um HEMT 1mm

-20

-15

-10

-5

atte

ring

Para

met

e

S11Sim S11Meas

Imax = 0,4 AVk = 3,5 V

Bias pointV = 3 V (20% I )

1 2 3 4 5 6 7 8 9-30

-25Sca

Frequency (GHz)

Sim Meas

S22Sim S22Meas

S21Sim S21Meas

VGS = -3 V (20% Imax)VDS = 25 V

Operating Frequencies5 5GHz for Radar applications Performance @ 5 5GHz5.5GHz for Radar applications

25

30

35

40

50

60

70

80 PoutSim

GainSim

GainMeas

GainMeas

Performance @ 5.5GHz

ain

(dB

)

EffSim

PAESim

EffMeas

PAEMeas

AE

(%)

10

15

20

25

20

30

40

50

out (

dBm

) & G

a

ienc

y (%

) & P

A

10 15 20 25 300

5

10

0

10

20

Po

Pin (dBm)

Effic

i

Pout = 2W & η = 63%



42/50Pout = 2W & η = 63%

C-Band GaN 2nd HT PA

Performance @ 5.5GHzPout = 33 dBm

62

64 40 C/I and Efficiency at the max Pout

C/I

η = 63%Bandwidth : >20%VDD=25V & VGG=-3V

56

58

60

62

35

C/I

(dB

c)

Effic

ienc

y (%

)

Efficiency

30

35

60

70

80 Frequency Performance

B) (%

) 60 80 100 120 14052

54

56

30

Dra

in E

D i Bi C t ( A)

60

70

USAUniv of Connecticut

C-Band-State of the artTARGETItaly, MiMEG15

20

25

30

40

50

60

Sim Measm) &

Gai

n (d

B

(%) a

nd P

AE

( Drain Bias Current (mA)

40

50USAUniv. of Illinois, Urbana

Univ. of Connecticut, Storrs

FranceEIC-LUSAC

FranceTIGER Istfic

ienc

y (%

)

0

5

10

0

10

20

30 Sim Meas

Pout

(dB

m

Effi

cien

cy(

20 25 30 35 4020

30

TIGER Ist.USAUniv. of California, Santa Barbara

Eff

P. Colantonio, F. Giannini, R. Giofrè, E. Limiti, A. Serino M. Peroni, P. Romanini, C. Proietti “A C-Band High Efficiency Second Harmonic Tuned Hybrid Power Amplifier in GaN technology,”

4,8 5,0 5,2 5,4 5,6 5,8 6,0 6,20 0

Frequency (GHz)



43/50Output Power (dBm)Band High Efficiency Second Harmonic Tuned Hybrid Power Amplifier in GaN technology,

IEEE Transactions on MTT, Vol. 54, Is. 6, Part: 2 - 2006

Linearity Design Issues

Modern TLC systems have to simultaneously fulfill output power, ACPR (or C/I3) and efficiency requirements

• PA Designer challenges

Select the best bias point

( )3 3 , ,,m in f out fIM g f∝ ⋅ Γ Γ

Select the best device output loads

j0.5

j1

j260

40

20

0Bm

)

60

40

20

0Bm

) POUTj0.2

-20

-40

-60

80P out

, P I

MD

(dB

-20

-40

-60

80P out

, P I

MD

(dB

PIMD

0.2 0.5 1 2

-j0 2

0000 10000

PAE

-40 -30 -20 -10 0 10 20

-80

-100

-120

-140-40 -30 -20 -10 0 10 20

-80

-100

-120

-140

-j0.2

-j0.5 -j2

C/I



44/50

40 30 20 10 0 10 20P (dBm)

40 30 20 10 0 10 20P (dBm)

-j1

Device terminationsThe Volterra Series approach has been adopted to analytically infer design guidelines.

The functions representing non linear circuit elements are approximated throughThe functions representing non linear circuit elements are approximated through a polynomial series of input (vgs) and output (vds) voltages

RGLG

DgdRD LD

Ri

Qgsvgs

vds

Dgs

Cds

Id

QgdYG YL

i

LS

RS

CPGCPD

( )2

26

m Lg YB F B B Y

⎡ ⎤+⎢ ⎥

⋅ ⋅ ⋅⎢ ⎥⎛ ⎞

where( ), ,2 2

3 2 62 8, ,2

,L f L L Gm dm

md L

L f L L G c gs

B F B B Yg gg

g GIM

9 Y Y Y Y j2 f C8

π

∆

∆

⋅ ⋅ ⋅⎢ ⎥⎛ ⎞⎢ ⎥⎜ ⎟−⎝ ⎠⎣ ⎦∆ = −

⋅ ⋅ ⋅ +, , , , , 2

G G G

L x L x L x c c

Y G jBY G jB x f f f

= += + = ∆



45/50

Out-of-band terminationThe key role of output base-band impedance (or biasing networks) on IMD asymmetry performance has been highlighted1 and experimentally2 demonstrated.

( )2

26

m Lg YF B B YB

⎡ ⎤+⎢ ⎥⎢ ⎥⎛ ⎞( ) 6

,2 2

3 2 62 82

, ,L L L Gm dm

md L

L f L L c

f

G gs

F B B Yg gg

g GIM

9 Y Y Y Y j2 f C8

B

π∆

∆ ⋅ ⋅ ⋅⎢ ⎥⎛ ⎞⎢ ⎥⎜ ⎟−⎝ ⎠⎣ ⎦∆ = −

⋅ ⋅ ⋅ +, ,2L f L L cG gsj f8 ∆

∆IM3=0 if BL,∆f=0

1 P. Colantonio, F. Giannini, E. Limiti, A. Nanni, “Investigation of IMD Asymmetry in Microwave FETs via Volterra Series,” Proc. of Gallium Arsenide Applications Symposium, Oct. 2005, pp 53-56.

2 B. De Carvalho, J. C. Pedro, “Comprehensive explanation of distortion sideband asymmetries,” IEEE Trans. on MTT, vol. 50, n. 9, Sept. 2002, pp.



46/502090 – 2101.

Harmonic terminations

From the Volterra analysis, an alternative condition to null the IMD asymmetry arises:

( )2

26

, 2,2,m L

L f Gm dL L

g YB Yg g

gF B B∆

⎡ ⎤+⎢ ⎥

⋅ ⋅ ⋅⎢ ⎥⎛ ⎞⎢ ⎥⎜ ⎟

∆IM3=0 if F(BL,BL2)=0

3 2 62 8, ,2

mmd L

L f L L G c gs

gg G

IM9 Y Y Y Y j2 f C8

π∆

⎢ ⎥⎜ ⎟−⎝ ⎠⎣ ⎦∆ = −⋅ ⋅ ⋅ +

B B 0BL=BL2=0

• Moreover, if condition BL=BL2=0 is fulfilled, it is possible to identify an optimum value for GL2 toMoreover, if condition BL BL2 0 is fulfilled, it is possible to identify an optimum value for GL2 tominimize IM3

where

( ), 1

,2 3 31 , 3 32 3

LL

L d m L m

G FG

F G g g G gω

ω

∆

∆

⋅= −

− ⋅ − ⋅( )( )

1 2

2 22 2

md L d m

d m md m L m L

F g G g g

g g g g G g G

= − + ⋅

⋅ − +



47/50

Linearity & Efficiency Design Guidelines

Step 1 2 3 4

Action

AimFind the optimumload condition to

Load Pull @fo

Identifying theoptimum source

Source Pull @2fo

Decreasing YL,f0(its real part)

Tuning YL@fo

Selecting the load@2f0 to obtained

Load Pull @2fo

maximize Poutand to null BL

load able tomodify the outputcurrent phase

( )according to theHT theory (i.e.GL*≅GL/1.41)

@ 0BL,2=0 while itsreal part waschosen accordingto HT theory

0 0 1

0.005

0 01

0.005

0 0 1

0.005

0 0 1

0.005

0 01

0.005

0 01

0.0050.005

0.01

0.01 0.005

0.005

0.005

0.01

0.0050.005

0.010.01

0.01 0.005

0.005

0.005

0.01

0.01 0.005

0.005

0.005

0.01

0.0050.005

0.010.01

0.01 0.005

0.005

0.005

0.01

0.01 0.005

0.005

0.005

0.01

0.0050.005

0.010.01

0.01 0.005

0.005

to HT theory

0.005

0.01

0.0 1

0.020.040.04

0.01

0.02

PA H_IMD

Loads @ 2foSynthetised

PA L_IMD

0.005

0.01

0.0 1

0.020.04

0.005

0.01

0.0 1

0.020.040.04

0.01

0.02

0.04

0.01

0.02

PA H_IMD


PA L_IMD

PA H_IMD


PA L_IMD

PA H_IMD


PA L_IMD

0.02

0.01

0.020.020.02

0.01

PA H IMD

Loads @ foSynthetised

PA L_IMD

0.02

0.01

0.020.020.02

0.01

PA H IMD


PA L_IMD

PA H IMD


PA L_IMD

0.02

0.01

3232.7

0.020.020.02

0.01

3232.7

ΓL,ext plane at 2f0: GL,2 (red)and BL,2 (black)

H_IMDH_IMDH_IMD

ΓL,ext plane at f0: GL (red) andBL (blu)

ΓL,ext plane at f0:Pout (black), GL (red) and BL (blu)



48/50

Linearity & Efficiency Design Guidelines

30

35

60

70

)

PA - High IMD PA - Low IMD

High Efficiency PA

10

15

20

25

20

30

40

50

t (dB

m) &

Gai

n (d

B)

Eff_PAL_IMD

Eff_PAH_IMD

Effi

cien

cy (%

)

0 4 8 12 16 20 24 280

5

0

10Pout

Pin (dBm)Intermodulation ComparisonAM/PM Comparison

High Efficiency Low IMD PA

2 5

3,0

3,5

4,0

4,5Intermodulation Comparison

PA - High IMD PA - Low IMD

)

12

16p

eg)

PA - High IMD PA - Low IMD Tecnology

• AlGaN/GaN HEMT

0,5

1,0

1,5

2,0

2,5

∆IM

3 (dB)

4

8

AM

/PM

(de

• Gate periphery 1mm

20 40 60 80 100-0,5

0,0

∆f (MHz)

0 4 8 12 16 20 24 280

Pin (dBm)

P Colantonio F Giannini R Giofrè E Limiti and A Nanni “Power Amplifier Design Strategy to null IMD asymmetry ” 36th European



49/50P. Colantonio, F. Giannini, R. Giofrè, E. Limiti and A. Nanni, Power Amplifier Design Strategy to null IMD asymmetry, 36th European

Microwave Conference 2006 Conference Proceedings. Manchester, UK, September 2006, pp. 1304-1307. (ISBN 2-9600551-6-0)

Conclusions

Starting from Tuned Load criteria, main device power figures (Pout, η, Gain) have been discussed and related to device physic parameters (Imax, Vk) and bias point p y p ( ) p(Class A, AB, B).

Power balance considerations have been discussed to increase device performances.p

Classical (Class E and Class F) approaches have been reviewed

Harmonic Tuning approaches for high efficiency & high frequency PA’s have beenHarmonic Tuning approaches for high efficiency & high frequency PA’s have been analysed.

Several experimental results have been discussedHarmonic load/source pull on GaAs-PHEMT @1GHz Harmonic manipulated GaAs-PHEMT PA @5GHz 2nd HT GaAs-PHEMT PA @20GHz (Fujitsu) Class F GaAs-PHEMT PAs for X-Band Applications (@9.6GHz)pp (@ )2nd HT GaN-HEMT PA @5.5GHzLinearity Issues



50/50

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