High-Bandwidth Memory (HBM2E+) 4G I/O Design Techniques for 7nm Technology & Below August 22, 2019

Santosh Narawade, IP Engineering Manager

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• HPC Market and Trends

• Introduction: HBM2E

• System Architecture

• Challenges & Problem Statement

• Solution

• Next Gen HBM

• Summary

Agenda

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IP Subsystem Requirement

HBM: Need of the Market Driving Next-Gen HPC Applications

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• Increase in Cores, BW and Data: Driving New Silicon Markets– Deep Learning and Networking Applications

ASIC Market Requirements & HBM Solution

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• High-Bandwidth Memory with High-Bandwidth Memory Interface

• 2.5D System in Package

• High-Speed SerDes IP Sub-System

– Enables Ultra High Port Density for Switching and Routing Applications

– High Speed Inter-node Connectivity for Deep Learning and Networking Applications

HBM Sub-System

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• Increase Threshold Voltages (Vt)

• Complex DRC Rules

• Restricted Leakage Power

• Speeds follow Moore Law; Process Node doesn't

• New Design methodologies (for 7nm and below)

• Physical Design of Large (>10 mm2) & High-Speed ASIC

• Power (IP and system level) and Timing closure

• Thermal Sign off

• Multiple Handshake IP

• Increasing Fab Cost

• Zero Tolerance: Time2Market

Problem Statement- HBM2E+ (4G IO Design)

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Quantity 16nm 28nm Comparison

Min Metal Stack Offered 7M 5M

Signal Routing Layer Pitches P64, P80, P126 P100, P200 Misalignment Issues

Track Availability (# per um) 12.5 10 25%

Site Density (# per um2) 19.3 8.2 135%

NAND D1 Pin Density 14.5 8 81%

Track Density is not increasing at the same rate as Pin Density when we scale down to a lower node. More routing layer required.

Implementation Challenges: HBM2 2.5D SiP

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Design Solution

Circuit Design:

• Max out Initial Condition Usage

• Avoid Large Loading

• Plan Symmetry of Delays, Gates, Placement, Power Rail, Usage

DFM Techniques:

• Plan for worst Failures to avoid Mask Cost

• Touch better than Plan Schedule

Test Structure:

• Keep Sufficient Test debugs

• Avoid Last minute changes

Static Timing:

• Minimum Path Delays

• Avoid feedback points

DFT:

• Systematic full-chip partitioning and core wrappers

• Hierarchical test points, BIST/scan, compression, memory repair, power aware ATPG and enablement of wafer probing

Modelling:

• Model wherever possible

• Make Ordinal Failure Classes

Significant Increase in #PVT Corners

“Architecture” - ”DFM Checks” - “SI-PI” - “Test Plan” -“Design Signoff”

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Selection of Accurate Design Flow

Functional Spec

Architecture Define

Schematic Design

Layout Design

Post Layout RC Extraction & Simln. Is it Meeting Spec?

Signoff Checks

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Structure Alignment

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• The models can be generated for three different corner conditions: typical, minimum, and maximum. In a typical model, the data will be obtained for nominal supply voltage, nominal temperature, and nominal process parameters; in a minimum model, the data will be obtained with the lowest supply voltage, high temperature, and weak process parameters; and for a maximum model, the conditions will be the highest supply voltage, low temperature, and strong process parameters.

• Each of these conditions leads to typical, slow, and fast models. A fast model is created by considering the highest current values with the fast transition time and the minimum package characteristics. On the other hand, the lowest current values with a slow transition time and maximum package values will produce a slow model.

I/O Modeling Solution

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HBM2E+ 4Gbps I/O Eye-Diagram

Zoom

Version

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HBM2E+ 4Gbps I/O: Simulation Results

I/O Delay Diagram I/O rfmm Diagram

I/O Periodic Jitter Diagram I/O Duty Cycle Diagram

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IP Test Architecture

SiFive’s HBM2E IP Test Architecture

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•IO LIBRARY Simulations•PVT Simulations including skewed corners•Monte Carlo Simulations•Reliability Check•ERC Check•Timing .lib Generation•BMOD Check if any•AMS Simulations•Post Layout Simulations•ESD Checks if any•CDM Checks•Layout Routing Review•IR Drops/EM Checks•EOS/Burnin/Aging Sims•Padcap Checks•Decap Checks•Power Checks•Leakage Checks•Jitter Checks•SI DCD Checks•Hysterisis Checks•Skew Checks

Target Checklist

Cell name Usage commentHBM_DATAIO Single ended IO (DQ & CMD/ADDR) Horizontal & vertical poly oriented cells

HBM_CLK_INPUT Differential Input ( RDQS ) Horizontal & vertical poly oriented cellsHBM_CLK_OUTPUT Differential Output ( CLK & WDQS ) Horizontal & vertical poly oriented cells

HBM_REFGEN VREF pad Distributed by abutment. Horizontal & vertical

poly oriented cellsHBM_VDD Core VDD cell Distributed by abutment . Horizontal & vertical

poly oriented cellsHBM_PVT

COMPENSATION

For PVT compensation within the DIE-DIE

area.

Distributed by abutment. Horizontal & vertical

poly oriented cellsHBM_VDDIO IO Power Distributed by abutment.

HBM_VSS Core Ground Distributed by abutmentHBM_VSSIO IO Ground Distributed by abutment

HBM_DECAP VDDQ-VSSQ decoupling cap cell To provide better decap

Cell list for the DIE-DIE IO LIBRARY

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Top Level Solution

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Phase Wise Solution

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Next Generation HBM2E+ IP Subsystem

Supports up to 4Gbps/Pin data rates and beyond

Supports up to 8 channels (16 pseudo channels)

Support up to >400GBytes of total Bandwidth

Supports full DFI4.0 compliant controller and PHY interface

Supports multi-port AXI interface

Supports different schemes of arbitration and scheduling (QoS)

Supports different address mapping modes

AXI (Advanced eXtensible Interface) based HBM2E+ IP subsystem

development

Targeting 4Gbps per-pin data rates, and beyond, in TSMC’s latest

FinFet technologies

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• Challenges for Designing HBM2E+ PHY and I/O were identified.

• Different techniques for innovative design solution of HBM2E+ (>4Gbps) are implemented

– Design Solution

– I/O Modeling

– Top Level Solution

– Phase Wise Solution

• Silicon Validation

– High-speed interface test chip taped-out with HBM2E 3.2Gbps and HBM2E+ 4Gbps Interface in TSMC’s 7nm technology-Q1’19

– HBM2E and HBM2E+ IP Subsystem validation platform tape-out in TSMC’s 7nm technology – Q3’19

• SiFive’s HBM2E IP Subsystem (Controller + PHY + IO) in TSMC 7nm technology is available for SoCs for HPC and AI applications

• The Next Gen HBM2E+ IP Sub-System Specification is being analyzed for SoCs enabling next generation high bandwidth applications

Summary

Thank You