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Hi-PBD : Hi erarchical P latform- B ased D esign Method ----research & implementation
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Transcript of Hi-PBD : Hi erarchical P latform- B ased D esign Method ----research & implementation
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Hi-PBD: Hierarchical Platform-Based Design Method ----research & implementation
Jihua Chen , Zhihui Xiong, Sikun Li
Speaker: Zhihui Xiong
VLSI Lab. National University of Defense TechnologyChangsha, China
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Outline
Related Work
Conclusions & Future Work
mainstream VLSI design methodologies existing co-design environments
drawbacks
YH-PBDE: Implementation of Hi-PBD method
Research on Hi-PBD
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Related Work mainstream VLSI design methodologies
Timing-Driven Design: TDD, deep sub-micro ASIC design
Block-Based Design: BBD, supports IP reuse
Platform-Based Design: PBD, supports system reuse, including reuse of IPs, models, tools, libraries and design flows
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existing co-design environments
VULCAN: by R. K. Gupta, 1993, Stanford University.
COSYMA : by R. Ernst, 1996, Tech. Univ. of Braunschweig
since then, others including: Ptolemy, Polis, PeaCE, …
SCE: by D. D. Gajski, 2003, TIMA Lab. France
some commercial tools
• Cadence VCC• CoWare N2C• Synopsys CoCentric Studio
Related Work (cont.)
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drawbacks
little support for Platform-Based Design methodology mainly support IP level reuse, not system level reuse
only support some phases of SoC design, and little support for the overall phases
Related Work (cont.)
no real separation of design concerns• no separation of function from structure
• no separation of computation from communication
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Outline
Related Work
Conclusions & Future Work
ideas overall structure
more words on Virtual Components Level
YH-PBDE: Implementation of Hi-PBD method
Research on Hi-PBD
features
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Research on Hi-PBD
ideas
first of all, let’s see a “true” story……
One day, Bill Gates discovered a big bag of dollars.However, it is too high to get it directly.
$$ how can Iget i t?
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ideas
first of all, let see a “true” story…… (cont.)
After some consideration, he decided to use a ladder.
$$ ha ha . . .
Research on Hi-PBD
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ideas
first of all, let see a “true” story…… (cont.)
Then, he climbed towards the dollars.
$$a good
i dea . . .
Research on Hi-PBD
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ideas
first of all, let see a “true” story…… (cont.)
Finally, he got the bag of dollars, and became the richest man in the world.
$$
am Idreami ng?
Research on Hi-PBD
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ideas
now, a similar thing happens with SoC design ……
abstracti on
complexity
al gori thms functi onal model s
detai l ed RTL descri pti ons embedded software codes SoC i mpl ementati on model s
since too many things to be done:• Hw/Sw partitioning
• co-simulation
• performance evaluation
• hardware & interface synthesis
• embedded software generation• ……
but, there i s a too bi g gapbetween them, so i t i s very
di ffi cul t to do di rect mappi ng
map the SoC functi onal modelto SoC i mpl ementati on model
Research on Hi-PBD
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ideas
now, a similar thing happens with SoC design ……
abstracti on
complexity
al gori thms functi onal model s
detai l ed RTL descri pti ons embedded software codes SoC i mpl ementati on model s
“ vi rtual desi gn” SoC abstracti on model
things will be better of, if there exists a “virtualdesign” level
• Hw/Sw partitioning
• hardware & interface synthesis
• embedded software generation
Research on Hi-PBD
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overall structure
3 design levels 2 design mappings• system modeling level
• virtual components level
• real components level
• design planning
• virtual-real synthesis
1 platform library• to achieve system level reusability
l evel 0
IPs Commu. CPU RTOS+EmbeddedSoftware
VHwIP VCommuIP VSwIP
domai n pl atform
functi on/performance anal ysi s
si mu. & eval . atal gori thm l evel eg.(
based on C/C++)
HW/SW co-si mu. atmessagi ng l evel (eg.
based on SystemCsi mu. core)
HW/SW co-si mu. atRTL l evel eg.(based on FPGA
board)
functi on & performance constrai nt
C/SystemC
SystemC
SystemC/Veri l og
l evel 1
l evel 2
l ater desi gn
mappi ng L0-L1
mappi ng L1-L2
pl atform Li b.& templ ates
l evel 0 l evel 1 l evel 2
opti mi zati on
reuse
reuse
reuse
reuse
reuse
Research on Hi-PBD
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system modeling level (SML)
describes function and performance of SoC at algorithm level
system modeling based on CTG model• CTG: Constrained Taskflow Graph
• Hierarchical FSM + coarse grained CDFG + performance constraint
overall structure (cont.)
A
B C D E
F G
HCT_Begi n CT_End
BT_Begi n
PT_Begi n PT_End
cond_2
cond_1
Research on Hi-PBD
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abstracts the RTL SoC system architecture
serves as a connecting link between the system modeling level and real components level
Virtual Components Level (VCL)
avoids direct synthesis from system model to the final SoC target
overall structure (cont.)
• virtual hardware components (VHwIPs)
• virtual software components (VSwIPs)
• virtual communicator components (VCommuIPs)
VCommuIP_0 VCommuIP_1
VHwIP_Bri dger
VHwIP_0
VHwIP_1
VHwIP_2
VHwIP_3
VHwIP_4
VSwIP_0
VSwIP_1
VSwIP_2
Research on Hi-PBD
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RTL Hw/Sw SoC system
fast prototyping based on FPGA board, for RTL simulation and performance analysis
HW part: hardware accelerator modules (such as co-processor, DSP, ASIC), Input/Output controller devices
SW part: RTOS, device driver, application processes
Real Components Level (RCL)
overall structure (cont.)
Hardware Part
Bridge
Arbiter
ProcessorLocal Bus
SRAM
RHwIP_0 RHwIP_1 RHwIP_2
RHwIP_3 RHwIP_4
Arbiter
Timer
DMAIrq Bridge
EmbeddedProcessor
DataCache
Inst.Cache
Software Part
Mem
. Mana.
Proc. M
ana.P
roc. Sche.
Proc. C
omm
.
……
APIs
RTOS
Device DriversDevice Manager
RSwIP_0 RSwIP_1 RSwIP_2
Research on Hi-PBD
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2 design mappings ---- mapping L0-L1 the mapping from System Modeling Level to Virtual Components Level, we call it Design Planning
overall structure (cont.)
some tasks are partitioned to hardware
other tasks are partitioned to software
A
B C D E
F G
HCT_Begi n CT_End
BT_Begi n
PT_Begi n PT_End
cond_2
cond_1
VCommuIP_0 VCommuIP_1
VHwIP_0
VHwIP_1
VHwIP_2
VSwIP_0
VSwIP_1
VHwIP_Bri dger
VSwIP_2
VHwIP_3
VHwIP_4
Research on Hi-PBD
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Hardware Part
Bridge
Arbiter
ProcessorLocal Bus
SRAM
RHwIP_0 RHwIP_1 RHwIP_2
RHwIP_3 RHwIP_4
Arbiter
Timer
DMAIrq Bridge
EmbeddedProcessor
DataCache
Inst.Cache
Software Part
Mem
. Mana.
Proc. M
ana.P
roc. Sche.
Proc. C
omm
.
……
APIs
RTOS
Device DriversDevice Manager
RSwIP_0 RSwIP_1 RSwIP_2
2 design mappings ---- mapping L1-L2 mapping from Virtual Components Level to Real Components Level, we call it Virtual-Real Synthesis
overall structure (cont.)
VCommuIP_0 VCommuIP_1
VHwIP_0
VHwIP_1
VHwIP_2
VSwIP_0
VSwIP_1
VHwIP_Bri dger
VSwIP_2
VHwIP_3
VHwIP_4
virtual hardware is synthesized to real (RTL) hardware
virtual software is synthesized to embedded process
virtual communicator is synthesized to On-Chip Bus
Research on Hi-PBD
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more words on Virtual Components Level
virtual component model
structure part behavior part
• construct “virtual design”• for partitioning• for synthesis
• for software generation• for co-simulation• for verification & evaluation
vi rtual component modelstructure part
modul e cl ass name port l i st submodul e l i st channel l i st vari abl e l i st
behavi or part
behavi or descri pti on functi on sensi ti ve si gnal l i st submodul e i nstanti ati on and port mappi ng vari abl e i ni ti al i zati on l i st
Research on Hi-PBD
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more words on Virtual Components Level (cont.)
modeling hardware at VCL
Adder
p_out=p_i n1+p_i n2 p_outch_out
p_i n1ch_i n1
p_i n2ch_i n2
a simple module (adder)
a more complex module
modeling of these two modules
SC_MODULE(modA) { sc_outmaster<i nt> P1; . . .};
SC_MODULE(modB) { sc_i nsl ave<i nt> P2; sc_outmaster<i nt> P3; . . .};
SC_MODULE(modX) { sc_i nmaster<i nt> P4; sc_l i nk_mp<i nt> ch1; modA *A1; modB *B1; … SC_CTOR(modX) { A1 = new modA("A1"); B1 = new modB("B1"); A1(ch1); B1(ch1, P4); }};
SC_MODULE(Adder) { sc_i n<i nt> p_i n1; sc_i n<i nt> p_i n2; sc_out<i nt> p_out;
voi d adder_func() { p_out = p_i n1 + p_i n2; }
SC_CTOR(Adder) { SC_METHOD(adder_func); sensi ti ve << p_i n1; sensi ti ve << p_i n2; }};
port l i st
modul e name
structure part
channel l i st
submodul e l i st
behavi or part
submodul e i nstanti ati onand port mappi ng
sensi ti ve si gnal l i st
behavi or descri pti onfuncti on
Research on Hi-PBD
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more words on Virtual Components Level (cont.)
modeling software at VCL wrap software process using SystemC module
• process (task) template in uC/OS II
• adder example process
• wrapped adder
• variables and external APIs are mapped to ports
• normal statements are mapped to behaviors
• RTOS services are mapped to SystemC core
process (task) prototype i n uC/OS I I
voi d YourTask (voi d *pdata){ for(;;) { / * user code */ / * cal l one of uC/OS I I servi ce:*/ OSMboxPend(); OSQPend(); OSSemPend(); OSTaskDel (OS_PRIO_SELF); OSTaskSuspend(OS_PRIO_SELF); OSTi meDl y(); OSTi meDl yHMSM(); / * user code */ }}
an adder wi th output functi on i n uC/OS I I
i nt gbl _data1;i nt gbl _data2;i nt gbl _resul t;
voi d adderTask (voi d *pdata){ for(;;) { gbl _resul t = gbl _data1 + gbl _data2; / /user code LCD_Di spl ayStri ng("%d + %d = %d\n", gbl _data1, gbl _data2, gbl _resul t); / /user code
OSSemPend();/ / cal l RTOS servi ce }}
Adder
p_out=p_i n1+p_i n2
i mpl emented by SystemC core
p_out ch_out
p_i n1ch_i n1
p_i n2ch_i n2
LCD_API ch_LCD
Research on Hi-PBD
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more words on Virtual Components Level (cont.)
modeling communication at VCL
connects multiple V.C.s
message transmitting flow
step1: consumer 2 requires data from producer 0
vi rtual communi cati on component
message transmi tti ng
5P5
1
2
0P0
P1
P2
3
4
P3
P4
producer0
producer1
producer2
consumer0
consumer1
consumer2
step 1step 2
step 3
step 4 step 5
step 6
step2: communicator transmits the message to producer 0
step3: producer 0 receives data requirement
step4: producer 0 sends data to consumer 2
step5: communicator transmits the message to consumer 2
step 6: consumer 2 receives the data
Research on Hi-PBD
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features
hierarchical design flow
supports system level reuse well
• 3 design levels• 2 mappings
• enables reuse of design templates on each design level
• enable reuse of mapping process & mapping results
achieves separation of design concerns
• separation of function from structure
• separation of computation from communication
Research on Hi-PBD
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Outline
Related Work
Conclusions & Future Work
architecture
snapshots
YH-PBDE: Implementation of Hi-PBD method
performance & power estimation
Research on Hi-PBD
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model i ng/si mul ati on & mappi ng tool s
architecture modeling/simulation & mapping tools
helper tools platform manager
• do modeling and simulation at the three design levels• do mapping between design levels
• for system level reuse
Level 0
Level 1
Level 2
mappi ng L0-L1
constrai ntassi gnment
parti ti on
mappi ng L1-L2
synthesi s
pl atformmanager
domai npl atform
sel ect
reusetempl ate
reus
e
reuse
opti mi zati on
reuse
reuse
reuse
hel per tool s
Li b. manager
R.C.
V.C.
algori thm
performanceanal i zer
retargetabl ecompi l er
YH-PBDE: Implementation of Hi-PBD method
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performance & power estimation
estimation at System Modeling Level • based on combination of SimpleScalar and Sim-Wattch
• and made some improvements
estimation at Virtual Components Level • establish performance character for each virtual component
• establish power character for each virtual component
• while simulating on SystemC core, calculate performance and power
estimation at Real Components Level • performance are estimated via FPGA development suites
• Power(system) = Power(Sw) + Power(Hw)
apply different estimation methods for different levels
YH-PBDE: Implementation of Hi-PBD method
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snapshots system modeling, task attribute editor
YH-PBDE: Implementation of Hi-PBD method
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snapshots (cont.) system modeling, taskFSM editor
YH-PBDE: Implementation of Hi-PBD method
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snapshots (cont.) virtual components editor
YH-PBDE: Implementation of Hi-PBD method
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snapshots (cont.)real components editor
YH-PBDE: Implementation of Hi-PBD method
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snapshots (cont.) partitioning interface
YH-PBDE: Implementation of Hi-PBD method
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Outline
Related Work
Conclusions & Future Work
YH-PBDE: Implementation of Hi-PBD method
Research on Hi-PBD
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Conclusions
Hi-PBD method improves high level design efficiency
The implemented environment supports Hi-PBD well
Conclusions & Future Work
Introduction of Virtual Components Level makes it more easy to do SoC high level design
Future Work
to do more research on Virtual-Real Synthesis
to do more work on embedded software generation
to do more work on power-aware Hi-PBD method
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Thank you