Hardware Pace Using Slope Detection Tony Calabria 10/22/2012.
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Transcript of Hardware Pace Using Slope Detection Tony Calabria 10/22/2012.
![Page 1: Hardware Pace Using Slope Detection Tony Calabria 10/22/2012.](https://reader036.fdocuments.in/reader036/viewer/2022062423/56649ca65503460f94968bce/html5/thumbnails/1.jpg)
Hardware Pace Using Slope Detection
Tony Calabria
10/22/2012
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2
The Concept
Subhead text here
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ECG + Pacemaker Signal
![Page 4: Hardware Pace Using Slope Detection Tony Calabria 10/22/2012.](https://reader036.fdocuments.in/reader036/viewer/2022062423/56649ca65503460f94968bce/html5/thumbnails/4.jpg)
Slope Detection
• Frequency components of ECG lie in 0.05 – 150Hz. Frequency of PACE components reside in >1KHz.
• Monitor for Slope of Pace Signal while ignoring ECG signal slope.
• Need to measure the rate of change of voltage to determine slope: Differentiator Circuit– Output signal should not respond to ECG – Pace Signal should only pass– Looking for a specific dV/dT
• Pace Spec required to meet: – 2mV Amplitude Signal– 100us Period Signal
![Page 5: Hardware Pace Using Slope Detection Tony Calabria 10/22/2012.](https://reader036.fdocuments.in/reader036/viewer/2022062423/56649ca65503460f94968bce/html5/thumbnails/5.jpg)
Alert/Trigger
• Need to trigger an Alert bit when Pace is present
• Using a window comparator, a pulse can be created once the output of the Differentiator Circuit shows a change outside the preset window.
• Threshold limits set externally depending on amplitude of Differentiator Output at minimum Pace signal spec requirements (2mV, 100us).
• SR Latch can be used to latch and hold the value of the Comparator output indicating a Pace Signal has occurred.
• Mandatory that an ECG Signal does not create a response by the comparator outputs.
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6
Differentiator Circuit
• Looking for specific slope: dV/dT change
• Duration of slope produces output amplitude
• R used to set gain
• Frequencies above fc, the circuit is acting as ordinary inverting amplifier
CRfc
21
Source: http://circuitalley.phpnet.us/circuit3.html
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7
Window Comparator
• The Differentiator output signal will idle within the window when PACE is not present
• When PACE appears, the output of the differentiator circuit will toggle, forcing the voltage outside the limits of the window comparator– The output to pulse low. – That low pulse must be latched and held until read back by a uC or GPIO
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SR Latch
• SR Latch output high once Window Comparator outputs low pulse
• Reset line is pulled high
• Latch stays until reset by user.
• Would need to reset with every QRS waveform if wanting to monitor for pace with each heartbeat
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9
Proposed Circuit
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10
Circuit Stability
Subhead text here
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11
Differentiator Circuit Analysis
VCC
Vref
VCCVref
V1 2.5
V2 2.5
C1 1u R2 0
+
-
+
U1 OPA348
R4 392k
C2 10n
C3
10p
L1 1
T
C4 1T
+
VG1
Vo
Vfb
C5 10p
C2 used for Op amp Stability and High Freq gain control
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12
Differentiator Circuit StabilityT
Vfb
Vo
beta
Vfb
Vo
beta
Ga
in (
dB
)
-200.00
-100.00
0.00
100.00
200.00
Frequency (Hz)
1.00m 100.00 10.00M
Ph
ase
[de
g]
-100.00
0.00
100.00
200.00
beta
Vfb
Vo
Vfb
beta
Vo Rate of Closure = 20dB/Dec
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13
Time Domain Analysis
VCC
VCC
Vref
+
-
+
OPA348
C1 1u R2 0
+
-
+
U1 OPA348
R4 392k
C2 10n
+
ECGp
VECG_block
+
Vpace Pos
ECG+PACE
R1
1M
Dif ferentiator out
Model to replace internal ADS1298 Pace Amplifier
2mV Amplitude100us Period
VCC
Vref V1 2.5
V2 2.5
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14
Time Domain Analysis Cont.
T
Time (s)
180.00m 190.00m 200.00m
Differentiator out
2.44
2.51
ECG+PACE
-1.00m
2.00m
VECG_block
2.50
2.50
Set threshold point for Window Comparator
Pace input pulse
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15
Window Comparator Threshold
VCC
VCC
VCC
VCC
R7
10.2
kR
8 10
kR
6 10
kR
5 8.
06k
V_PACE_OUT
R16
100
k
+
-
+
U3 TLV3401
+
-
+
U2 TLV3401
Differentiator out
To SR Latch
VCC
Vref V1 2.5
V2 2.5
~ 2.77V
~ 2.48V
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16
Pace Circuit Design with Values
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17
Testing
Subhead text here
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Pace Card Design
• Designed to mate with ADS1298ECG-FE board
• Top side populated for PACE OUT 2 and bottom side for PACE OUT 1
• Requires one 5V supply
• SR Latch Outputs routed to ADS1298 GPIOs
• Analysis required for circuit stability
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19
Unstable Design
Differentiator out
Comparator out
SR Latch
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21
Stable Design
Differentiator out
Comparator out
SR Latch
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22
Pace Circuit Design with Values
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23
Pace Circuit Layout