Georgia Institute of...
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Georgia Institute of Technology Department of Electrical and Computer Engineering Exam 3 ECE-4430 Fall 2007 Friday, November 30, 2007 Duration: SOmin Og l(j T First name O(7T/(W\y Last name Og lj T ) (W( ID number This is a close-book, close-note exam. You can use a standard engineering calculator (if needed). You can have three 2-sided sheets of equations and notes. Show your work for partial credits. Remember to write you name on each page. Please consider the following honor pledge. "I have neither given nor received any unauthorized assistance on this exam." Signature
Transcript of Georgia Institute of...
Georgia Institute of TechnologyDepartment of Electrical and Computer Engineering
Exam 3
ECE-4430 Fall 2007
Friday, November 30, 2007 Duration: SOmin
Og l(j TFirst name O ( 7 T / ( W \ y Last name Og lj T ) (W(
ID number
This is a close-book, close-note exam. You can use a standard engineering calculator (ifneeded). You can have three 2-sided sheets of equations and notes.
Show your work for partial credits. Remember to write you name on each page.
Please consider the following honor pledge. "I have neither given nor received anyunauthorized assistance on this exam."
Signature
First name Last name
Problem #1: Multiple Choice Questions
For the questions below, assume the following parameters: (Vdd = 2.5V, UT = 25mV)
MOSFET:BJT:
Ith' = 500nA, K' = 200|aA/V2, VT = 0.5V, and VA = 25V, K = 1, Io' = IfA(3 = 100, VA = 25V, Is = IfA, BJT has a typical asymmetric doping
V2H
4|aA
W/L= 1
1
Device-1
(all devices in saturation)1. Device 1 Transconductance
GND
a.(£} l/25kQc. l/12.5kOd. l/6.25kQe. None of the Above
2. Device 1 Vds(sat)a. 400mV V.b. 300mV
(jx> 200mVd. lOOmVe. None of the Above
3. Device 1 V2
a. 0.81V Vfl ib. 0.74V ' a
c. 0.68Vd. 0.64V
(e^\ None of the Above4. Device 1 Output Resistance
a. 25MQ „ \b. 12.5MQ
(2) 6.25MQd. 1.6M^e. None of the Above
,I
1
W/L= 16
GNDDevice-2
4 .
5. Device 2 Transconductancea. l/50kQb. l/25kQ
l/12.5kDl/6.25kQNone of the Above
6. Device 2 Vds(sat)a. 200mV ^
150mVlOOmV50mVNone of the Above
7. Device 2 V 3
a. 0.60V
c.
e.
b.
d.e.
W
b.0
d.e.
* a
0.54V0.48V0.42VNone of the Above
8. Device 2 Max Gain (magnitude)0 1000 Ab. 500c. 250d. 125e. None of the Above
/£700
First name Last name
v
16JJA
out
V:in
GND
Circuit-1 Circuit-3
b.c.
Output voltage is biased at 1.5V.
9. Circuit 1 Input Resistance ..a. 6.25MQ Rj,, i jjj = -^ •
3.13MQ 3i
6.25kQ3.13kQNone of the Above
10. Circuit 2 Gain (magnitude)a. 1000
500250125None of the Above
11. Circuit 3 Gain (magnitude)a. 1000
c. 250 - <J*' ̂ 'd. 125e. None of the Above
12. Circuit 1 Gaina. -1000b. 1000c. -500
©500 ,e. None of the Above - T
e.
b.
d.e.
13. Circuit 1 Output Resistancea. 6.25MQ vo J ,yb. 3.13MQ Ko"*"- a
12.5kQ6.25kQNone of the Above
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14. Circuit 2 Output Resistancea. 6.25MQ /^. y^ -
3.13MQ1.56MQ0.78MQNone of the Above
c.d.
fe^
b.
d.e.
I
15. Circuit 3 Output Resistancea. 6.25MQ
@3.13MDc. 12.5kQd. 6.25kQe. None of the Above
ft
- 3.
First name Last name
Problem #2: Circuit Analysis
n̂ , i
Answer the following questions regarding the above schematic. Assume all transistors are biasedabove threshold and need to be kept in saturation for the circuit to operate properly.
The CMOS fabrication process parameters are:
unCox=100nA/V2 UpCox = 40 |aA/V2 VTn = 0.7 V VTp = 0.9 V VDS(sat) * 100 mV
Also in terms of size, assume: M9 = Mio = M13 = Mi4, M5 = M? = M)5, and MH = Mi2
Finally the nominal value for VDD = 3 V \!r$_
(a) What is the overall function of this circuit?
OL. ^tf-eS'(MC&' Gen.
.(b) What is the role of branches A-F? (only I sentence each)
A: ef-<
D:E:
. P.
0.7
4$ I)
. (A,)(At)
(c) If the resistors in the schematic are small, what is the minimum VDD for this circuit? Whichbranch is going to limit the VDD? \JpK Ifcf
VEB * °- 7 ̂ Vss l f t^ VTn^ \/D , - i -^(%w ] s Q.7+
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First name Last name
T"' (d) Estimate the input common mode range (ICMR) of stage D.
^ (e) For Vref = 1.26 V at room temperature, find the output swing range of stage D.29 g (f) Find the size of transistors in stage D to achieve the following specifications:
Total power consumption of the entire circuit at no load (RL = oo) less than 300 uW, Avd forstage D > 200, bandwidth of stage D > 150 kHz if d = 1 pF (ignoring all parasitic capacitors),and slew rate > 10 V/u,s.
}£ 3 (g) What would you do to increase the gain of stage D?
3 (h) What would you do to reduce the noise of stage D?
3 (i) What would you do to increase the gain of stage E?
3 (j) What would you do to increase the ICMR of stage D?
3 (k) If stage D was supposed to amplify a small signal near the GND level, how would youchange the topology of stage D?
3 (1) Considering all of the above information, if RL = 100 Q, what is Vout?
choice
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105
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