GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD MIDTERM PRESENTATION STUDENTS: OLEG KORENEV EUGENE...
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Transcript of GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD MIDTERM PRESENTATION STUDENTS: OLEG KORENEV EUGENE...
![Page 1: GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD MIDTERM PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester: spring.](https://reader035.fdocuments.in/reader035/viewer/2022062308/56649db95503460f94aa9c53/html5/thumbnails/1.jpg)
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GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD
MIDTERM PRESENTATION
STUDENTS:
OLEG KORENEV
EUGENE REZNIK
SUPERVISOR:
ROLF HILGENDORF
Semester: spring 2012
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CONTENT
1. Project overview
2. Goals
3. Specifications
4. HW Block Diagram
5. MEMORY on ml605
6. AXI4
7. Design Block Diagram
8. Accomplished so far
9. Workflow
10. Timeline
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PROJECT OVERVIEW
Design and implementation of General Purpose FIFO IP core which allows usage of external memory (DDR3) as FIFO storage on Xilinx FPGA device
• Design and implement generic IP core of FIFO
• Design and implement GUI generator of IP core on PC
• Create sample design with implemented IP core
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OUR GOALS•Gain experience in hardware development
(VHDL environment)•Explore and expertise FPGA work environment
•Create design with configurable
• word size• FIFO depth
•Achieve best performance
•Minimize usage of FPGA resources
•Make our world a better place
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SPECIFICATIONS
Hardware• Xilinx Virtex-6 ML605 FPGA Evaluation Kit
• DDR III memory• Ethernet interface• PCIe interface
• PC with Ethernet interface
Software• ISE Design Suite Logic Edition Version 13.2• Modelsim
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PC
HW BLOCK DIAGRAM
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ML605 BOARD
DDR3 MEMORY
VIRTEX6
USER DESIGN
FIFO CORE
ETHERNET/PCIe
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MEMORY ON ML605 DDR3 memory
• Capacity: 512MB
• Max theoretical bandwidth: 800MT/s*64bit = 6.4GB/sec
Xilinx provides us with DDR3 controller which has AXI Memory Mapped interface
• AXI bus data width up to 1024 bit
• 256 bit for max memory performance, assuming bus works with 200Mhz
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4AXI
Xilinx provides us with AXI4 Memory Mapped bus, which is a standard bus used in modern ARM SoC.
Features
• Separate Address/Control and Data Phases• burst-based transactions with only start address issued• separate read and write data channels
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DESIGN BLOCK DIAGRAM
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DDR3HOST STORAGE LOGIC STORAGE USER STORAGE
MEMORY CONTROLLER
AXI4 BUS (INTERCONNECT)
ARBITER / CONTROLLER
MEMORY TO FIFO
FIFO
Ethernet Interface
LOGIC
User Interface
ETHERNET
HOST
FIFO TO MEMORY
FIFO
MEMORY TO FIFO
FIFO
FIFO TO MEMORY
FIFO
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DESIGN BLOCK DIAGRAM
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DDR3HOST STORAGE LOGIC STORAGE USER STORAGE
MEMORY CONTROLLER
AXI4 BUS
ARBITER / CONTROLLER
MEMORY TO FIFO
FIFO
LOGICEMULATOR
User Interface
FIFO TO MEMORY
FIFO
MEMORY TO FIFO
FIFO
FIFO TO MEMORY
FIFO
User Interface
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ACCOMPLISHED SO FARExternal interface
• Defined basic FIFO interface• Defined word size limitation as 32 up to 1024 bit• Studied features and integrated AXI4 memory mapped bus• Connected DDR3 to AXI bus
Internal architecture
• Implemented memory arbiter with basic functionality, connected to AXI bus as master
• Implemented internal FIFO-To-Memory controller• Implemented internal Memory-To-FIFO controller• Implemented basic emulator of user logic for testing
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PROBLEMSPlacement in FPGA
• We did not succeeded to place synthesized memory controller on chip.
Design
• In which policy should memory arbiter work• Ethernet or PCIe?
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WORKFLOW
Add AXI Interconnect for enabling User Logic to use memory
Improve AXI arbiter for best performance
Studying usage of Ethernet for communication with PC
• Integrating Ethernet controller with AXI stream interface into design
Verification of design in hardware
Implementing GUI for generating FIFO IP core
Testing
Implementing sample design
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TIMELINE2/9 26/8 19/8 12/8 5/8 29/7 exams 24/6 17/6 Duration Task
1 week Integrate AXI interconnect into design
2 weeks Complete AXI arbiter functionality
2 weeksStudying and integrating Ethernet controller into design
3 weeksVerification design in hardware including communication with PC
1 week Part A Presentation