G N POWER HEMT RELIABILITY RESEARCH WITHIN THE … · GaN power HEMT reliability research within...

DEPARTMENT OF

INFORMATION

ENGINEERING

GAN POWER HEMT RELIABILITY RESEARCH WITHIN

THE POWERBASE ECSEL PROJECT : FROM FAILURE

PHYSICS TO INDUSTRIAL EVALUATION

Enrico Zanoni, Matteo Meneghini, Gaudenzio Meneghesso, Carlo De Santi, Alessandro Barbato, Matteo Borga, Maria Ruzzarin

University of Padova, Department of Information Engineering

GaN power HEMT reliability research within the POWERBASE project– [email protected]

OUTLINE• The POWERBASE consortium and research project

• GaN strengths and issues (dynamic-Ron, breakdown effects)

• Failure physics: where we were and what we learned

• drain-to-substrate conduction mechanisms and time-

dependent breakdown

• forward bias p-gate degradation

• hot-electron effects

• Industrial reliability

• dynamic testing approaches

• JEDEC-like accelerated tests

• need for standardization

• Conclusions

OUTLINE


The POWERBASE project consortium

PowerBase, an ECSEL project with 39 partners from 9 European countries

• demonstrate and assess GaN on Si e-mode (normally off) devices

• Pilot production line for fully processed GaN HEMT compatible with high volume CMOS power manufacturing facilities

• Pilot production line for advanced packaging of GaN-based power products

• Prove target achievements in key demonstrators applications in the “smart energy” domain

• Demonstrate reliability and quality as key enabler to gain market acceptance for these new technologies.

Funded by the Electronic Component and Systems

for European Leadership Joint Undertaking (JU-

ECSEL), grant 662133. This JU receives support

from the European Union HORIZON 2020 research

and innovation programme and from Austria,

Belgium, Germany, Italy, The Netherlands, Norway

Slovakia, Spain and United Kingdom


POWERBASE WP6 „Reliability“ partners

University of Bristol, UoB

KompetenzzentrumAutomobil- undIndustrieelektronik, KAI

InteruniversitairMicro-ElectronicaCentrum, IMEC

Institute for Microstructure of Materials and Systems (FhG-IMWS)

Universityof Padova, UNIPD

InfineonTechnologiesAustria, IFAT

Slovak University of Technology in Bratislava, STUBA

NanoDesign,NANO

University of Graz, UNIGRAZ






dependent breakdown







• Conclusions

OUTLINE


K. Chen, O. Häberlen et al. GaN-on-Si Power Technology: Devices and ApplicationsIEEE TED 64, 779 (2017)

Comparison on devices with similar RDSON

QOSS is the output charge, required to load the drain-source capacitance (higher for Si SJ)

QRR is the reverse recovery charge (no body diode in GaN devices)

QG is the total gate charge

Robust VTH

Reliability?

GaN transistors significantly minimize resistive and switching losses, comparedto Si superjunction

GaN on Si power technology


GAN HEMTS VS COOLMOS IN BOOST APPLICATION

• GaN HEMT (cascoded) and SiCoolMOS are compared• At 500 kHz/1.5 kW (HS) overall loss reduced from 42 W

to 26 W (-41 %)• 13.5 W of total loss due to inductor and diode• Performance enhancement mainly due to better

RDSONxQOSS

(GaN: 5 mWµC, Si SJ: 23.5 mWµC)[QOSS=charge for charging DS capacitance]

Hard switched, 500 kHz, 230:400 V, CCM

Valley switching DCM, 100 kHz, 230:400 V

K. Chen, O. Häberlen et al. GaN-on-Si Power Technology: Devices and ApplicationsIEEE TED 64, 779 (2017)



BATTLEFIELDS FOR GAN

https://www.infineon.com/dgdl/Infineon-Presentation_GaN_GalliumNitride_APEC2016-AP-v01_00-EN.pdf?fileId=5546d46253a864fe0153d0a8f85132c5

GaN is expected to target the high frequency (>100 kHz), mid-powermarket (<10 kW)

Competition with SiC will come from next generation vertical devices



GAN HEMT: TYPICAL STRUCTURE

http://www.i-micronews.com/upload/Rapports/Yole_III-V_Epitaxy_April_2012_Report_Sample.pdf

Substrate (typically p-type, up to 200 mm)

AlN nucleation layer

Strain relief layer(s)

Back-barrier/C-doped GaN

AlGaN/GaN heterojunction

GaN-on-Si HEMT : critical areas

deep levels may be introduced :

due to GaN defectivity (lattice-mismatch with Si)

due to compensation or unwanted impurities, e.g. C

deep levels induce carrier trapping effects during switching: dynamic Ron


DYNAMIC RON: A LIMITATION?

VDD

(50 V)

VGS

(-8 V)

99 µs

1 µs

OFF

ON

OFF

ON

OFF

ON

CurrentCollapse

Measured by pulsing from restconditions (VG_QB=0, VD_QB=0)

Measured by pulsing from trappingconditions (VG_QB=-8, VD_QB=50)

Currentcollapse

Dynamic-Ron recoverable increase in on-resistance induced by charge trapping in off-state On-resistance is higher when measured after a switching event (OFFON)

May significantly limit the dynamic performance of the devices, the maximum switching frequency, and increase switching losses

Dynamic on-resistance effects


HT1: EC - ET = 0.557 eV, s = 2.02E-18 cm2, Si-Ga vacancy or N

vacancy

HT2: EC - ET = 0.878 eV, s = 1.63e-15 cm2, GaN dislocation

ET1: EC - ET = 0.377 eV, s = 1.75e-14 cm2 AlGaN/GaN interface

ET2: EC - ET = 0.230 eV, s = 6.73E-17 cm2, N vacancy

Advancements in defect

analysis: Identification of

the deep levels

responsible for gate

leakage based on C-

DLTS

High gate leakage Low gate leakage

analysis of deep levels and dynamic Ron data

demonstrate epi and device improvement over

POWERBASE timeline

Objective 6.2:

Parasitic effects characterization and modeling

Slovak University of Technology in Bratislava, STUBA

NanoDesign,NANO


Recessed and regrowth gate p-GaN Technology

Fully recessed 1st barrier

Regrowth of 2nd barrier and p-GaN layer

Excellent Vth stability

p-GaN ring at drain for dynamic RDSON optimization

Device concept

Hole injection at drain side

Key features

Infineon, Proceedings of ISPSD 2015 (Hongkong) and ISPSD 2016 (Prague)20

By inserting a p-GaN gate layer enhancement-mode operation is achieved


WP6 reliability methodology

GaN-related testingtools and methods

Identification of failure modes and

mechanisms

Derivation of acceleration laws

statistically relevantindustrial reliability

testing

Trusted extrapolationof lifetime data






dependent breakdown







• Conclusions

OUTLINE


Main failure mechanisms are related with chargetrapping and time-dependent breakdown

Knowledge on failure modes and mechanisms of p-gate enhancement-

mode power GaN HEMT and their acceleration laws

hot-electron trapping

(hard switching)

time dependent

breakdown of p-gate

stack (positive bias)

time dependent

gate-drain breakdown

drain-substrate

leakage and time

dependent

breakdown

positive and negative threshold

voltage instability

at the beginning of

POWERBASE,

knowledge on failure

mechanisms referred to

GaN HEMT for GaN-on-

SiC microwave

applications only


GaN reliability beyond initial state of the art

Knowledge on failure modes and mechanisms of p-gate enhancement-

mode power GaN HEMT and on the related acceleration laws

• conduction mechanisms of drain-to-substrate leakage

• impact of substrate and buffer design

on the performance and breakdown of

GaN-on-Si power HEMT

• - substrate orientation

• - p doping level

• time-dependent breakdown of drain-to-substrate vertical structure

• degradation mechanisms of p-gate adopting Schottky and ohmic

contact to p


VD=800 V


Influence of p-Si substrate doping on drain-substrate breakdown and reliability

When high voltage is applied to the drain with

respect to p-Si substrate a trade-off is established

between leakage, breakdown voltage and trapping

effects: lower p-doping, higher BV, higher trapping

M. Borga et al.,

IEEE Trans.

El. Dev. 65 (7)

2765 (2018)

M. Borga et al.

IEEE Trans.

El. Dev. 64 (9)

3616 (2017)

L. Sayadi, G.

Curatola et al.

IEEE Trans.

El. Dev. 65 (1)

51 (2018)


D. Marcon et al. IEEE Trans. El. Dev. 60(10) 3132, 2013

Weibull distribution and lifetime extrapolation


LIMITS TO OFF-STATE RELIABILITY:2 – VERTICAL TBD (INTRINSIC)

UNIPD & imec, M. Borga et al., IEEE Trans. El. Dev. 64 (9) 3616 (2017)

Device structure

Here dielectrics are not involved, GaN itself is showing TBD

Constant voltagestress

2-terminal stress experiment (drain-

to-substrate) induces a time-

dependent failure

Semi-insulating GaN behaving as a

dielectric?

VD=800 V

Time-dependent breakdown in the drain-to-

substrate vertical stack


Time-dependent breakdown of p-GaN gate junction with Schottky contact

Highlight: full description of the degradation of p-GaN gate stack of normally-off HEMTs

105

106

107

108

109

1010

10-1

100

101

102

103

104

105

106

y = y0 + Ae

Bx

VG = 9.5 V

VG = 9.0 V

VG = 8.5 V

Exp. Fitting

Tim

e T

o F

ailu

re (

s)

1/IG (A/mm)

-1

T = 25 C

Correlation between lifetime and gate leakage for different gate voltages

Physical origin of degradation was understood1. during TLP/ESD tests breakdown of the metal/p-GaN Schottky junction

2. during a constant voltage experiment time-dependent degradation due to the build-up of positive charges in the AlGaN layer)

5 6 7 8 9 1010

0

101

102

103

104

105

106

107

108

109

Exponential law

Fail. criterion:

F = 1%

T = 150 °C

10 years

Life

tim

e (

s)

Gate Voltage (V)

VG_MAX

= 6.46 V

100 101 102 103 104

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4 T = 100 °C

T = 125 °C

T = 150 °C

mean

VT

H (

mV

)

Stress Time (s)

VG_S = 8 V

Al = 25 %

I. Rossetto et al. (UNIPD + imec) Microelectr. Reliability 76-77 (2017) 298-303


Other option : ohmic contact on p-GaN gate.

Mechanism of forward gate current degradation

• Below VGstress = 8 V: no degradation

• 8 V < VGstress < 11.5 V: negative shift

of VTH due to hole trapping, leakage

decrease

• VGstress > 12 V hole detrapping,

leakage increase

M. Ruzzarin et al. (UNIPD+IFAT), IEEE

Trans. El. Dev. 65 (7), 2778 (2018)


HARD SWITCHING AND SEMI-ON STATE

Role of hot electronsconfirmed by:

• Intensity of EL signalwith increasingoverlapping

• Reduced dynamic Ronat high temperature in hard switchingconditions

Soft switching

Hard switching

I. Rossetto et al., IEEE-TED 64 (9) 3734 (2017)

VGATE

IDRAIN

t

t

VDRAINt

(a) Hard switching conceptBoost converter

VGATE

IDRAIN

t

t

VDRAINt

(b) Soft switching conceptDouble Pulse

VDSON

VDSOFF

VDSON

VDSOFF

VDSTEST≈ ≈ ≈ ≈

DGD

measures

the time

overlap

between

drain voltage

and current:

more negative

DGD, more

overlap, more

hot-electrons

During hard

switching, hot-

electrons

enhance

trapping

effects and

dynamic Ron

Hot-electron effects during switching


On-wafer application-related device testing

Novel system to measure the RDSON on-wafer, in real application conditions, in a DC-DC boost power converter

In this way, the devices can be tested and stressed in final application regime, without need of package Faster feedback to WP3!!

Dynamic-Ron can be

measured directly in a boost

converter (on-wafer)

Comparison between hard-

switching and soft-switching,

evaluation of hot-electron

effects

Converter Board

Microscope

Manipulators

On-wafer GaN-HEMT

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

0E+0 1E-6 2E-6 3E-6 4E-6

Time [s]

RD

SON

no

rmal

ized

[a.

u.]

I DS

[A],

VD

S[V

]

VOUT = 400VVDS

RON

IDS

turn ON

0

2

4

6

8

10

12

14

16

18

20

0 100 200 300 400 500 600

RO

N[O

hm

]

VDS_OFF [V]

WF1

WF2

Link with WP3

Boost

PIV

RO

N(a

u)


HARD SWITCHING AND SEMI-ON STATE: IMPACT ON DYNAMIC RON

Gate driver

Inductor L Diode D

InputCapacitorCIN

OutputCapacitorCOUT

G

S

D

VDS

IDS

VDS

probe

OscilloscopeIDS

probe

a) b)

0

10

20

30

40

50

0

100

200

300

400

500

0 5 10 15 20 25 30

I L[m

A]

VD

S[V

]Time [ms]

1 V

400VWF1

f=100 kHz, VIN = 72.5 V, VOUT 400 V, load resistor RLOAD = 150 kW

On-wafer boost converter Circuit schematic

Clamp circuit to get fast scope reading

Typical inductor currents

UNIPD & Infineon, Barbato et al, IEEE-TPEL (under review)

Converter Board

Microscope

Manipulators

On-wafer GaN-HEMT

Converter Board

Microscope

Manipulators

On-wafer GaN-HEMT

Realistic evaluation of switching-related

degradation: on-wafer in-circuit testing


HARD SWITCHING AND SEMI-ON STATE: IMPACT ON DYNAMIC RON

0.00

0.01

0.02

0.03

0.04

0.05

-50.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0

I DS

[A]

VDS [V]

TURN-ON Locus

OFFON

Turn-on waveforms Turn-on locus

UNIPD & Infineon, A. Barbato et al, IEEE-Tr. Ind. El. (submitted)

Turn-on locus is critical for reliability for some 10 ns device is subject to both high current and high drain bias

Possible consequences:• Hot electron trapping• Enhanced self-heating• Catastrophic failure

What isimportant is

the Switching-SOA*The switching transistion shown is slowed down very much (due

to WL setup) compared to a real application (few 100ns vs. few10ns)

On-wafer boost converter testing


Double Pulse Measurement

VGS

VDS

VDS_clamped

iL

IDS = 20A

VDS =600V

VDS = 600V

~ 0% dyn RDSon at ZCS

~ 40% dyn RDSon

@20A hard switching

iL

OFF 1st turn ON OFF 2nd turn ONZero Current Turn-On Hard Turn-On 20A

Δt=1µs

Early development

stage sample

Current devices show no dynamic Ron under 20A hard switching at 600 V


Objective 6.1 : Innovation in reliability methodology

28

Methodology: innovative failure analysis techniques for GaN

Cathodoluminescence analysis of AlGaN/GaN epi

on Si.

Atomic-level resolution TEM image of

AlN spacer between AlGaN and GaN

Identification of short-

circuit by lock-in

thermography, cross-

sectioning and TEM






dependent breakdown







• Conclusions

OUTLINE


Qualification/evaluation of industrial-leveldevices

Reliability evaluation of industrial-level p-gate

600 V enhancement-mode devices

• Deep-levels and dynamic Ron evaluation using DLTS and double-pulse drain and backgating measurement systems

• Evaluation of on-wafer DC stability : step-stress tests, constantvoltage tests at 700V, 800 V

• Stability under multipulse test (unclamped inductive switching)

• High temperature forward gate bias overstress and study of p-gatefailure modes and mechanisms

• High temperature testing in short-circuit mode

• Extended JEDEC-like long-term accelerated testplan


Extended end-of-life accelerated testing

33

500 V / 15 kW power supplies & active loads Climate chamber with 24 stress test modules


Long-term reliability package test

Long-term reliability test-plan has been implemented by extending the JEDEC

guidelines for electronic devices


Pre-qualification summary: 600V & 70mW,

Standard Stress Tests based on JESD47

StressRequired

Duration

Sample

SizeStatus/Results

Risk

Rate

High Temperature Reverse Bias

(HTRB)

JESD22 A-108 (Q101)

1000 hr 1 x 28pcs

• 168hr: 0 / 28

• 500hr: 0 / 28

• 1000hr: 0 / 28

*. Minor Idss current drift but no noticeable change in

all the other parametersPass

Positive High Temperature Gate

Stress (P-HTGF)

JESD22 A-108 (Q101)

1000 hr 1 x 30

• 168hr: 0 / 30

• 500hr: 0 / 30

• 1000hr: 0 / 30

• Ig & Id leakage current drift but within the

specification limitPass

Negative High Temperature Gate

Stress (N-HTGS)

JESD22 A-108 (Q101)

1000 hr 1 x 30

• 168hr: 0 / 30

• 500hr: 0 / 30

• 1000hr: 0 /30

• No noticeable parametric drift

Pass

High Humidity High Temperature

Reverse Bias (H3TRB)

JESD22 A-101

1000 hr 1 x 30

• 168hr: 0 / 30

• 500hr: 0 / 30

• 1000hr:0 / 30

Pass

High Temperature Storage Life

(HTSL) JESD22 A-1031000 hr 1 x 40

• 168hr: 0 / 40

• 500hr: 0 / 40

• 1000hr: 0 / 40

Pass

Intermittent Operational Life Test

(IOL)

MIL-STD 750/Meth.1037

15,000x 1 x 30• 7500x: 0 / 30

• 15,000hx: 0 /30Pass

ESD-HBM

JS-001Target: 2kV

3 pcs per

voltage

PASS

(Target: 2 kV, Class 2)

• No failure up to 2kV

• Fail at 3kVPass

ESD-CDM

JS-002Target: 500V 3 x 3

Pass

(Target: 500 V, Class C3)• No failure up to 1250V Pass

Preliminary data of “Temperature Cycle (TC, 55 °C / +125 °C)” showed no failures up to 2000 Cycles and regular TC lots will run for the qualification.

Highly Accelerated Stress Test (HAST, 130 °C / 85 % r.h. / 480 V, JESD22 A-110) is under evaluation and already passed 96hr without failures (June 2018).


Parametric drift:

PowerBase 600V GaN NormOff HEMT

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

0hr 168hr 500hr 100hr

Id (

uA

) at

Vd

= 6

00

V

Stress Tme (Hr)

IDSS at Vd = +600VPost-HTRB

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

0hr 168hr 500hr 1000hrIGSS

(u

A)

at V

g =

+1.5

V

Stress Tme (Hr)

IGSS at Vg = +1.5VPost-HTRB

0.9

1

1.1

1.2

1.3

1.4

1.5

0hr 168hr 500hr 1000hr

Vth

(V

) at

Id =

2.6

mA

Stress Tme (Hr)

Vth at Id=2.6mAPost- HTRB

40

50

60

70

80

0hr 168hr 500hr 1000hrRD

Son

(mW

) at

Id =

8A

Stress Tme (Hr)

RDSon(mW) at Id=8APost-HTRB

✓ No parametric drift except for a small increase in IDSS


Application-related reliability test

How to test GaN HEMT devices

for reliability & robustness under

application conditions?

❖ Standard JEDEC qualification –

PTC, HTOL, HTRB, IOL …

(dynamic testing not considered)

❖ Lab characterization – SOA,

double pulse, UIS …

❖ Customer life test of final

product @ system level

❖ Carry out device level stress

testing in an application

related test configuration

Control module

PWM Guard Switch

Power Supply

Active Load GaN

GaN

External devices

Application board GaN test board

I IN

I OUT

I SENS V SENS

Blocking Diodes

HostPC

Ethernet


Lifetime testing

Projection at 480 V

𝐿 𝑡 = 𝐴 ∗ 𝑒−𝛾𝑉 ∗ 𝑒𝐸𝑎

𝑘𝑇

Life Time Model:

Lifetime requirement:< 1 fit for 15 years at

480V, 125 °C

➢ Very tight distribution (high ß good process control)

➢ The conservative model predicts a lifetime of ~55 years at 100

ppm, 480 V and 125 °C

➢ > 3X safety margin from Infineon’s criteria

JEDEC testing 3 x 77

parts, 480V, 1000h


Increased buffer reliabilityHigh reliability, stability on 200mm (650V epi on p+)

39

63% failure63% failure, area scaling

■ scaling to 0.9mm2

power transistor.

0.01% failure, area scaling

■ 63% failure to 0.01% failure.

10 years820V

Buffer induced Ron,dyn Buffer reliability (TDDB)

Large step in overall reliability of 650V buffer architecture on p+

▪ Buffer induced Ron,dyn is below 5% at 650V

▪ Maximum applicable drain voltage is 820V (large margin over spec)

▪ Very high β, indicating good uniformity


GaN Standardization: JEDEC JC-70.1

The power electronics industry recently reached an important milestone:

The Joint Electron Device Engineering Council (JEDEC) announcedthe formation of a new committee in Sep-2017:JC-70 Wide Bandgap Power Electronic Conversion Semiconductors

JC-70.1 subcommittee is dedicated to GaN

This committee’s charter is to standardize reliability and qualification procedures, data sheet elements and parameters, and test and characterization methods

Having a common standardwill enable the power industryto compare and contrastdifferent GaN deviceson a common base.

40


Need for GaN-specific standard testing

methodology : JEDEC committee JC-70.1

today at 15:55

Status of GaN device qualification standards effort by new JEDEC

committee JC-70.1

Tim McDonald, Senior Consulting Advisor , CoolGaNTM Technology

Development, Infineon Technologies


CONCLUSIONS: POWERBASE impact

• Significant improvement of the knowledge on failure modes and

mechanisms of conventional- and enhanced-substrate power GaN HEMTs

• Development and validation of new testing and failure analysis techniques

specifically tailored to GaN technology

• Accurate modeling tools and methods for device thermal evaluation and

control of junction temperature (not shown)

• Highly-accelerated stress testing of GaN power HEMTs now possible for

the first time in large scale under closely application-related conditions

• Before POWERBASE, no End of Life data for GaN power HEMTS was

available under real application conditions of GaN power HEMTs. These

data are now linked to specific failure modes and mechanisms

G N POWER HEMT RELIABILITY RESEARCH WITHIN THE … · GaN power HEMT reliability research within...

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