Fundamental Principles of Optical Lithography

Fundamental Principles of Optical

Lithography:The Science of

Microfabrication

CHRIS MACK

www.lithoguru.com

Fundamental Principles of Optical

Lithography:The Science of

Microfabrication

CHRIS MACK

www.lithoguru.com

Copyright © 2007 John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England

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Contents

Preface xv

1. Introduction to Semiconductor Lithography 1 1.1 Basics of IC Fabrication 2 1.1.1 Patterning 2 1.1.2 Etching 3 1.1.3 Ion Implantation 5 1.1.4 Process Integration 6 1.2 Moore’s Law and the Semiconductor Industry 7 1.3 Lithography Processing 12 1.3.1 Substrate Preparation 14 1.3.2 Photoresist Coating 15 1.3.3 Post-Apply Bake 18 1.3.4 Alignment and Exposure 19 1.3.5 Post-exposure Bake 23 1.3.6 Development 24 1.3.7 Postbake 25 1.3.8 Measure and Inspect 25 1.3.9 Pattern Transfer 25 1.3.10 Strip 26 Problems 26

2. Aerial Image Formation – The Basics 29 2.1 Mathematical Description of Light 29 2.1.1 Maxwell’s Equations and the Wave Equation 30 2.1.2 General Harmonic Fields and the Plane Wave in

a Nonabsorbing Medium 32 2.1.3 Phasors and Wave Propagation in an Absorbing

Medium 33 2.1.4 Intensity and the Poynting Vector 36 2.1.5 Intensity and Absorbed Electromagnetic Energy 37

viii Contents

2.2 Basic Imaging Theory 38 2.2.1 Diffraction 39 2.2.2 Fourier Transform Pairs 43 2.2.3 Imaging Lens 45 2.2.4 Forming an Image 47 2.2.5 Imaging Example: Dense Array of Lines and Spaces 48 2.2.6 Imaging Example: Isolated Space 50 2.2.7 The Point Spread Function 51 2.2.8 Reduction Imaging 53 2.3 Partial Coherence 56 2.3.1 Oblique Illumination 57 2.3.2 Partially Coherent Illumination 58 2.3.3 Hopkins Approach to Partial Coherence 62 2.3.4 Sum of Coherent Sources Approach 63 2.3.5 Off-Axis Illumination 65 2.3.6 Imaging Example: Dense Array of Lines and Spaces

Under Annular Illumination 66 2.3.7 Köhler Illumination 66 2.3.8 Incoherent Illumination 69 2.4 Some Imaging Examples 70 Problems 71

3. Aerial Image Formation – The Details 75 3.1 Aberrations 75 3.1.1 The Causes of Aberrations 75 3.1.2 Describing Aberrations: the Zernike Polynomial 78 3.1.3 Aberration Example – Tilt 81 3.1.4 Aberration Example – Defocus, Spherical

and Astigmatism 83 3.1.5 Aberration Example – Coma 84 3.1.6 Chromatic Aberrations 85 3.1.7 Strehl Ratio 90 3.2 Pupil Filters and Lens Apodization 90 3.3 Flare 91 3.3.1 Measuring Flare 92 3.3.2 Modeling Flare 94 3.4 Defocus 95 3.4.1 Defocus as an Aberration 95 3.4.2 Defocus Example: Dense Lines and Spaces and

Three-Beam Imaging 98 3.4.3 Defocus Example: Dense Lines and Spaces and

Two-Beam Imaging 100 3.4.4 Image Isofocal Point 102 3.4.5 Focus Averaging 103 3.4.6 Reticle Defocus 104 3.4.7 Rayleigh Depth of Focus 105

Contents ix

3.5 Imaging with Scanners Versus Steppers 106 3.6 Vector Nature of Light 108 3.6.1 Describing Polarization 111 3.6.2 Polarization Example: TE Versus TM Image of

Lines and Spaces 113 3.6.3 Polarization Example: The Vector PSF 114 3.6.4 Polarization Aberrations and the Jones Pupil 114 3.7 Immersion Lithography 117 3.7.1 The Optical Invariant and Hyper-NA Lithography 118 3.7.2 Immersion Lithography and the Depth of Focus 120 3.8 Image Quality 121 3.8.1 Image CD 121 3.8.2 Image Placement Error (Distortion) 123 3.8.3 Normalized Image Log-Slope (NILS) 123 3.8.4 Focus Dependence of Image Quality 125 Problems 126

4. Imaging in Resist: Standing Waves and Swing Curves 129 4.1 Standing Waves 130 4.1.1 The Nature of Standing Waves 130 4.1.2 Standing Waves for Normally Incident Light in

a Single Film 131 4.1.3 Standing Waves in a Multiple-Layer Film Stack 135 4.1.4 Oblique Incidence and the Vector Nature

of Light 137 4.1.5 Broadband Illumination 141 4.2 Swing Curves 144 4.2.1 Refl ectivity Swing Curve 144 4.2.2 Dose-to-Clear and CD Swing Curves 148 4.2.3 Swing Curves for Partially Coherent Illumination 149 4.2.4 Swing Ratio 151 4.2.5 Effective Absorption 154 4.3 Bottom Antirefl ection Coatings 156 4.3.1 BARC on an Absorbing Substrate 157 4.3.2 BARCs at High Numerical Apertures 160 4.3.3 BARC on a Transparent Substrate 164 4.3.4 BARC Performance 165 4.4 Top Antirefl ection Coatings 167 4.5 Contrast Enhancement Layer 170 4.6 Impact of the Phase of the Substrate Refl ectance 170 4.7 Imaging in Resist 173 4.7.1 Image in Resist Contrast 173 4.7.2 Calculating the Image in Resist 177 4.7.3 Resist-Induced Spherical Aberrations 179 4.7.4 Standing Wave Amplitude Ratio 181

x Contents

4.8 Defi ning Intensity 183 4.8.1 Intensity at Oblique Incidence 183 4.8.2 Refraction into an Absorbing Material 184 4.8.3 Intensity and Absorbed Energy 187 Problems 188

5. Conventional Resists: Exposure and Bake Chemistry 191 5.1 Exposure 191 5.1.1 Absorption 191 5.1.2 Exposure Kinetics 194 5.2 Post-Apply Bake 199 5.2.1 Sensitizer Decomposition 200 5.2.2 Solvent Diffusion and Evaporation 205 5.2.3 Solvent Effects in Lithography 209 5.3 Post-exposure Bake Diffusion 210 5.4 Detailed Bake Temperature Behavior 214 5.5 Measuring the ABC Parameters 217 Problems 219

6. Chemically Amplifi ed Resists: Exposure and Bake Chemistry 223 6.1 Exposure Reaction 223 6.2 Chemical Amplifi cation 224 6.2.1 Amplifi cation Reaction 225 6.2.2 Diffusion 227 6.2.3 Acid Loss 230 6.2.4 Base Quencher 232 6.2.5 Reaction–Diffusion Systems 233 6.3 Measuring Chemically Amplifi ed Resist Parameters 235 6.4 Stochastic Modeling of Resist Chemistry 237 6.4.1 Photon Shot Noise 237 6.4.2 Chemical Concentration 239 6.4.3 Some Mathematics of Binary Random Variables 241 6.4.4 Photon Absorption and Exposure 242 6.4.5 Acid Diffusion, Conventional Resist 246 6.4.6 Acid-Catalyzed Reaction–Diffusion 247 6.4.7 Reaction–Diffusion and Polymer Deblocking 251 6.4.8 Acid–Base Quenching 253 Problems 254

7. Photoresist Development 257 7.1 Kinetics of Development 257 7.1.1 A Simple Kinetic Development Model 258 7.1.2 Other Development Models 261 7.1.3 Molecular Weight Distributions and the Critical

Ionization Model 264 7.1.4 Surface Inhibition 265

Contents xi

7.1.5 Extension to Negative Resists 267 7.1.6 Developer Temperature 267 7.1.7 Developer Normality 268 7.2 The Development Contrast 270 7.2.1 Defi ning Photoresist Contrast 270 7.2.2 Comparing Defi nitions of Contrast 274 7.2.3 The Practical Contrast 276 7.2.4 Relationship between g and rmax/rmin 277 7.3 The Development Path 278 7.3.1 The Euler–Lagrange Equation 279 7.3.2 The Case of No z-Dependence 280 7.3.3 The Case of a Separable Development Rate Function 282 7.3.4 Resist Sidewall Angle 283 7.3.5 The Case of Constant Development Gradients 284 7.3.6 Segmented Development and the Lumped

Parameter Model (LPM) 286 7.3.7 LPM Example – Gaussian Image 287 7.4 Measuring Development Rates 292 Problems 293

8. Lithographic Control in Semiconductor Manufacturing 297 8.1 Defi ning Lithographic Quality 297 8.2 Critical Dimension Control 299 8.2.1 Impact of CD Control 299 8.2.2 Improving CD Control 303 8.2.3 Sources of Focus and Dose Errors 305 8.2.4 Defi ning Critical Dimension 307 8.3 How to Characterize Critical Dimension Variations 309 8.3.1 Spatial Variations 309 8.3.2 Temporal Variations and Random Variations 311 8.3.3 Characterizing and Separating Sources of CD Variations 312 8.4 Overlay Control 314 8.4.1 Measuring and Expressing Overlay 315 8.4.2 Analysis and Modeling of Overlay Data 317 8.4.3 Improving Overlay Data Analysis 320 8.4.4 Using Overlay Data 323 8.4.5 Overlay Versus Pattern Placement Error 326 8.5 The Process Window 326 8.5.1 The Focus–Exposure Matrix 326 8.5.2 Defi ning the Process Window and DOF 332 8.5.3 The Isofocal Point 336 8.5.4 Overlapping Process Windows 338 8.5.5 Dose and Focus Control 339 8.6 H–V Bias 343 8.6.1 Astigmatism and H–V Bias 343 8.6.2 Source Shape Asymmetry 345

xii Contents

8.7 Mask Error Enhancement Factor (MEEF) 348 8.7.1 Linearity 348 8.7.2 Defi ning MEEF 349 8.7.3 Aerial Image MEEF 350 8.7.4 Contact Hole MEEF 352 8.7.5 Mask Errors as Effective Dose Errors 353 8.7.6 Resist Impact on MEEF 355 8.8 Line-End Shortening 356 8.8.1 Measuring LES 357 8.8.2 Characterizing LES Process Effects 359 8.9 Critical Shape and Edge Placement Errors 361 8.10 Pattern Collapse 362 Problems 366

9. Gradient-Based Lithographic Optimization: Using the Normalized Image Log-Slope 369

9.1 Lithography as Information Transfer 369 9.2 Aerial Image 370 9.3 Image in Resist 377 9.4 Exposure 378 9.5 Post-exposure Bake 381 9.5.1 Diffusion in Conventional Resists 381 9.5.2 Chemically Amplifi ed Resists – Reaction Only 383 9.5.3 Chemically Amplifi ed Resists – Reaction–Diffusion 384 9.5.4 Chemically Amplifi ed Resists – Reaction–Diffusion

with Quencher 391 9.6 Develop 393 9.6.1 Conventional Resist 397 9.6.2 Chemically Amplifi ed Resist 399 9.7 Resist Profi le Formation 400 9.7.1 The Case of a Separable Development

Rate Function 400 9.7.2 Lumped Parameter Model 401 9.8 Line Edge Roughness 404 9.9 Summary 406 Problems 408

10. Resolution Enhancement Technologies 411 10.1 Resolution 412 10.1.1 Defi ning Resolution 413 10.1.2 Pitch Resolution 416 10.1.3 Natural Resolutions 418 10.1.4 Improving Resolution 418 10.2 Optical Proximity Correction (OPC) 419 10.2.1 Proximity Effects 419 10.2.2 Proximity Correction – Rule Based 422

Contents xiii

10.2.3 Proximity Correction – Model Based 425 10.2.4 Subresolution Assist Features (SRAFs) 427 10.3 Off-Axis Illumination (OAI) 429 10.4 Phase-Shifting Masks (PSM) 434 10.4.1 Alternating PSM 435 10.4.2 Phase Confl icts 438 10.4.3 Phase and Intensity Imbalance 439 10.4.4 Attenuated PSM 441 10.4.5 Impact of Phase Errors 445 10.5 Natural Resolutions 450 10.5.1 Contact Holes and the Point Spread Function 450 10.5.2 The Coherent Line Spread Function (LSF) 452 10.5.3 The Isolated Phase Edge 453 Problems 454

Appendix A. Glossary of Microlithographic Terms 457

Appendix B. Curl, Divergence, Gradient, Laplacian 491

Appendix C. The Dirac Delta Function 495

Index 501

Preface

There was a time when I was sure this book would never be fi nished. Believe it or not, I began working on it about 18 years ago, and for a long time it seemed that each year left me farther from completion (a consequence of working in a rapidly changing fi eld). Several things conspired to fi nally make this book a reality. Ron Hershel, the closest person to a mentor I have known, gave me sage advice on writing a book: Don’t try to write it all at once – instead, write and publish pieces of your book as journal articles over time, then collect them up when you have written enough. That advice has served me well, especially since I have been writing a quarterly column for Microlithography World since 1992. That approach helped me fi nish my fi rst book, Inside PROLITH: A Comprehensive Guide to Optical Lithography Simulation, in 1997.

While I enjoyed fi nishing and publishing Inside PROLITH, my ambition was to write a more comprehensive university textbook on the topic of semiconductor lithography. I have been teaching a graduate level class on optical lithography at the University of Texas at Austin since 1991, using handouts in place of a real book. Each year I strove to add more material to make those notes more complete. But I ran into the same problem as before – new material in this quickly changing fi eld was needed at a faster rate than I was writing.

I solved this problem in two ways. First, I began to focus solely on fundamental prin-ciples needed to understand the science of lithography. While lithography practice changes quickly, the fundamental principles underlying that practice do not. The result, though, is that this book has very little ‘practical’ advice, that is, descriptions of best practices in the industry. While such practical descriptions can be very useful, they also become dated very quickly. I hope that by focusing on fundamentals this book might be useful to the reader many years after it is purchased.

Secondly, I quit my job and worked on this book full-time (well, almost full time) for the fi nal year before its completion. I hope that this admission doesn’t scare off the earnest would-be author, but the reality was, for me at least, that dedicated effort was required

xvi Preface

to complete the project. Much of the material contained herein is, of course, a tutorial review of the published literature on lithography and related sciences. But a signifi cant portion is new work, having never before been published. Thus, I hope that this book will contribute to the body of lithography literature mostly as a convenient repository of a useful portion of the collective knowledge in this fi eld, but also as a repository for the information contained in various notebooks, fi les and scraps of paper scattered around my cluttered offi ce.

While the length of the fi nal book surprised even me, still, there are many fascinating and important topics in lithography that have been excluded for lack of space. In particu-lar, rigorous treatment of electromagnetic scattering through the topography of a photo-mask is extremely important in lithography today, but goes without even a mention in the book. With respect to photoresist, etch resistance, spin coat rheology, adhesion, shelf life and quality control, resist formulations and defects all receive short shrift, and nothing is mentioned of top surface imaging or the various multilayer and nontraditional resist schemes. For those interested in imaging tools, the topics of geometrical optics, lens design, aberration measurement and tool component functions such as alignment, auto-focus, stage motion, etc., are essentially ignored. The world of mask making is left to other books, as are the topics of chip design and design for manufacturability, despite their obvious impact on the fi eld of lithography. Metrology, especially critical dimension metrology, is extremely important to lithography, since data from these measurements drive much of our knowledge of how lithography behaves. However, even though metrol-ogy deserves an entire chapter, I have left it out almost completely. Surprisingly to some, I have chosen not to cover an aspect of lithography very dear to me – lithography simula-tion. While the use of simulation is illustrated throughout the book, and of course a sci-entifi c description of lithography must necessarily serve as the foundation of a lithographic simulator, I have avoided the topic of the numerical solutions to the equations presented in the book as well as to the topics of model speed, accuracy and calibration. Finally, there is no effort to describe research into next generation lithography technologies, and no description of the many lithographic approaches that don’t use projection optical imaging. Despite these glaring omissions, I still might be criticized for making the book too long, with too many topics, for use as a university text. I can only say that I have successfully covered most of the information contained in the book in a one semester course, with only the usual amount of grumbling from the affected students.

I am indebted to many, many people for their help with this book. In the 24 years that I have worked in the fi eld of lithography I have been taught by many, many people. I couldn’t possible begin to count, let alone recount, the published works that have so greatly contributed to my understanding in this fi eld. In fact, I will here issue a blanket apology to all those whose important works I have relied on but did not include in the references in the book. The lack of proper references is, I think, the biggest failure of this work, though I hope to be forgiven based on its format as a university textbook. I would also like to thank the students at the University of Texas at Austin and at Notre Dame whom I punished with early drafts of this book. Their feedback and experiences, good and bad, helped me to greatly improve the material and make it more suitable for the classroom.

There are many people who helped by reviewing chapters and providing feedback: Gary Bernstein, John Biafore, Robert Bunch, Jeff Byers, John Kulp and John Petersen

Preface xvii

among others that I am sure I am forgetting. I would especially like to thank Warren Grobman who carefully read every chapter in the book and provided invaluable feedback, and Trey Graves who bravely defi ed Finman’s Law of Mathematics and re-derived many of the equations in Chapters 2 and 3. I am indebted to Chris Sallee and KLA-Tencor for allowing me the use of the lithography simulator PROLITH, which I employed exten-sively in generating many of the fi gures found throughout the book.

As a fi nal note, I encourage the interested reader to visit the web page for this book: www.lithoguru.com/textbook. There I will post errata and other information that might be useful to the reader, and information that might prove valuable to the professor inter-ested in using this text as the basis for a university course.

Chris A. MackAustin, Texas

June, 2007

Fundamental Principles of Optical Lithography: The Science of Microfabrication, Chris Mack.© 2007 John Wiley & Sons, Ltd.

1Introduction to Semiconductor

Lithography

The fabrication of an integrated circuit (IC) involves a great variety of physical and chemical processes performed on a semiconductor (e.g. silicon) substrate. In general, the various processes used to make an IC fall into three categories: fi lm deposition, patterning and semiconductor doping. Films of both conductors (such as polysilicon, aluminum, tungsten and copper) and insulators (various forms of silicon dioxide, silicon nitride and others) are used to connect and isolate transistors and their components. Selective doping of various regions of silicon allows the conductivity of the silicon to be changed with the application of voltage. By creating structures of these various components, millions (or even billions) of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Fundamental to all of these processes is lithography, i.e. the formation of three-dimensional (3D) relief images on the substrate for subsequent transfer of the pattern into the substrate.

The word lithography comes from the Greek lithos, meaning stones, and graphia, meaning to write. It means quite literally writing on stones. In the case of semiconductor lithography, our stones are silicon wafers and our patterns are written with a light-sensitive polymer called a photoresist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithog-raphy and etch pattern transfer steps are repeated at least 10 times, but more typically 25 to 40 times to make one circuit. Each pattern being printed on the wafer is aligned to the previously formed patterns as slowly the conductors, insulators and selectively doped regions are built up to form the fi nal device.

The importance of lithography can be appreciated in two ways. First, due to the large number of lithography steps needed in IC manufacturing, lithography typically accounts

Mask

Wafer

Mask

Wafer

2 Fundamental Principles of Optical Lithography

for about 30 % of the cost of manufacturing a chip. As a result, IC fabrication factories (‘fabs’) are designed to keep lithography as the throughput bottleneck. Any drop in output of the lithography process is a drop in output for the entire factory. Second, lithography tends to be the technical limiter for further advances in transistor size reduction and thus chip performance and area. Obviously, one must carefully understand the trade-offs between cost and capability when developing a lithography process for manufacturing. Although lithography is certainly not the only technically important and challenging process in the IC manufacturing fl ow, historically, advances in lithography have gated advances in IC cost and performance.

1.1 Basics of IC Fabrication

A semiconductor is not, as its name might imply, a material with properties between an electrical conductor and an insulator. Instead, it is a material whose conductivity can be readily changed by several orders of magnitude. Heat, light, impurity doping and the application of an electric fi eld can all cause fairly dramatic changes in the electrical con-ductivity of a semiconductor. The last two can be applied locally and form the basis of a transistor: by applying an electric fi eld to a doped region of a semiconductor material, that region can be changed from a good to a poor conductor of electricity, or vice versa. In effect, the transistor works as an electrically controlled switch, and these switches can be connected together to form digital logic circuits. In addition, semiconductors can be made to amplify an electrical signal, thus forming the basis of analog solid-state circuits.

By far the most common semiconductor in use is silicon, due to a number of factors such as cost, formation of a stable native oxide and vast experience (the fi rst silicon IC was built in about 1960). A wafer of single-crystal silicon anywhere from 75–300 mm in diameter and about 0.6–0.8 mm thick serves as the substrate for the fabrication and inter-connection of planar transistors into an IC. The most advanced circuits are built on 200- and 300-mm-diameter wafers. The wafers are far larger than the ICs being made so that each wafer holds a few hundred (and up to a few thousand) IC devices. Wafers are pro-cessed in lots of about 25 wafers at a time, and large fabs can have throughputs of greater than 10 000 wafers per week. The cycle time for making a chip, from starting bare silicon wafers to a fi nished wafer ready for dicing and packaging, is typically 30–60 days. Semi-conductor processing (or IC fabrication) involves two major tasks:

• Creating small, interconnected 3D structures of insulators and conductors in order to manipulate local electric fi elds and currents

• Selectively doping regions of the semiconductor (to create p–n junctions and other electrical components) in order to manipulate the local concentration of charge carriers

1.1.1 Patterning

The 3D microstructures are created with a process called patterning. The common sub-tractive patterning process (Figure 1.1) involves three steps: (1) deposition of a uniform fi lm of material on the wafer; (2) lithography to create a positive image of the pattern

Introduction to Semiconductor Lithography 3

that is desired in the fi lm; and (3) etch to transfer that pattern into the wafer. An additive process (such as electroplating) changes the order of these steps: (1) lithography to create negative image of the pattern that is desired; and (2) selective deposition of material into the areas not protected by the lithographically produced pattern. Copper is often patterned additively using the damascene process (named for a unique decorative metal fi ll process applied to swords and developed in Damascus about 1000 years ago).

Deposition can use many different technologies dependent on the material and the desired properties of the fi lm: oxide growth (direct oxidation of the silicon), chemical vapor deposition (CVD), physical vapor deposition (PVD), evaporation and sputtering. Common fi lms include insulators (silicon dioxide, silicon nitride, phosphorous-doped glass, etc.) and conductors (aluminum, copper, tungsten, titanium, polycrystalline silicon, etc.). Lithography, of course, is the subject of this book and will be discussed at great length in the pages that follow. Photoresists are classed as positive, where exposure to light causes the resist to be removed, and negative, where exposed patterns remain after development. The goal of the photoresist is to resist etching after it has been patterned so that the pattern can be transferred into the fi lm.

1.1.2 Etching

Etch involves both chemical and mechanical mechanisms for removal of the material not protected by the photoresist. Wet etch, perhaps the simplest form of etch, uses an etchant solution such as an acid that chemically attacks the underlying fi lm while leaving the photoresist intact. This form of etching is isotropic and thus can lead to undercutting as the fi lm is etched from underneath the photoresist. If anisotropic etching is desired (and most always it is), directionality must be induced into the etch process. Plasma etching replaces the liquid etchant with a plasma – an ionized gas. Applying an electric fi eld causes the ions to be accelerated downward toward the wafer. The resulting etch is a mix of chemical etching due to reaction of the fi lm with the plasma and physical sputtering due to the directional bombardment of the ions hitting the wafer. The chemical nature of the etch can lead to good etch selectivity of the fi lm with respect to the resist (selectivity being defi ned as the ratio of the fi lm etch rate to the resist etch rate) and with respect to the substrate below the fi lm, but is essentially isotropic. Physical sputtering is very

Wafer

Film

Resist

Deposition

Lithography

Etch

ResistStrip

Figure 1.1 A simple subtractive patterning process


directional (etching is essentially vertical only), but not very selective (the resist etches at about the same rate as the fi lm to be etched). Reactive ion etching combines both effects to give good enough selectivity and directionality – the accelerated ions provide energy to drive a chemical etching reaction.

The photoresist property of greatest interest for etching is the etch selectivity, which is dependent both on the photoresist material properties and the nature of the etch process for the specifi c fi lm. Good etch processes often have etch selectivities in excess of 4 (for example, polysilicon with a novolac resist), whereas poor selectivities can be as low as 1 (for example, when etching an organic bottom antirefl ection coating). Etch selectivity and the thickness of the fi lm to be etched determine the minimum required resist thick-ness. Mechanical properties of the resist, such as adhesion to the substrate and resistance to mechanical deformation such as bending of the pattern, also play a role during etching.

For an etch process without perfect selectivity, the shape and size of the fi nal etched pattern will depend on not only the size of the resist pattern but its shape as well. Consider a resist feature whose straight sidewalls make an angle q with respect to the substrate (Figure 1.2). Given vertical and horizontal etch rates of the resist RV and RH, respectively, the rate at which the critical dimension (CD) shrinks will be

d

dH V

CD

tR R= +2( cot )θ (1.1)

Thus, the rate at which the resist CD changes during the etch is a function of the resist sidewall angle. As the angle approaches 90°, the vertical component ceases to contribute and the rate of CD change is at its minimum. In fact, Equation (1.1) shows three ways to minimize the change in resist CD during the etch: improved etch selectivity (making both RH and RV smaller), improved anisotropy (making RH/RV smaller) and a sidewall close to vertical (making cotq smaller).

The example above, while simple, shows clearly how resist profi le shape can affect pattern transfer. In general, the ideal photoresist shape has perfectly vertical sidewalls. Other nonideal profi le shapes, such as rounding of the top of the resist and resist footing, will also affect pattern transfer.

Resist

RH

RV

q

Figure 1.2 Erosion of a photoresist line during etching, showing the vertical and horizontal etch rate components


1.1.3 Ion Implantation

Selective doping of certain regions of the semiconductor begins with a patterning step (Figure 1.3). Regions of the semiconductor that are not covered by photoresist are exposed to a dopant impurity. p-type dopants like boron have three outer shell electrons and when inserted into the crystal lattice in place of silicon (which has four outer electrons) create mobile holes (empty spots in the lattice where an electron could go). n-type dopants such as phosphorous, arsenic and antimony have fi ve outer electrons, which create excess mobile electrons when used to dope silicon. The interface between p-type regions and n-type regions of silicon is called a p–n junction and is one of the foundational structures in the building of semiconductor devices.

The most common way of doping silicon is with ion implantation. The dopant is ionized in a high-vacuum environment and accelerated into the wafer by an electric fi eld (voltages of hundreds of kilovolts are common). The depth of penetration of the ions into the wafer is a function of the ion energy, which is controlled by the electric fi eld. The force of the impact of these ions will destroy the crystal structure of the silicon, which then must be restored by a high-temperature annealing step, which allows the crystal to reform (but also causes diffusion of the dopant). Since the resist must block the ions in the regions where dopants are not desired (that is, in the regions covered by the resist), the resist thickness must exceed the penetration depth of the ions.

Ion implantation penetration depth is often modeled as a Gaussian distribution of depths, i.e. the resulting concentration profi le of implanted dopants follows a Gaussian shape. The mean of the distribution (the peak of the concentration profi le) occurs at a depth called the projected range, Rp. The standard deviation of the depth profi le is called the straggle, ∆Rp. For photoresists, the projected range varies approximately linearly with implant energy, and inversely with the atomic number of the dopant (Figure 1.4a). A more accurate power-law model (as shown in Figure 1.4a) is described in Table 1.1. The straggle varies approximately as the square root of implant energy, and is about indepen-dent of the dopant (Figure 1.4b). For higher energies (1 MeV and above), higher atomic number dopants produce more straggle. When more detailed predictions are needed, Monte Carlo implantation simulators are frequently used.

ResistLithography

Ion Implantation

ResistStrip

Wafer

DopantIons

Figure 1.3 Patterning as a means of selective doping using ion implantation


In order to mask the underlying layers from implant, the resist thickness must be set to at least

resist thickness R m R≥ +p p∆ (1.2)

where m is set to achieve a certain level of dopant penetration through the resist. For example, if the dopant concentration at the bottom of the resist cannot be more than 10−4 times the peak concentration (a typical requirement), then m should be set to 4.3. While the resolution requirements for the implant layers tend not to be challenging, often the thickness required for adequate stopping power does pose real challenges to the lithogra-pher. Carbonization of the resist during high energy and high dose implantation (as well as during plasma etching) can also result in a fi lm that is very diffi cult to strip away at the end.

1.1.4 Process Integration

The combination of patterning and selective doping allows the buildup of the structures required to make transistors. Figure 1.5 shows a diagrammatical example of a pair of CMOS (complementary metal oxide semiconductor) transistors. Subsequent metal layers (up to 10 metal levels are not uncommon) can connect the many transistors into a full

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Figure 1.4 Measured and fi tted ion implantation penetration depths for boron, phosphorous and arsenic in AZ 7500 resist: (a) projected range and (b) straggle. Symbols are data1 and curves are power-law fi ts to the data as described in Table 1.1. For the straggle data, the empirical model fi t is ∆Rp = 4.8E0.5 where E is the ion energy in keV and ∆Rp is the straggle in nm

Table 1.1 Empirical model of ion implanted projected range (Rp, in nm) into photoresist versus ion energy (E, in keV) as Rp = aEb

Dopant Coeffi cient a Power b

Boron 26.9 0.63Phosphorous 5.8 0.80Arsenic 0.49 1.11


circuit and the fi nal metal layer will provide connections to the external pins of the device package.

Many lithographic levels are required to fabricate an IC, but about 1/3 of these levels are considered ‘critical’, meaning that those levels have challenging lithographic require-ments. Which levels are critical depends on the process technology (CMOS logic, DRAM, BiCMOS, etc.). The most common critical levels of a CMOS process are active area, shallow trench isolation (STI), polysilicon gate, contact (between metal 1 and poly) and via (between metal layers), and metal 1 (the fi rst or bottom most metal layer). For a large logic chip with 10 layers of metal, the fi rst three will be ‘1×’, meaning the dimensions are at or nearly at the minimum metal 1 dimensions. The next three metal layers will be ‘2×’, with dimensions about twice as big as the 1× metal levels. The next few metal levels will be 4×, with the last few levels as large as 10×. For a DRAM device, some of the critical levels are known as storage, isolation, wordline and bitline contact (see Figure 1.6 for example design patterns for these four levels).

1.2 Moore’s Law and the Semiconductor Industry

The impact of semiconductor ICs on modern life is hard to overstate. From computers to communication, entertainment to education, the growth of electronics technology, fueled

Silicon Wafer

p-welln-well

p+p+

Oxide Polysilicon Metal

n+n+

Figure 1.5 Cross section of a pair of CMOS transistors showing most of the layers through metal 1

(a) Storage (b) Isolation (c) Wordline (d) Bitline Contact

Figure 1.6 Critical mask level patterns for a 1-Gb DRAM chip2. Each pattern repeats in both x and y many times to create the DRAM array


by advances in semiconductor chips, has been phenomenal. The impact has been so pro-found that it is now often taken for granted: consumers have come to expect increasingly sophisticated electronics products at ever lower prices, and semiconductor companies expect growth and profi ts to improve continually. The role of optical lithography in these trends has been, and will continue to be, vital.

The remarkable evolution of semiconductor technology from crude single transistors to billion-transistor microprocessors and memory chips is a fascinating story. One of the fi rst ‘reviews’ of progress in the semiconductor industry was written by Gordon Moore, a founder of Fairchild Semiconductor and later Intel, for the 35th anniversary issue of Electronics magazine in 1965.3 After only 6 years since the introduction of the fi rst com-mercial planar transistor in 1959, Moore observed an astounding trend – the number of electrical components per IC chip was doubling every year, reaching about 60 transistors in 1965. Extrapolating this trend for a decade, Moore predicted that chips with 64 000 components would be available by 1975! Although extrapolating any trend by three orders of magnitude can be quite risky, what is now known as Moore’s Law proved amazingly accurate.

Some important details of Moore’s remarkable 1965 paper have become lost in the lore of Moore’s Law. First, Moore described the number of components per IC, which included resistors and capacitors, not just transistors. Later, as the digital age reduced the predomi-nance of analog circuitry, transistor count became a more useful measure of IC complex-ity. Further, Moore clearly defi ned the meaning of the ‘number of components per chip’ as the number which minimized the cost per component. For any given level of manu-facturing technology, one can always add more components – the problem being a reduc-tion in yield and thus an increase in the cost per component. As any modern IC manufacturer knows, cramming more components onto ICs only makes sense if the resulting manufac-turing yield allows costs that result in more commercially desirable chips. This ‘minimum cost per component’ concept is in fact the ultimate driving force behind the economics of Moore’s Law.

Consider a very simple cost model for chip manufacturing as a function of lithographic feature size. For a given process, the cost of making a chip is proportional to the area of silicon consumed divided by the fi nal yield of the chips. Will shrinking the feature sizes on the chip result in an increase or decrease in cost? The area of silicon consumed will be roughly proportional to the feature size squared. But yield will also be a function of feature size. Assuming that the only yield limiter will be the parametric effects of reduced feature size, a simple yield model might look something like

Yield Costw

Yieldw w= − ∝− −1 0

2 222

e ,( ) / σ (1.3)

where w is the feature size (which must be greater than w0 for this model), w0 is the ulti-mate resolution (feature size at which the yield goes to zero), and s is the sensitivity of yield to feature size. Figure 1.7 shows this yield model and the resulting cost function for arbitrary but reasonable parameters.

But minimizing cost is not really the goal of a semiconductor fab – it is maximizing profi t. Feature size affects total profi t in two ways other than chip cost. The number of chips per wafer is inversely proportional to the area of each chip, thus increasing the


number of chips that can be sold (that is, the total possible throughput of chips for the fab). Also, the value of each chip is often a function of the feature size. Smaller transistors generally run faster and fi t in smaller packages – both desirable features for many applica-tions. Assuming the price that a chip can be sold for is inversely proportional to the minimum feature size on the chip, an example profi t model for a fab is shown in Figure 1.8. The most important characteristic is the steep falloff in profi t that occurs when trying to use a feature size below the optimum. For the example here, the profi t goes to zero if one tries to shrink the feature size by 10 % below its optimum value (unless, of course,

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.)Figure 1.7 A very simple yield and cost model shows the feature size that minimizes chip cost (w0 = 65 nm, s = 10 nm). Lowest chip cost occurs, in this case, when w = 87 nm, corre-sponding to a chip yield of about 90 %

Figure 1.8 Example fab profi t curve using the yield and cost models of Figure 1.7 and assuming the value of the chip is inversely proportional to the minimum feature size. For this example, maximum profi t occurs when w = 80 nm, even though the yield is only 65 %


the yield curve can be improved). It is a diffi cult balancing act for a fab to try to maximize its profi t by shrinking feature size without going too far and suffering from excessive yield loss.

In 1975, Moore revisited his 1965 prediction and provided some critical insights into the technological drivers of the observed trends.4 Checking the progress of component growth, the most advanced memory chip at Intel in 1975 had 32 000 components (but only 16 000 transistors). Thus, Moore’s original extrapolation by three orders of magni-tude was off by only a factor of 2. Even more importantly, Moore divided the advances in circuit complexity among its three principle components: increasing chip area, decreas-ing feature size, and improved device and circuit designs. Minimum feature sizes were decreasing by about 10 % per year (resulting in transistors that were about 21 % smaller in area, and an increase in transistors per area of 25 % each year). Chip area was increas-ing by about 20 % each year (Figure 1.9). These two factors alone resulted in a 50 % increase in the number of transistors per chip each year. Design cleverness made up the rest of the improvement (33 %). In other words, the 2× improvement = (1.25)(1.20)(1.33).

Again, there are important details in Moore’s second observation that are often lost in the retelling of Moore’s Law. How is ‘minimum feature size’ defi ned? Moore explained that both the linewidths and the spacewidths used to make the circuits are critical to density. Thus, his density-representing feature size was an average of the minimum line-width and the minimum spacewidth used in making the circuit. Today, we use the equiva-lent metric, the minimum pitch divided by 2 (called the minimum half-pitch). Unfortunately, many modern forecasters express the feature size trend using features that do not well represent the density of the circuit. Usually, minimum half-pitch serves this purpose best.

By breaking the density improvement into its three technology drivers, Moore was able to extrapolate each trend into the future and predict a change in the slope of his

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Figure 1.9 Moore’s Law showing (a) an exponential increase (about 15 % per year) in the area of a chip, and (b) an exponential decrease (about 11 % per year) in the minimum feature size on a chip (shown here for DRAM initial introduction)

Fundamental Principles of Optical Lithography

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