Fundamental Concepts of BPU

7/27/2019 Fundamental Concepts of BPU

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Fundamental Concepts

Processor fetches one instruction at a time and

perform the operation specified.

Instructions are fetched from successive memory

locations until a branch or a jump instruction isencountered.

Processor keeps track of the address of the memory

location containing the next instruction to be fetched

using Program Counter (PC).

Instruction Register (IR)


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Executing an Instruction

Fetch the contents of the memory location pointed

to by the PC. The contents of this location are

loaded into the IR (fetch phase).

IR [[PC]] Assuming that the memory is byte addressable,

increment the contents of the PC by 4 (fetch phase).

PC [PC] + 4

Carry out the actions specified by the instruction in

the IR (execution phase).


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Processor Organization

lint

rlin

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Cr r y- i n

LU

C

u

u

I

c n t r lLU

lin

C n t r l i n l

n-

In tr u cti n

c r n

I nt r nl r c r

c n t r l l i c

F i ur . . i n l u r n i t i n f t h t t h i n i r c r .

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Datapath


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Executing an Instruction

Transfer a word of data from one processorregister to another or to the ALU.

Perform an arithmetic or a logic operation

and store the result in a processor register. Fetch the contents of a given memory

location and load them into a processor

register. Store a word of data from a processor

register into a given memory location.


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Register Transfers

All operations and data transfers are controlled by the processor clock.

i r 7. . i r ri r i .

l ck

i u

i n

u

Input and output gating for one register bit.


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Performing an Arithmetic or

Logic Operation

The ALU is a combinational circuit that has no

internal storage.

ALU gets the two operands from MUX and bus.

The result is temporarily stored in register Z. What is the sequence of operations to add the

contents of register R1 to those of R2 and store the

result in R3?

1. R1out, Yin

2. R2out, SelectY, Add, Zin

3. Zout, R3in


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Fetching a Word from Memory

Address into MAR; issue Read operation; data into MDR.

m r - u

i r 7 . . i r l i l rr i r .

linn rn l r c r

uuu

nn

Connection and control signals for register MDR.


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Fetching a Word from Memory

The response time of each memory access varies(cache miss, memory-mapped I/O,).

To accommodate this, the processor waits until itreceives an indication that the requested operation

has been completed (Memory-Function-Completed,MFC).

Move (R1), R2 MAR [R1]

Start a Read operation on the memory bus

Wait for the MFC response from the memory Load MDR from the memory bus

R2 [MDR]


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Execution of a Complete

Instruction

Add (R3), R1

Fetch the instruction

Fetch the first operand (the contents of thememory location pointed to by R3)

Perform the addition

Load the result into R1


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Instruction

e c o

1 ut , in , , l c t , , in

ut , in , Yin , F

ut , I in

ut , in ,

1 ut , Yin , F

ut , l ct Y, , in

ut , 1in , n

F i ur . . n tr l u n c f r c u ti n f t h in tr uc ti n , 1 .

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Cr r y- i n

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C

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Add (R3), R1

Add R2, R1 ?


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Instruction

e c o

1 ut , in , , l c t , , in

ut , in , Yin , F

ut , I in

ut , in ,

1 ut , Yin , F

ut , l ct Y, , in

ut , 1in , n

F i ur . . n tr l u n c f r c u ti n f t h in tr uc ti n , 1 .

lint

rlin

umry

Cr r y- i n

LU

C

u

u

I

c n t r lLU

lin

C n t r l i n l

n-

In tr u cti n

c r n

I nt r n l r c r

c n t r l l i c


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Add R2, R1

R2out


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Execution of Branch

Instructions

A branch instruction replaces the contents of

PC with the branch target address, which is

usually obtained by adding an offset X given

in the branch instruction.

The offset X is usually the difference between

the branch target address and the address

immediately following the branch instruction. Conditional branch


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Execution of Branch

Instructions

StepAction

1 PCout, MARin,Read,Select4,Add, Zin

2 Zout, PCin, Yin, WMFC

3 MDRout,IRin

4 Offset-field-of-IRout,Add, Zin

5 Zout, PCin, End

Control sequence for an unconditional branch instruction.


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Multiple-Bus Organizationm r y ut l ini u r . . h r - u r ni t i n f t h t t h.

u u u C

I n t r u t i nr

C

it r

fil

C n t n t

LU

U

I n r m n t r

rlin

I

Allow the contents of two

different registers to be

accessed simultaneously and

have their contents placed onbuses A and B.

Allow the data on bus C to

be loaded into a third register

during the same clock cycle.

Incrementer unit.

ALU simply passes one of ts

two input operands

unmodified to bus C

control signal: R=A or R=B


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Multiple-Bus Organization

Add R4, R5, R6

StepAction

1 PCout, R=B, MARin,Read,IncPC

2 WMFC

3 MDRoutB, R=B,IRin

4 R4outA, R5outB, SelectA,Add,R6in,End

Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization


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Exercise

What is the controlsequence forexecution of the

instructionAdd R1, R2

including theinstruction fetchphase? (Assumesingle busarchitecture)

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Cr r y- i n

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C n t r l i n l

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In tr u cti n

c r n

I nt r n l r c r

c n t r l l i c


Ulct

C n t n t

Fundamental Concepts of BPU

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