Fully Integrated Low-Drop-Out Regulator Design based on ...

Fully Integrated Low-Drop-Out RegulatorDesign based on Event-Driven PI Control

Doyun Kim

Submitted in partial fulfillment of the

requirements for the degree of

Doctor of Philosophy

in the Graduate School of Arts and Sciences

COLUMBIA UNIVERSITY

2019

c©2019

Doyun Kim

All Rights Reserved

ABSTRACT

Fully Integrated Low-Drop-Out RegulatorDesign based on Event-Driven PI Control

Doyun Kim

A system-on-chip (SoC) with near-threshold supply voltage (NTV) operation has received

a significant amount of attention. Its high energy-efficiency supports a number of low-

power emerging applications such as wireless sensor networks and Internet-of-Thing edge

devices. Integrating various digital, analog, mixed-signal, and power sub-systems, such SoC

designs need to employ tens of voltage domains to push the envelope of energy-efficiency,

performance, and robustness. A low-drop-out (LDO) regulator is a key building block for

creating voltage domains on a chip thanks to its high power density.

In particular, its digital implementation, i.e., digital LDO, recently has emerged as a

popular topology since it can support a wide range of input voltage from super-threshold

to near-threshold voltage regimes, while conventional analog LDOs become less effective.

One of the critical overheads in existing digital LDO designs is a requirement of off-chip

output capacitor for stabilizing the output voltage, due to inadequate latency in active

control paths. It is possible to employ higher clock frequency in a digital LDO; however

such solutions inevitably increase power dissipation. This off-chip capacitor overhead can

significantly increase chip pin count and printed circuit board (PCB) space, thus limiting

the number of power domains that an SoC can have.

This thesis presents my research on fully-integrated digital LDO designs based on event-

driven control architecture. My research focuses on scaling down the output capacitor size

(COUT ) to the integrable level and improving transient performance such as maximum voltage

change and settling time. To shrink the output capacitor size, we introduced the event-driven

control and the binary digital PI controller in our first event-driven LDO design. Thanks to

the event-driven control, we achieved control loop latency reduction without compromising

power consumption, leading to output capacitor size reduction. The first design shows 2.7x

improvement over the previous digital LDO designs in Figure-of-Merit with a 400pF of

output capacitor. To further reduce output capacitor size and support larger load current,

we implemented the second event-driven digital LDO designs with fine-grained parallelism.

The parallel structure of its PI controller reduces the latency of the proportional part, which

mainly regulates output voltage, so it achieves better transient performance with reduced

size of capacitor. Also, the parallel-shift-register-based integration part lowers computation

and area overheads. The second design outperforms the state of the arts by over 17x in

Figure-of-Merits with only a 100pF of output capacitor. In the last design, we introduced

initialization and self-triggering control. The initialization estimates load current change in

the beginning of regulation process and sets the controller output close to the desired value.

This leads to substantial reduction of settling time. Also, thanks to self-triggering control,

the hardware overhead from counting the event interval is removed without the first response

time degradation, achieving high current density. The last design with a 100pF of output

capacitor improves settling time and current density by 3.8x and 6.7x, respectively, while

achieving comparable transient performance in terms of Figure-of-Merit.

Table of Contents

List of Figures iii

List of Tables vi

1 Introduction 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Low-drop-out regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Comparison between analog and digital LDO designs . . . . . . . . . . . . . 3

1.4 Event-driven control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5 Event-driven digital LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Event-driven LDO based on binary PI control 10

2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Overall architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Continuous-time ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Trigger generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Binary PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Challenges of Event-driven systems . . . . . . . . . . . . . . . . . . . . . . . 19

i

2.6.1 Sticking Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.2 Limit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7 Stability analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.8 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Event-driven LDO based on parallelized controller 33

3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33


3.3 Separate PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 P part structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5 I part structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.6 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 Event-driven LDO with self-triggering control and initialization 46

4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46


4.3 Pulse controller for self-triggering control . . . . . . . . . . . . . . . . . . . . 49

4.4 Integration part with initialization . . . . . . . . . . . . . . . . . . . . . . . . 51

4.5 Proportional part with timing hysteresis . . . . . . . . . . . . . . . . . . . . 53

4.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Conclusion 59

Bibliography 60

ii

List of Figures

1.1 Basic structure of (a) analog and (b) digital LDOs . . . . . . . . . . . . . . . 4

1.2 Latency comparison between (a) time-driven and (b) event-driven control . . 7

1.3 Step response and triggering behavior comparison between (a) time-driven

and (b) event-driven control . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Overall architecture of the proposed LDO design . . . . . . . . . . . . . . . . 11

2.2 Continuous-time ADC structure . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Trigger generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Pulse blocker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 Timing diagram of regulation process . . . . . . . . . . . . . . . . . . . . . . 15

2.6 Transient response comparison among P-only, I-only and PI controllers . . . 17

2.7 Binary digital PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.8 Illustration of PI computation . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.9 Illustration of sticking problem . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.10 Modified trigger generator with a sticking counter . . . . . . . . . . . . . . . 21

2.11 Illustration of limit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.12 Modified PI controller with adaptive gain control . . . . . . . . . . . . . . . 22

iii

2.13 Eigenvalue plot for stability analysis across different parameters . . . . . . . 25

2.14 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.15 Transient snapshot of load regulation . . . . . . . . . . . . . . . . . . . . . . 27

2.16 Impact of gains (KP , KI) on (a) VDROOP , (b) TS . . . . . . . . . . . . . . . . 27

2.17 Impact of (a) TFRO, (b) VREF , (c) COUT and (d) ∆ILOAD on performance . . 28

2.18 (a) Different error assignment and its impact on transient performance ((b)

VDROOP , (c) TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1 Overall architecture of the proposed LDO . . . . . . . . . . . . . . . . . . . 34

3.2 Impact of control latency (TLAT ) on maximum voltage change (∆VOUT ) . . . 35

3.3 Comparison between (a) conventional and (b) parallel PI controllers . . . . . 36

3.4 P part structure with PMOS and NMOS power tranasistors . . . . . . . . . 37

3.5 Parallelized pulse generator and I part with parallel shift-registers . . . . . . 38

3.6 Pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.7 Pulse shifter structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.8 Pulse routing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.9 Pulse routing unit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.10 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.11 Transient snapshot of load regulation . . . . . . . . . . . . . . . . . . . . . . 41

3.12 Impact of gains (KP , KI) on (a) ∆VOUT , (b) TS, and (c) NEV . . . . . . . . 42

3.13 (a) Impact of NEV and (b) optimal gain selection . . . . . . . . . . . . . . . 42

3.14 (a) Load regulation and (b) current efficiency across different VIN . . . . . . 43

3.15 Impact of resolution on line regulation . . . . . . . . . . . . . . . . . . . . . 44

iv

3.16 Impact of dropout on load regulation . . . . . . . . . . . . . . . . . . . . . . 44

4.1 Control comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.2 Entire architecture of the proposed LDO design . . . . . . . . . . . . . . . . 48

4.3 Pulse controller with FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4 Pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.5 Steady state detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.6 Timing diagram of regulation process with initialization . . . . . . . . . . . . 51

4.7 Integration part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.8 Timing diagram with and without timing hysteresis . . . . . . . . . . . . . . 53

4.9 Proportional part with the implementation of timing hysteresis . . . . . . . . 54

4.10 Chip micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.11 Transient response with and without initialization . . . . . . . . . . . . . . . 56

4.12 Impact of gains (KP , KI) on transient performance without initialization . . 57

4.13 Impact of initialization on (a) TS, (b) ∆VOUT . . . . . . . . . . . . . . . . . 57

4.14 Load regulation and current efficiency across multiple VIN . . . . . . . . . . 58

v

List of Tables

2.1 Comparison table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31



vi

Acknowledgements

Now is the time to move on to the next chapter of my life. In retrospect, I never imagined

myself living in New York, the biggest and most exciting city in the world, but I met a good

advisor, good group members, and good friends and my wife here. Without them, I could

not enjoy my PhD Life. Five years of my life at Columbia University has helped to grow

myself more than I expected. Thanks to many others’ help, I learned important lessons for

the rest of my life not only as a researcher, but also as a person.

I am proud and honored that my advisor was Professor Mingoo Seok. I was not a great

PhD student in the beginning, but his kind advice and care always encouraged me to be a

better researcher. He always listened to my opinion carefully, treated me with respect, and

tried to help me out as much as possible. I was lucky to see in person and learn his grit,

professional attitude, time management skill, passion for research, and many other valuable

skills. Those are engraved in my mind and I am sure that the experience with him will guide

me through the rest of my life. Thank you, Mingoo.

I would also like to express great gratitude to the thesis committee, Professor Yannis

Tsividis, Professor Matthias Preindl, Professor Luca Carloni, and Professor Simha Sethu-

madhavan. Thank you all for your commitment and valuable time for my graduation. Also,

I appreciate Professor Yannis Tsividis, Professor Matthias Preindl, Professor Peter Kinget

for the technical discussion about my research. Your constructive feedback improves the

quality of my research enormously.

My colleagues in VLSI research group had made my life in Mudd building enjoyable.

vii

Thank you for having all the technical discussion with me and listening to my weird jokes

all the time. Seongjong Kim, Teng Yang, Jiangyi Li, Joao Cerqueira, Zhewei Jiang, Pavan

Kumar Chundi, Sung Kim, Dongkwon Kim, Wei Jin, Tianchan Guan, and Minhao Yang.

Even we did not have much time outside the lab, but you all made me feel like family. I

want to say thank you again to Seongjong Kim for inspiring me to be a better researcher as

well as a better person. You were always a great leader of team VLSI for us and you will be

always my soul mentor.

Outside the group, I would like to thank Junghyun Kwak for being a great roommate

and best friend and making me feel not alone, Youngwan Kim and Jonghee Kang for spend-

ing great time for me, Taekjin Lee for being a workout and drinking rival, Guen Park for

inviting me to your awesome parties, Seungki Min for listening to my random ideas and all

the circuit people from other groups I have met in the school, Yu Chen, Ning Guo, Jah-

navi Sharma, Anandaroop Chakrabarti, Jin Zhou, Jeffrey Chuang, Linxiao Zhang, Negar

Reiskarimian, Yang Xu, Daniel de Godoy Peixoto, Matt Bajor, Guoxiang Hang, Yudong

Zhang, and Thomas Repetti for being a good company.

Special thanks to all my friends from hometown, high school and college. Whenever I

came back to Korea, all of you always welcomed me with open arms. With your cheerful

messages and prays, I still feel well-connected to you guys. Hope you all are doing great and

we can meet sooner or later. Next time is on me!

Most importantly, I would like to thank my family. My parents and parents-in-law always

believed in me and prayed for me all the time. I have not expressed my gratitude enough to

them, but I always deeply appreciate your support. Also, my only brother and sister-in-law,

even we do not talk to each other very often, I know we pray for each other. Thank you for

viii

all your support.

Lastly, my wife, Jihyun Agnes Kim, meeting you here was the luckiest thing that ever

happened during my PhD and my life. You always make me want to be a better man. I

really appreciate your kind care, trust, feedback and everything. I was not able to go through

my PhD without your love. Thank you and I love you to the moon and back.

ix

To my beloved wife, family and friends

x

Chapter 1

Introduction

1.1 Background

As portable systems and Internet-of-Things applications flourish, power consumption has

become one of the major constraints. To implement such systems, modern System-on-Chip

(SoC) designs require analog, digital, and mixed-signal sub-systems to perform various tasks

including sensing, signal processing and communication. The advance of technology allows

to implement multiple modules in single System-on-Chip (SoC) design, but it is hard to meet

the increasing demand for various functions in a system with tight power constraint.

Fine-grained power management of a system is essential for power saving. Each module

in a system requires different supply voltage specification. Therefore, the system must im-

plement multiple power domains to provide optimal voltages to avoid consuming more power

than required. Furthermore, fine-grained power management can support power-saving tech-

niques such as Dynamic Voltage Scaling (DVS) to further save power consumption [1, 2].

As the number of power domains increases, area and power efficiency of voltage regulators

1

have become more important. Voltage regulators implement separate power domains and

supply power from source to load circuits while output voltage must be stable. The input

voltage from power source such as a battery changes over time and current pulled by a

load circuit may fluctuate upon tasks, especially when the load is digital circuit. Therefore,

voltage regulators need to respond to and compensate changes in voltage and current fast

and accurate.

Voltage regulators can be categorized into two types: switching regulators and linear

regulators. Switching regulators such as buck converters use switches and passive components

such as an inductor. On the other hand, linear regulators operate as a voltage divider:

linear regulators adjust its equivalent impedance as compared to its load impedance to

control output voltage. Linear regulators are preferable for fully integrated systems. Unlike

switching regulators, linear regulators do not need large inductors so it can substantially

reduce area and cost when a large number of power domains are needed. Also, the response

time of linear regulators to external changes is relatively short so they are applicable to

power-saving techniques.

1.2 Low-drop-out regulator

A low-drop-out regulators (LDO) is one of the most common voltage regulators. As

its name suggests, An LDO supports very small drop-out, the voltage difference between

input and output voltage, by using PFET power transistors. The small drop-out voltage

improves power efficiency. An LDO uses negative feedback control to regulate its output

voltage. First, it detects the voltage error, i.e., the voltage difference between output voltage

2

and set-point voltage. Based on the error, its controller produces either analog or digital

value to determines the amount of current to supply and adjust its resistance. Then, power

transistors produce current required for its load.

LDO designs have multiple performance metrics. First, it needs to support a wide range of

input voltage, output voltages and load current. DC line regulation defines output voltage

change against DC input voltage change. Power supply rejection ratio (PSRR) indicates

output voltage stability against continuously-changing input voltage such as sinusoidal input.

DC load regulation measures output voltage change against DC load current change. The

transient performance for load regulation is defined by two metrics: maximum output voltage

change and settling time against step change of load current. Definitely, quiescent(static)

current of controllers and drop-out voltage must be minimized for high power efficiency.

Lastly, area is also an important metric, so we must reduce active area (controller and power

transistors) and passive area (output capacitor).

1.3 Comparison between analog and digital LDO de-

signs

An LDO can be categorized into two types: analog and digital. Figure 1.1 shows the

basic structure of each LDO design. Most analog LDOs consists of a high-gain error amplifier

and one large PFET power transistor. The amplifier has two inputs from reference voltage

and output voltage, whether they are scaled by a resistive divider or not. The amplifier

produces analog voltage output which is proportional to the differential input voltage (error

3

Figure 1.1: Basic structure of (a) analog and (b) digital LDOs

voltage). The output voltage of the amplifier is applied to the gate of single large PFET

power transistor to adjust VGS of the transistor, thus current provided from the power

transistor. Large gain from the amplifier and power transistor allows a wide range of supply

current with only small error voltage. High bandwidth of feedback control loop in analog

LDOs allows to regulate large load current change without having large compensation and

output capacitors. Also, it helps to prevent output voltage change from power supply noise.

However, a stack of multiple transistors in the high gain error amplifier limits the range

of input voltage to high. It is a critical downside for low-power applications, which runs

at near-threshold voltages. Also, the high performance error amplifier may consume much

power.

On the other hand, digital LDOs commonly consist of a comparator or ADC (Analog-to-

Digital Converter), digital controller, and power transistor arrays. Like the error amplifier in

analog LDOs, a comparator or ADC detects error voltage and converts it to digital value. The

digital value is applied to the subsequent digital controller. The digital controller updates

its digital output and it determines how many power transistors turn on. Based on the

4

number and size of turn-on power transistors, supply current is determined. Thanks to its

digital-intensive design, the digital LDO is easier to implement and integrate across different

technology nodes. Also, less complexity of ADC or comparator enables low input voltage

operation unlike analog LDOs. Therefore, digital LDO is more applicable for low-power

applications. In addition, fully turn-on power transistor arrays can supply more current

than power transistor in analog LDOs, which partially turns on. This leads to area efficiency.

However, one of difficulties in digital LDOs is its reliance control loop on clock. As the ADC

and digital controller in most digital LDOs produce outputs upon clock, the use of slow clock

causes large control loop latency, resulting in degraded regulation performance. Conversely,

as clock speed increases, the control loop latency decreases and the regulation performance

is improved. However, fast clock leads to large power consumption from triggering the

ADC and controller more often. In other words, digital LDOs have an inevitable trade-off

between power consumption and regulation performance. In order to break this trade-off,

we introduce event-driven control to digital LDO designs.

5

1.4 Event-driven control

Event-driven control as known as event-based control has originally been explored on

theory and simulation level to overcome limited bandwidth of communication [35–42]. Many

control systems have multiple inputs and multiple outputs (MIMO) and the number of inputs

and outputs increases as distributed systems emerge. To detect each input change and take

control action on each output, enormous computing power and communication are required.

To minimize the use of limited resources for computation and communication, event-driven

sampling has been introduced. The system with the event-driven sampling takes a new input

only when the input changes from its previous state by certain amount, i.e., a new event.

The event-driven sampling can prevent the system from conveying and processing redundant

information. However, most works employed the clock-based event detection. The input is

sampled every clock period, then the systems decide whether the input is considered to be a

new event and transmitted to the controller. In other words, they still rely on clock signal.

Recently, fully event-driven sampling has been applying to circuit designs [28–33]. Unlike

clock-based event-driven sampling, a continuous-time (CT) analog-to-digital converter does

not rely on clock for sampling operation. It monitors the analog input continuously and

detects a new event immediately when the input changes by certain amount. Therefore, the

sampling operation is dependent on signal rather than clock. Also, an entire digital signal

processing (DSP) system has been proposed based on the fully event-driven sampling. To

accommodate varying sampling period, the succeeding computation part also operates in a

continuous-time manner. Delay cells are implemented to replace flipflops in a digital filter.

In [34], CT DSP is used to implement an algorithm for DC-DC converter, so it can achieve

6

fast voltage recovery.

1.5 Event-driven digital LDO

The major problem of digital LDO designs is the necessity of large output capacitor.

As described in the previous section, time-driven (synchronous) digital LDO designs have

the inherent trade-off between transient performance and power consumption. For high

power efficiency, time-driven designs must employ large output capacitor to compensate

fast load current change without using high speed clock. Large output capacitors are usually

implemented off chip, so the increasing number of pins and area is inevitable. It is particularly

undesirable when a system needs multiple LDOs to implement a number of power domains.

Figure 1.2: Latency comparison between (a) time-driven and (b) event-driven control

To overcome drawbacks of conventional digital LDO designs, event-driven control is intro-

duced to the digital LDO designs. Our event-driven approach allows a controller to update

its output only when the LDO output deviates considerably from VSP , i.e., a new event.

This architecture can achieve very short latency without high-frequency clock. As shown in

Figure 1.2, a time-driven system triggers its controller at every clock edge. Thus, if load

current changes just after a clock edge, the systems must wait for the next clock edge to

7

catch the change and start regulation process. Therefore, the worst-case latency is a single

clock period. Unlike time-driven systems, event-driven systems can immediately respond

to the load change and take control action upon a new error. This significantly improves

transient performance.

Figure 1.3: Step response and triggering behavior comparison between (a) time-driven and(b) event-driven control

In addition, the event-driven approach can eliminate unnecessary operations, i.e., up-

dating the output of the controller in the steady state. Once LDO output is settled to the

set-point voltage, the system with the event-driven approach observes no new event and thus

stops triggering its controller. Figure 1.3 shows the exemplary step responses of time-driven

and event-driven systems. A time-driven system continues to update its controller output

even in the steady state. Not only the redundant update does consume power, but it also

results in ripples on the output. Event-driven systems, however, stop updating its output

after the output is settled to the set-point and consume only quiescent power (i.e., digital

circuit leakage and bias current of comparators). Therefore, the transient performance is not

compromised by low power consumption.

In this thesis, we will demonstrate several prototypes of our event-driven digital LDO

8

designs. In chapter 2, we show our first digital LDO design based on event-driven PI con-

troller [16]. Then chapter 3 demonstrates the event-driven LDO design based on parallelized

PI controller [18] to further reduce control loop latency and output capacitor size. In chapter

4, we show the event-driven LDO design with self-triggering control and initialization [20]

for settling time reduction and high current density. Lastly, I will summarize and conclude

this thesis.

9

Chapter 2

Event-driven LDO based on binary PI

control

2.1 Motivation

The key overhead of the existing LDO design is the large off-chip output capacitor (COUT )

for compensating large/fast change in load current (ILOAD). Miniaturizing and thus inte-

grating COUT on a chip is highly desirable and theoretically possible by shortening control

loop latency. This can be achieved by employing higher sampling frequency (FCLK) in

synchronous time-driven digital LDO [13] and a high-speed amplifier in analog LDO [3].

However, large power consumption and the resulting low current efficiency are often in-

evitable. In this work, therefore, we aim to break this trade-off between passive size and

efficiency by introducing an event-driven (ED) control scheme. We design the level-crossing

event detector and the ED PI controller for short latency. The power dissipation is kept

small since no event occurs in the steady states. We prototype a 400µA class LDO with

10

typical VIN=0.5V and VOUT=0.45V in a 65nm based on the proposed technique, achieving

a small voltage droop (VDROOP ) of 40mV (¡9% of set-point voltage [VSP] of 450mV) with

an on-chip integrated COUT of 0.4nF and the peak current efficiency of 96.3%.

2.2 Overall architecture

Figure 2.1: Overall architecture of the proposed LDO design

The architecture of the proposed LDO is shown in Fig. Figure 2.1. It consists of a

continuous-time (CT) ADC with refresh circuits, a trigger generator, a PI controller, and

power transistors. The ADC captures the output voltage (VOUT ) when it crosses one of

seven reference voltage levels (VREF [6:0]), then generate LV signal. Upon detecting LV

signal change, the trigger generator produces triggers for the following proportional-integral

(PI) controller. It also codes the time interval between two events into a digital value using

a free-running oscillator (FRO) and sends it to the PI controller. Then, the PI controller

computes P and I part results and produces 10-bit output. This output turns on and off

power transistors so that they can supply the right amount of current to a load.

11

2.3 Continuous-time ADC

Figure 2.2: Continuous-time ADC structure

Figure 2.2 shows the schematics of our continuous-time FLASH ADC. It consists of seven

inverter-based comparators [31]. Each comparator has two inputs and one output. The two

inputs take one of the reference voltages (VREF [N]) and the output voltage of LDO (VOUT ).

The output of each comparator produces LV[N]. The seven reference voltages are equally

spaced by the voltage resolution (VRES), typically 10mV in this design. Whenever VOUT

crosses one of the reference voltages, the ADC updates its 7-bit thermometer-coded output.

The ADC operates via two phases: (i) refresh and (ii) conversion, coordinated by ADC

REFRESH signal to implement the correlated double sampling method [43]. In the refresh

phase, the comparator performs the double sampling operation to compensate process vari-

ation and ensuring high gain. Specifically, the input and output of the first inverter in a

comparator are shorted and this makes the input and output to be at the mid-point of volt-

age transfer curve (VTC, ∼ 1/2 · VDD). The input capacitor of a comparator (CIN) retains

the voltage difference between this mid-point of VTC and the reference voltage. The voltage

difference represents the input offset, which in the conversion phase will be automatically

subtracted from the input. Note that the CIN will lose some of the voltage difference via

12

gate leakage. Therefore, it is designed to periodically perform the refresh phase. Also, we

interleave the refresh phases of the seven comparators over time so that while one of them

is in the refresh phase all the other six are still in the conversion phase.

Note that a comparator in a refresh phase can produce incorrect output. Thus, the

refresh-incurred worst-case error can happen when a comparator whose reference voltage is

the farthest from the set-point is being refreshed. To avoid this problem, we design the

error encoder to ignore isolated 1 or 0 and to find the error value based on more than two

consecutive 0’s and 1’s. We also design the comparator in a refresh phase produce a value so

as to make the error larger than the actual error. With these schemes, the controller receives

mostly-correct and conservative error values to regulate VOUT even in the refresh phase.

In the conversion phase, the input and output of the first inverter of each comparator are

disconnected, maKIng it as an amplifier. Then, we connect the input of every comparator

to VOUT , the output voltage of LDO, through CIN . Now if VOUT becomes larger than the

VREF [N], the N-th comparator amplifies the difference (VOUT -VREF [N]) to the logic high level

through its four inverters. Otherwise, the comparators produce the logic low level.

2.4 Trigger generator

Figure 2.3: Trigger generator

13

Figure 2.3 shows the schematics of trigger generator. It takes the ADC output and

produces five digital signals for the following event-driven PI controller. By comparing the

ADC outputs via an XOR-based change detector, the trigger generator produces a pulse,

called P TRIG. The rising edge of P TRIG has the P part of the PI controller to start

to compute. Similarly, it produces a pulse called I TRIG. As the name suggests, it is for

the I part of the controller. I TRIG generally follows P TRIG but if several consecutive

events happen in a short period of time, I TRIG produces only one pulse. This design is

for accommodating the longer circuit delay of the I part computation than the P part as

the I part involves complex computation such as multiplication. The minimum time interval

of two consecutive I TRIG pulses is, therefore, set to the critical path delay of the I part

computation. Figure 2.4 shows the implementation of the pulse blocker to generate I TRIG.

It asserts I TRIG at the rising edge of P TRIG, then it asynchronously resets through the

self-resetting loop consisting of the odd number of inverters. The reset is then released again

through the loop. The delay of the inverters is matched to half of the I part computation

delay so as to produce only one I TRIG pulse at the first P TRIG rising edge even if several

other consecutive P TRIGs arrive in a short amount of time. The trigger generator also

Figure 2.4: Pulse blocker

produces 4-bit CNT signal by measuring the time interval between two successive events

using the interval counter. The CNT signal is synchronized at the rising edge of I TRIG as

14

it is used for the I-part computation in the controller. To count a new time interval, the

interval counter is reset by P TRIG so I part changes its output conservatively with smaller

CNT value. Similarly, the trigger generator produces 1-bit TIME OUT for handling the

sticking problem (A for more details).

Finally, the trigger generator produces 5-bit ERROR signal by translating the thermome

ter-code LV into binary values using the error encoder. The error encoder is designed to

be configurable to support more than the standard thermometer to binary translation. For

example, we can set the ERROR values growing super-linearly with the LV values. Such

non-uniform translation can improve transient response to large load current change (see

Sec. V.B for details).

Figure 2.5: Timing diagram of regulation process

Figure 2.5 shows the timing diagram of the trigger generator. As the LDO output voltage

(VOUT ) crosses one of the reference voltages (VREF [N]), the ADC produces a new LV value,

which generates P TRIG. It also produces I TRIG based on P TRIG while ignoring P TRIG

15

pulses that are too close to the previous pulse. Also, the new LV value becomes the ERROR

in the binary format via the error encoder. The interval counter produces the CNT value at

the I TRIG rising edge, and then reset to zero at the delayed P TRIG signal.

2.5 Binary PI controller

Only at the occurrence of P TRIG and I TRIG, the ED PI controller takes the ERROR

and the CNT and produces UB to modulate the power transistors of the LDO (Figure 2.1

bottom right). The P-part is implemented with a shifter for short latency as this latency

mainly dictates VDROOP . The I-part, whose primary function is to eliminate steady state

error, performs Euler backward method, i.e., CNT∗ERROR, using a general 9-bit multiplier.

The integrating gain (KI) is later multiplied, again by using a shifter. Still, the delay of the

I-part is slower and the use of the fast trigger (P TRIG) can cause data corruption; thus it

performs computation only with I TRIG. The LSB of I-part is smaller than that of P-part.

Hence, only the most significant 10 bits for from the addition of P-part and I-part is used

for generating UB.

In the controller design, we mainly consider the PID control law and its variants for its

high performance and simple implementation. The PID control law consists of proportional

(P), integration (I), and differential (D) parts. Each part has its own gain, KP , KI , and KD,

which will be multiplied for output generation. We can use one of the parts, combine two

of them or all. However, we decide not to use the D control since the division operation can

significantly increase complexity. Therefore, we mainly compare three control laws, namely,

P, I, and PI, in our controller design.

16

Figure 2.6: Transient response comparison among P-only, I-only and PI controllers

P-only control is similar to what the classical analog LDO is based on. The output of

the controller is proportional to the error. The advantage of P controller is its fast transient

response (Figure 2.6). In the digital LDO design, however, insufficient gain can cause a

considerable amount of steady-state error. Insufficient DAC resolution can also cause limit-

cycle oscillation in the steady state. I-only control can reduce the steady-state error down to

less than one LSB of the ADC resolution. However, its regulation speed is slow, particularly

much slower than P-only control in event-driven control systems. This is because, in event-

driven control systems, the rate of change of the plant state (VOUT in our LDO design)

determines the rate of new event generation, and then the rate of new event generation

determines control speed. This self-loop in the event-driven control system process makes

I-only control slower than P-only control.

Therefore, we design the event-driven PI controller since it can take advantages of both P

and I control, namely fast regulation and less than one LSB steady-state error (Figure 2.6).

Figure 2.7 shows the schematics of the controller. It takes the outputs of the trigger gen-

erator, computes the P and I part results, sums them, and finally produces 10-bit unsigned

binary output U for turning-on/off power transistors. The P computation requires to mul-

17

Figure 2.7: Binary digital PI controller

tiply ERROR and KP , as shown below:

P (k) = KP × e(k) (1)

, where P(k) is the output of P part at the k-th event and e(k) is the ERROR value at the

k-th event. The I computation is the accumulation of multiplications of ERROR, CNT, and

KI , as defined below:

I(k) =k−1∑i=0

[KI × e(i) × CNT (i)] (2)

, where I(k) is the state of I-part (accumulation result), e(i) is the error of i-th event (samples),

and CNT(i) is the i-th time interval from the trigger generator. Figure 2.8 graphically shows

the P and I part computations. The P part output is a function of the error magnitude at the

k-th event. The I part output implements forward Euler method, i.e., it accumulates the area

of the rectangle determined by CNT(k-1) and e(k-1) at the k-th event. We use the shifters to

implement the multiplication of each gain (KP , KI) with e(i) for short computation latency.

We use a 9-bit general-purpose multiplier for the multiplication of e(i) with CNT(i). Lastly,

18

the output of the controller, U(k), at the k-th event is determined by the sum of P(k) and

I(k) as below.

U(k) = P (k) + I(k) (3)

Figure 2.8: Illustration of PI computation

2.6 Challenges of Event-driven systems

Event-driven control systems have several unique characteristics that time-driven or

continuous-time control systems do not have. This is because in the event-driven control, the

regulation of output is initiated only by the change of output itself. This can cause several

undesirable behaviors, as well, which we try to compensate in our proposed LDO design.

2.6.1 Sticking Problem

Sticking problem is a phenomenon that a plant state is stuck to a value that is not

a set-point. Figure 2.9 shows exemplary waveforms of which our LDO experiences such

19

Figure 2.9: Illustration of sticking problem

Sticking problem. During regulation, the output voltage (VOUT ) can change slowly between

two reference voltages (e.g., VREF [k] and VREF [k+1]) for some reason, and this can limit new

trigger generation. Without triggers, the controller cannot update its output and thus plant

states (VOUT ) cannot change further. The lack of change in VOUT prevents new triggers from

being generated. Eventually, this forces VOUT to settle at an undesired level.

To resolve this sticking problem, we design our PI controller to generate a compulsive

trigger if VOUT is stuck at the non-zero error position for more than a predefined amount

of time. Once generated, this compulsive trigger can update controller output, and it helps

VOUT to cross one of the reference voltages, generating new triggers and thus reactivating

the normal regulation operation. Figure 2.10 shows our proposed PI controller with the

aforementioned countermeasure for the sticking problem. Specifically, the sticking detector

determines if the current error is zero or not. If not, the sticking detector enables the sticking

counter (in the trigger generator), and if the sticking counter reaches a predefined threshold,

it asserts HIT, which initiates a new trigger generation.

20

Figure 2.10: Modified trigger generator with a sticking counter

2.6.2 Limit cycle

Figure 2.11: Illustration of limit cycle

Limit cycle is a phenomenon that the state of a plant oscillates near a set-point in the

steady state. Figure 2.11 shows the exemplary waveforms of limit cycle occurring in the

proposed digital LDO. Although the amplitude of oscillation is not significant, it causes

continuous event generation and thus overshadows one of the key benefits of event-driven

control systems: no control operation in the steady state. This unnecessarily increases power

dissipation. One of the main causes of the limit cycle is insufficient resolution of DAC. In our

21

Figure 2.12: Modified PI controller with adaptive gain control

proposed LDO system, the DAC resolution is determined by the sizes of power transistors

and gains of P and I control law computation (i.e., KP , KI). To avoid limit cycle, therefore,

we use fine-grained sizes of power transistors. Furthermore, as shown in Figure 2.12, we

employ an adaptive gain scheme for the I part computation. Specifically, the controller has

two sets of registers to store two successive error values. Then, the limit cycle detector

determines if one of the two successive errors is zero and the other is ±LSB. If this condition

is met, the controller reduces KI to alleviate the limit cycle.

2.7 Stability analysis

Stability analysis is critical to any control systems. However, it is not straightforward

to use some of the conventional analysis techniques to our LDO design since event-driven

control systems have a sampling rate that is not constant. A large body of the works have

analyzed the stability of non-uniform sampling systems [37, 39–42]. In this work, we devise

a stability analysis framework by using the state space model that describes the transient

22

behavior of the LDO system between two sampling moments. With this model, we analyze

the stability of our LDO by considering all the possible sampling intervals.

In our LDO design, we model the plant by using supplying current of power transistors

(IPWR), load current (ILOAD), and output capacitor (COUT ). One of the states of the plant

part is defined as VOUT at the current sampling moment (VOUT (k)) and that at the next

sampling moment (VOUT (k+1)), which is a function of COUT , the time interval between

current and the next events (TEV ), and the difference between load current and supply

current (IPWR-ILOAD). IPWR can be further defined as the product of the controller output

(U) and a unit current (IU) of the power transistor array. VOUT (k+1) can be derived as:

VOUT (k + 1) = VOUT (k) +U(k) · IU − ILOAD

COUT

· TEV (k) (4)

To simplify the analysis we normalize VOUT to the ADC resolution (VRES), as shown below:

e(k) =VREF − VOUT (k)

VRES

(5)

By combining Equation (4) and Equation (5), we can derive e(k+1) as below:

e(k + 1) = e(k) − U(k) · IU − ILOAD

COUT · VRES

· TEV (k) (6)

The remaining part of the LDO, i.e., the controller, can be modeled based on Equation (2)

and Equation (3). We reformulate Equation (2) in a recursive form and also Equation (3)

as a function of e(k) and I(k). The output of I part, another state, at the (k+1)-th sampling

23

time then can be derived as:

I(k + 1) = I(k) +KI · e(k) · CNT (k) (7)

And the output of the controller at the k-th sampling moment can be found as:

U(k) = KP · e(k) + I(k) (8)

Using Equation (8) we can reformulate Equation (6) into:

e(k + 1) = (1 − KP · TEV (k) · IUCOUT · VRES

)e(k) − TEV (k) · IUCOUT · VRES

I(k) +TEV (k)

COUT · VRES

ILOAD (9)

Finally, we can model the LDO with two states at the k-th event, namely e(k) and I(k),

based on Equation (7) and Equation (9). Those equations can be formulated into a matrix

form as below:

e(k + 1)

I(k + 1)

=

1 − KP ·TEV (k)·IUCOUT ·VRES

− TEV (k)·IUCOUT ·VRES

KITEV (k)TFRO

1

e(k)

I(k)

+

TEV (k)COUT ·VRES

0

ILOAD (10)

The stability analysis of the state space model is done by determining the eigenvalues in its

matrix equation, Equation (10) in our case. Figure 2.13 shows the eigenvalues of the proposed

LDO system as a function of various design parameters. In our systems, TEV is a variable

and thus we plot eigenvalue pairs across TEV s. A key factor to consider is that TEV is the

multiplication of CNT with TFRO (discretized) and is bounded by the predefined threshold

of the sticking counter. This allows us to consider only a limited number of TEV s, and thus

24

simplifies the stability analysis. If eigenvalues are inside a unit circle, the corresponding

system is considered stable. As shown in Equation (10), however, the amount of impact

of different sampling time can significantly be varying according to the values of design

parameters. Each parameter often makes a non-linear impact on a pair of eigenvalues. Thus,

we inspect all the possible design parameters to ensure the stability of the LDO (Figure 2.13).

Figure 2.13: Eigenvalue plot for stability analysis across different parameters

It is shown that our choice of design parameters (KP=64, KI=0.5, COUT=400pF, TFRO

=5ns, VRES=10mV) makes the LDO system stable. Furthermore, it is worthwhile to note

that the stability analysis that we devised is the necessary condition for system’s stability. In

other words, even if the systems have eigenvalues outside of the unit circle for some sampling

25

moments, we cannot rule out the possibility that the systems could be back to stable. This is

because each eigenvalue represents only the behavior between two sampling moments. Even

if systems cannot regulate its state across several sampling moments, e.g., due to large TEV

values, the systems could recover to a stable state with e.g., several successive small TEV

values. Our proposed stability analysis, therefore, confirms the stability in the worst case.

2.8 Measurement results

The test chips for the proposed event-driven LDO system have been prototyped in a 65nm

General-Purpose CMOS process. Figure 2.14 shows the micrograph of the test chip. The

integrated output capacitor and the input capacitors of ADC are implemented with metal

oxide silicon capacitors (MOSCAP) and metal-insulator-metal capacitors (MIMCAP). The

active area of LDO system without the output capacitor is 0.029mm2.

Figure 2.14: Chip micrograph

We investigate the performance of our proposed LDO system across different environ-

ments. Figure 2.15 shows the transient response to a sudden load current change (200µA) at

26

0.1ns edge time (TEDGE) and the corresponding droop voltage (VDROOP ) and settling time

(TS). The ADC resolution (VRES) is set to 10mV. As shown in Figure 2.16, we measure the

Figure 2.15: Transient snapshot of load regulation

impact of KP and KI on VDROOP and TS. Increasing KP can significantly reduce VDROOP .

This is because large KP helps IPWR to quickly follow ILOAD upon the first event, and thus

prevents further VOUT droop. After that, the I part removes the steady state error over

time. On the other hand, KI has a strong impact on TS. As error becomes smaller during

Figure 2.16: Impact of gains (KP , KI) on (a) VDROOP , (b) TS

regulation, the I part gradually takes over the current produced by the P part. At the end

27

of regulation, the P part does not contribute to IPWR. Therefore, the I part needs to supply

IPWR upon all possible load current. Increasing KI speeds up the operation of the I control

by increasing the amount of I part output change at each event and thus reducing TS. Note

that increasing KP also helps to reduce TS since it reduces VDROOP and the I part needs

to correct a less amount of VOUT deviation. We also investigate the impact of several other

Figure 2.17: Impact of (a) TFRO, (b) VREF , (c) COUT and (d) ∆ILOAD on performance

design parameters. First of all, we modulate the period of free-running oscillator (TFRO)

and measure quiescent current (IQ) and TS (Figure 2.17 (a)). Using small TFRO increases

the I part computation result, and this is equivalent to increasing KI yet without causing

limit cycle. However, small TFRO increases dynamic power dissipation of the ring oscillator.

28

In our design, we use 5ns TFRO as a sweet spot for this trade-off.

We also investigate the impact of VRES. VRES has a strong impact on the number of events

for the same amount of VOUT change. Also, VRES inherently involves the control loop gain

since the ADC gain, defined as analog input voltage to digital output code ratio, is inversely

proportional to VRES. Therefore, as shown in Figure 2.17 (b), small VRES is beneficial

to VDROOP and TS. However, implementing small VRES requires more comparators in the

FLASH ADC architecture for the same input range. In our design, we use 10mV VREF as a

sweet spot for this trade-off.

We also investigate the impact of the output capacitor size (COUT ). The LDO transient

performance is a function of control loop speed and the rate of VOUT change. The rate

of VOUT change is determined by the load current change (∆ILOAD), and COUT . While

increasing COUT improves VDROOP for the same load current change (Figure 2.17 (c)), it is

undesirable for on-chip integration. Increasing COUT also increases TS since it takes a longer

time to charge larger COUT . In this work, we set COUT to 400 pF, the smallest value that

has VDROOP less than 10% of VOUT at the ±400µA ILOAD change. Figure 2.17 (d) shows

the performance across different load current changes. As expected, large ILOAD change

increases VDROOP , and thus TS. To support a larger ILOAD change for the target ∆VOUT ,

we need to either increase output capacitor size or speed up the control loop latency, which

typically increases power consumption and thereby degrades current efficiency. We also

conduct an experiment of the adaptive gain scheme. As discussed in Sec. III.B, the error

encoder in the proposed LDO is configurable on the translation of the thermometer-coded

LV into the binary ERROR signal. Figure 2.18 (a) shows four translation configurations for

the evenly assigned VREF s (VRES = 10mV). The Error3 configuration, for example, has a

29

Figure 2.18: (a) Different error assignment and its impact on transient performance ((b)VDROOP , (c) TS

non-uniform translation scheme where ERROR value increases super-linearly with LV ones.

This configuration is equivalent to increasing KP and KI only for larger VOUT error. For the

precise VOUT regulation, we still keep the linear translation for the error around a set-point.

As shown in Figure 2.18 (b) and (c), the adaptive gain scheme improves VDROOP and TS.

While we design our LDO mainly for 0.5V input voltage (VIN) with 50mV drop-out

voltage, it functions across 0.5-1V VIN with the same drop-out voltage. As shown in Fig.

21 (a), it can support up to 400µA at 0.5V VIN to 3.5mA at 1V VIN (about 50x range for

ILOAD). The maximum load current is limited by the control loop latency at low VINs and

by the test setup (the size of load transistor array in the test chips) at high VINs.

We also measure current efficiency across VINs. The peak current efficiency at 0.5V is

96.3% (Fig. 21 (b)). The peak current efficiency is more than 90% across all the VINs.

The peak current efficiency tends to decrease as VIN increases since the continuous-time

ADC operates in the super-threshold region and thus consume more crowbar (short-circuit)

current.

We evaluate the power supply rejection (PSR) of our LDO. For DC-like VIN change from

0.48 to 0.6V, the LDO can regulate VOUT error less than one LSB, which is equivalent to

30

28dB. For VIN change of 10kHz and 10MHz, the LDO exhibits the PSR of 20dB and 5.2dB,

respectively. The 50mV dropout voltage has the power transistors of digital LDOs operate

in the deep triode region, which can facilitate to pass VIN change onto VOUT . Our LDO has

tens of nanoseconds of control loop latency, and thus can well regulate slow VIN change. But

when the time constant of VIN change is comparable to the control loop latency it suffers

from low PSR. To improve it, the active and passive techniques (e.g., [12]) are desirable.

Table 2.1: Comparison table

Finally, we compare our proposed LDO with the state-of-the-art designs based on time-

driven control systems that support 0.5V VIN (Table 2.1). To compare the trade-off between

passive size and quiescent power dissipation, we define the first figure-of-merit (FoM):

FOM [pF ] = IQ · VDROOP,MAX

ILOAD · VOUT

· COUT (11)

31

The first term represents quiescent power dissipation, the second term represents the load

regulation performance normalized to ILOAD and VOUT , and the last term is passive size. As

shown in Table I, our proposed LDO achieves 2.7-108x improvement over two previous works

[10,11] which can support 0.5V VIN operation in this FoM. Note that FoM is a function of

VIN and thus it is non-trivial to compare designs of different VINs. Therefore, we compare

our design to the design having the same VIN of 0.5V.

32

Chapter 3

Event-driven LDO based on

parallelized controller

3.1 Motivation

Our previous work ( [16]) has employed an event-driven (ED) control scheme to alleviate

COUT requirement, demonstrating a 400µA-class digital LDO with a COUT of 400pF [18].

The ED scheme is promising, but it is still desirable to develop an LDO which can support

larger ILOAD with a smaller COUT . This is indeed a daunting challenge since substantial

reduction in feedback latency (TLAT ) is necessary to retain the same level of output voltage

change (∆VOUT ) with a smaller COUT . In this work, to shorten latency, we propose to infuse

fine-grained parallelism to ED control systems and develop a fully-integrated digital LDO.

The prototyped LDO can support 1.44mA ILOAD at 0.5V VIN , 0.45V VSP , and 99.2% peak

current efficiency. The LDO shows less than 34mV (7.6%) ∆VOUT with an only 0.1nF COUT

when ∆ILOAD is ±1.44mA.

33


Figure 3.1: Overall architecture of the proposed LDO

Figure 3.1 shows the architecture of the proposed LDO. It consists of a level-crossing ADC

with a refresh circuitry (similar to the ADC in [16]), a pulse generator, and an ED controller

including parallel proportional (P) and integration (I) parts. The ADC asynchronously

detects the change in output voltage (VOUT ) and produces the error signal called LV, which

represents VOUT -VSP in a 7-bit thermometer code. Upon the change in LV, i.e., a new event,

the pulse generator triggers proportional (P) and integration (I) parts. The P part multiplies

the LV by a proportional gain (KP ) and the I part integrates the LV multiplied by an integral

gain (KI) over time until error is gone. Each output of the P and I parts turns on and off

independently its own power transistors to regulate VOUT .

In LDO designs, it is critical to shorten TLAT . Large TLAT causes the controller to hold its

previous value for a while after large load current change. Before the controller is activated

upon a new load current change, VOUT changes at the maximum rate because the difference

34

Figure 3.2: Impact of control latency (TLAT ) on maximum voltage change (∆VOUT )

between the load current and the supplied current is largest during its transient response.

The first output voltage change (∆VOUT ) is roughly proportional to ∆ILOAD · TLAT/COUT

and this contributes to the maximum voltage change (∆VOUT ) the most. Note that the

controller requires further updates to recover VOUT after the first drop. Thus, it is necessary

to minimize TLAT for ∆VOUT reduction (Figure 3.2), so we can trade it off for smaller COUT .

3.3 Separate PI controller

To shorten TLAT , first we parallelize the P and I parts. In PI controllers, the P part

dominantly regulates VOUT first. In other words, the P part mainly determines ∆VOUT . On

the other hands, the I part is zero steady-state error to finalize regulation process. Therefore,

to reduce COUT , it is more critical to shorten the P part latency. The key bottleneck for

the latency in the prior art [16] is a digital adder which adds up the P and I part results.

It makes the P part output to wait until the I part finishes computation, which takes long

time due to its complex operation such as multiplication and accumulation. As a results,

the adder prevents the P part from applying its output to power transistors. To eliminate

35

Figure 3.3: Comparison between (a) conventional and (b) parallel PI controllers

this holdup, we replace the adder and one set of power transistors with two sets of power

transistors controlled by the P and I parts in parallel. The addition of the P and I part

outputs is performed in the current domain (Figure 3.3). Our simulations confirm that this

parallelization shortening P part latency by 72%. In addition, the P part multiplies the LV

and KP using a bit shifter to further shorten latency. Hence, the P part can solely start to

regulate VOUT as soon as possible.

3.4 P part structure

This parallelism of the PI controller necessitates the use of NMOS power transistors

for the P part. The P part may produce negative results for overshoots. However, the

PMOS-only power transistors cannot utilize negative value since they can only supply current

(cannot sink current). This could lead the I part to solely handle overshoots, resulting in

sub-optimal regulation. To address this, we propose the P part utilizing both PMOS and

36

Figure 3.4: P part structure with PMOS and NMOS power tranasistors

NMOS power transistors (Figure 3.4). Simulations show that this reduces ∆VOUT by 27%

for -1.4mA ∆ILOAD only with 0.36% area overhead.

3.5 I part structure

We further optimize the I part using parallel shift-registers. Although having a less

impact on COUT minimization, minimizing the I part latency is still important as it affects

settling time (TS), a critical metric to determine the time constant of the dynamic voltage

scaling (DVS) technique. Implementing the I part with regular adders and multipliers,

however, causes long latency as well as computation overhead. Instead, we propose parallel

implementation of the pulse generator and I part (Figure 3.5).

The I part regulation process includes a pulse generator, a pulse shifter, four pairs of

pulse routing units (PRU) and 7-b shift-registers (SR), and octal-sized power transistor

arrays. The pulse generator (Figure 3.6) translates the LV from the thermometer to one-

37

Figure 3.5: Parallelized pulse generator and I part with parallel shift-registers

hot code, which feeds one of the five error magnitude pulse generators (EMPG) to produce

MPULSEs (Magnitude-Pulse). The bit location of MPULSE represents error magnitude.

Also, the sign of error (SIGN) is determined by LV[3]. Also, PPULSE is produced by OR-

ing MPULSEs including zero-magnitude. Note that a sticking counter is employed to force

a pulse if VOUT does not change for a specific time.

Then, instead of multiplication, the position of incomping pulse is shifted based on the

time interval between two events measured by a counter (CNT) and the integration part

gain (KI) in the pulse shifter (Figure 3.7). Each position of pulses means binary number. In

the beginning, zero padding takes place to implement adaptive gain. Then, the MPULSE

is shifted by the most significant 1’s position of CNT, i.e., CNT=1100 shifts the MPULSE

by 3. In this way, the shifter approximates the multiplication of ERROR and CNT. Again,

the shifted pulse (pulse cnt) is shifted by the integration gain (KI). To limit the number of

shift-reigsters, the 13 resulting positions converge into four IPULSEs by OR-ing 3 positions.

38

Figure 3.6: Pulse generator

Figure 3.7: Pulse shifter structure

The actual I part consists of four pairs of pulse routing units (PRU) (Figure 3.8) and 7-b

shift-registers. Each shift-register drives a power transistor array sized in the power of 8.

This configuration produces the same current by the bit within the same shift-register, but

the different current across different shift-registers. For example, 1 in the third shift-register

can produces 64 times larger current than 1 in the first shift-register. Also, a PRU can

quickly detect under/overflow by checking the LSB and MSB of the SR in its pair. Upon the

detection, the PRU can route the IPULSE to the adjacent PRU to handle under/overflow

39

Figure 3.8: Pulse routing unit

Figure 3.9: Pulse routing unit operation

(Figure 3.9).

This structure can significantly improve accumulation speed over binary digital controller

[16] or single shift register [14]. The binary controller has large timing constraint due to

its complex arithmetic, so it cannot handle fast successive inputs. However, this parallel

structure can take fast inputs thanks to fast operation of shift-registers. Also, while the

single shift-register can change its output by only 1, this structure can update the stored

values adaptively (not only by 1) and add up the partial results in the current domain using

power transistors, all in parallel. Hence, it supports fine-grained control of output current

40

with fast speed.

3.6 Measurement results


Figure 3.11: Transient snapshot of load regulation

We prototype this digital LDO in 65nm technology(Figure 3.10. We measure transient

performance such as ∆VOUT and TS as shown in Figure 3.11. The CT ADC here uses

the resolution (VRES) of 10mV and thus the VSP < VOUT < VSP + 10mV is considered to

be zero error, where VSP is our set-point voltage. For the ILOAD change of +1.4mA, our

LDO exhibits ∆VOUT of 24.8mV (5.5%) and TS of 11.2mus (118 fan-out-of-4 [FO4] delays

41

at VDD=0.45V). For the ILOAD change of -1.4mA, ∆VOUT is only 8mV and TS is reduced

to 1.41µs (15 FO4 delays). We investigate the impacts of KP and KI on ∆VOUT , TS,

Figure 3.12: Impact of gains (KP , KI) on (a) ∆VOUT , (b) TS, and (c) NEV

Figure 3.13: (a) Impact of NEV and (b) optimal gain selection

and the number of events (NEV ) (Figure 3.12). As mentioned in previous section, the P

part dominates regulation performance. Therefore, large KP can reduce ∆VOUT and TS

as long as the system is stable. However, large KP can increase NEV since the transient

response becomes more oscillatory, crossing reference voltages many times. On the other

hand, large KI can reduce TS and NEV as the controller output change becomes large at

each event. Note that it may seem that arbitrarily large KI is beneficial in every aspect.

42

However, it increases the unit amount of current the controller can change, so VOUT may not

converge. It is critical to reduce the number of event during transient response. NEV has

Figure 3.14: (a) Load regulation and (b) current efficiency across different VIN

a strong impact on the power dissipation of control systems since the update of controller

consumes dynamic power at each event. Figure 3.13 (a) shows the portion of dynamic power

consumption as compared to static power consumption. Assuming load current changes every

1µs, the dynamic power becomes comparable to static power as NEV increases to hundreds.

High NEV may overshadow the advantage of event-driven control by working similar time-

driven system: unnecessary triggering. Thus, it is important to minimize NEV as long as

satisfying ∆VOUT requirement by using an optimal KP , which has trade-off between transient

performance and the number of events; for example in Figure 3.13 (b), for ∆ILOAD=1.2mA,

KP=1 can be optimal to balance ∆VOUT ( 50mV) and NEV (29.9). When the load current

changes by 1.2mA every 1mus, our LDO still consumes comparably low power (14.8muA).

This is because the ADC takes 45% of the total power dissipation (simulation).

We also investigate operation across different VINs with 50mV drop-out (Figure 3.14).

The proposed LDO can support 0.45-1V VIN range and maximum ILOAD is 3.4mA. We also

43

Figure 3.15: Impact of resolution on line regulation

Figure 3.16: Impact of dropout on load regulation

measure current efficiency of the proposed LDO. It is confirmed the peak efficiency of 99.2%

at 0.5V VIN , showing over 95% of peak current efficiency across different VIN . We measure

DC line regulation: When VIN changes from 0.5 to 0.67V with fixed 0.45V VSP , the LDO

can regulate VOUT with the error less than a VRES of 10mV. We sweep VRES from 6mV to

15mV, confirming the errors are still less than the VRESs (Figure 3.15). Similarly, we verify

the line regulation capability across different drop-outs from 30mV to 100mV and different

VINs from 0.45 to 1V. The measurements show the regulation ability with errors less than

44

VRES (Figure 3.16).


Finally, we compare our proposed LDO with recent LDOs supporting 0.5V VIN . Our

proposed LDO achieves 7.6% ∆VOUT with a 100pF on-chip integrated COUT while supporting

1.44mA ILOAD. It consumes 12.2µA IQ, making the peak efficiency of 99.2%. Based on two

FOMs [14,16], our proposed LDO outperforms the two recent designs [14, 16] by >17X and

>63X, respectively.

45

Chapter 4

Event-driven LDO with self-triggering

control and initialization

4.1 Motivation

Recent works [16, 18] demonstrated LDOs based on Event-Driven (ED) control. Unlike

Time-Driven (TD) control, ED control can operate only upon a new event without clock

(Figure 4.1 (a), (b)). This can largely shorten the latency to compensate the voltage droop

(∆VOUT ) caused by a sudden load current (ILOAD) change, defined as the first compensation

latency. This in turn allows aggressive scaling of the output capacitor (COUT ), enabling its

on-chip integration. Also, the absence of triggering in the steady state makes event-driven

LDOs consume only small leakage.

However, these benefits are overshadowed by two main drawbacks of the conventional

event-driven LDOs: explicit-time coding and sticking problem(Figure 4.1 (b)). To calculate

integrals of errors, the existing event-driven LDOs need to measure the non-equidistant time

46

Figure 4.1: Control comparison

interval between every two successive events by a counter and multiply error with the time

interval by a binary multiplier or a shifter [16, 18]. The complex hardware increases delay

and area. In addition, in the event-driven feedback control systems, the dynamics of plant’s

state, i.e., the output voltage [VOUT ] in the case of LDOs, determines the rate of new event

generation. As the state is coming close to the set-point and error magnitude is decreasing,

the feedback control gradually becomes weaker. This is called sticking problem which often

has the VOUT stuck to or slowly moving near an undesired value in the event-driven LDOs.

Thus, additional hardware (e.g., a watchdog counter [16,18]) is unavoidable to mitigate this

problem, which again degrades area, power, and settling time.

In this work, we aim to address these drawbacks and propose a new event-driven control

based on self-triggering (Figure 4.1 (c)). This scheme keeps generating pulses (IPULSE)

equidistantly and triggering the integration part of the control (I-part) to update its output

unless VOUT is settled to VSP . Equidistant IPULSE eliminates the need to measure time

intervals. Also, IPULSE is not dependent on the changing rate of VOUT and continuously

produced, so the event-driven LDO does not suffer from the sticking problem. These sub-

stantially simplify hardware design, reducing power and area overhead. Self-triggering also

47

reduces the settling time (TS) thanks to frequent triggering even when VOUT changes slowly

unlike the prior event-driven LDOs. Still, the proportional part (P-part) is optimized to min-

imize the first compensation latency. We also devise the initialization scheme to further speed

up regulation. With this new control, we prototyped the LDO in a 65nm. It demonstrates

significant improvement in major performance metrics over the state-of-the-art event-driven

and time-driven LDOs.


Figure 4.2: Entire architecture of the proposed LDO design

Figure 4.2 shows the proposed LDO architecture. It consists of a continuous-time (CT)

ADC, a pulse controller, a proportional part (P-part), a integration part(I-Part), and power

transistor arrays. Unlike an ADC in the previous event-driven LDO works [16, 18], this

ADC consists of CT comparators without large input capacitors [44], so its area is reduced

substantially. The ADC digitizes VOUT into a 7-bit thermometer code (LV). Having seven

comparators rather than one can increase precision in digital control (e.g., power transistor

granularity), improving regulation speed and accuracy.

48

4.3 Pulse controller for self-triggering control

Figure 4.3: Pulse controller with FSM

The pulse controller governs the overall event-driven regulation process. It consists of

a pulse generator, a pulse logic, a ring oscillator, a steady state detector and a finite state

machine (FSM). The pulse controller produces two types of pulses: PPULSE for the P-part

and IPULSE for the I-Part. As shown in Figure 4.3, the FSM determines the I-part states:

Steady, Initialization, and Integration.

If VOUT is regulated (i.e., VOUT=VSP ), its state is set to steady. In the steady state, it

triggers neither the P-part nor the I-Part, so the controller just holds the previous output.

As VOUT deviates from VSP by a new load current change, the ADC detects the deviation in a

continuous-time manner and changes its digital output, LV. The XOR-based pulse generator

consists of XOR, OR gates and delay elements as shown in Figure 4.4. A change in each LV

signal produces a pulse by XOR-ing LV and delayed LV. OR-ing all puleses produces PPULSE

and OR-ing puleses from LV[3,4] and LV[2,5] is used to produce TDC BGN, TDC END,

49

Figure 4.4: Pulse generator

respectively. TDC logic allows TDC BGN and TDC END to rise only once before reset by

STEADY signal. LV[3] is used for SIGN in the initialization process, which will be explained

later. Every PPULSE directly triggers the P-Part to start computing KP · (VSP − VOUT )

and accordingly control its power transistors. The latency from a VOUT deviation to the

power transistor control of the P-part, i.e., the first compensation latency, is aggressively

optimized. This enables COUT scaling to 0.1nF while still meeting the 10% droop constraint.

Figure 4.5: Steady state detector

Also, the first PPULSE initiates the self-triggering loop. The PPULSE from the pulse

generator or the IPULSE with STEADY enables the ring oscillator to produce IPULSE.

Note that the pulse logic block checks PPULSE asynchronously and IPULSE synchronously.

To turn off the ring oscillator, the pulse logic checks STEADY signal from the steady state

detector every IPULSE. The steady state detector (Figure 4.5) checks the error existence

50

during 7 cycles of IPULSE and asserts STEADY if any of the errors is non-zero. If all errors

in 7 consecutive cycles are zero, meaning VOUT is stable for a long time and the regulation

process is done, STEADY becomes low. At the next IPULSE, the pulse logic turns off the

ring oscillator according to the STEADY . As a result, the IPULSEs are being produced

only when error exists. Note that the FSM is also updated by STEADY every IPULSE.

4.4 Integration part with initialization

Figure 4.6: Timing diagram of regulation process with initialization

Figure 4.6 shows the process of Initialization and Integration. The first PPULSE is

produced and the P-part responds to the load current change. Also, the first PPLUSE has

51

the pulse logic to enable a local ring oscillator and start producing IPULSE. At the first

IPULSE, the FSM enters the Initialization state and the embedded time-to-digital converter

(TDC) estimates ∆ILOAD. As VOUT crosses two nearest reference levels from VSP (VREF [3]

to VREF [2] for VOUT undershoot; VREF [4] to VREF [5] for VOUT overshoot), TDC BGN and

TDC END are asserted. A classic TDC in the I-part uses these signals and measures the

time interval (TINT) between the rising edges of TBC BGN and TDC END. ∆ILOAD can be

estimated by TINT (∆ILOAD ≈ COUT · ∆VOUT/TINT ) because the regulation for the new

load current change is not applied at the beginning of the process. Then, the time encoder

in the I-part maps TINT into the programmed value in an inverse proportional manner and

add the value to the current I-part output. The I-part regulation is now able to start with

value close to the desired value for the new load current without a number of iterations. As

a result, the initialization process significantly improve regulation speed, thus reduces TS.

Figure 4.7: Integration part

In the next IPULSE, the FSM enters the Integration state. Here, the pulse logic keeps

52

enabling the local ring oscillator to produce IPULSE repeatedly at the same interval as

long as the error becomes zero (VOUT = VSP ). The I-part is kept triggering by IPULSE

to calculate integrals by simply accumulating ERROR (= VSP − VOUT ), as the time-driven

control does. Note that LV is also kept updating every IPULSE. The proposed event-driven

LDO, therefore, no longer requires a hardware multiplier needed by the conventional event-

driven LDOs for computation of time-interval and error product [16,18] to take varying time

interval into account. I-part gain (KI) is again constrained to a power of two to use a shifter

to approximate multiplication. Also, the IPULSE triggering occurrence is independent of

VOUT dynamics; thus it eliminates the sticking problem (when VOUT changes slow so that

the I-Part update happens sparsely). Therefore, it largely shortens TS. The FSM finally

goes back to the Steady after VOUT is regulated to VSP , using a steady state detector which

checks the error is zero for seven consecutive IPULSE cycles. The structure of I-Part for

Initialization and Integration is shown in Figure 4.7.

4.5 Proportional part with timing hysteresis

Figure 4.8: Timing diagram with and without timing hysteresis

53

We also infuse timing hysteresis in the P-part control to prevent limit cycle. The first

IPULSE is produced by PPULSE through the pulse logic, so the delay between the P-part

and the I-part regulations exists. Figure 4.8 shows the case where the P-part with high

gain temporarily recovers VOUT to VSP for small ∆ILOAD. At the following IPULSE edge,

the I-part only latches LV that represent zero error, so the I-part remains in the Steady

state. Only with the P-part regulation, the VOUT is likely to oscillate near VSP since it

cannot solely remove the steady state error, therefore finish the regulation. Note that larger

∆ILOAD causes no such oscillation since the P-part cannot regulate the error to zero so

quickly that the I-part will involve in the regulation process.

Figure 4.9: Proportional part with the implementation of timing hysteresis

To avoid this, we added a small amount of timing hysteresis to the P-part (Figure 4.9).

Specifically, we use a pair of a flip-flop and a latch to store LV[3] and LV[4]. All the other

LV bits are stored in latches. If the P-part sees the error that is ±1 (i.e., LV[3] and LV[4]

latches new value), it modulates the power transistors corresponding to LV[3] and LV[4] after

a small amount of delay. During this delay, the I-Part can latch the proper non-zero error

value and be involved in the regulation process. This leads to the prevention of limit cycle

54

without performance degradation for large ∆ILOAD.

4.6 Measurement Results


We prototyped the proposed LDO in a 65nm process (Figure 4.10). Figure 4.11 shows

the measured transient response with VIN=0.5V, VOUT=0.45V when load current changes

from 70µA to 2.37mA in 0.1ns. The LDO can meet the droop voltage constraint ( 11%,

∆VOUT=49.8mV) only with on-chip 0.1nF COUT . Thanks to the self-triggering control and

initialization, it also achieves TS=26.4ns, which is >100X shorter than prior event-driven

LDOs [16,18].

Figure 4.12 shows the transient performance with different configurations without ini-

tialization. Larger KP and KI can respectively scale down ∆VOUT and TS. Note that the

configuration with KP = 8, KI = 1 leads to larger TS since the Large KP suppresses most of

∆VOUT in the beginning, so the I-Part only updates its output with small error. Figure 4.13

confirms that the proposed initialization can effectively scale TS and ∆VOUT , showing 4.4µs

reduction and 44% reduction, respectively. It is more effective for large ∆ILOAD with low

55

Figure 4.11: Transient response with and without initialization

gains. The initialization is not activated for small ∆ILOAD since the second PPULSE, which

produces TDC END, is not generated in the Initialization state, i.e., the first period of

IPULSE. Also, if high KP is used, the P-part strongly suppress the voltage change rate, so

the initialization becomes unnecessary. Figure 4.14 shows the operation of the LDO across

different VINs with fixed 50mV drop-out. Our LDO supports up to 5.62mA ILOAD at 0.5V

VIN , which is our target VIN , with the maximum current efficiency of 99.7%.

Finally, we compare our design to the state-of-the-art ED and TD LDOs in Table 4.1

( [21] is difficult to compare since it discloses no measurement at 0.5V VIN). In the FoM

typically used for droop voltage and COUT scaling, our LDO is 11.7X better than the TD

and 1.2X than the ED. In TS, our LDO is 3.8X better than the TD and 424X than the ED.

Finally, in the current density, defined as the maximum current support divided by the total

56

Figure 4.12: Impact of gains (KP , KI) on transient performance without initialization

Figure 4.13: Impact of initialization on (a) TS, (b) ∆VOUT

area normalized to a process, our LDO achieves 165mA/mm2, 9.6X better than the TD and

6.7X than the ED.

57

Figure 4.14: Load regulation and current efficiency across multiple VIN


58

Chapter 5

Conclusion

Modern SoC designs require tens of domains for power efficient operation. A low-drop-out

voltage regulator (LDO) is one of the most efficient way of implementing power domains.

As the number of power domains increases, it is preferable to design compact LDOs. In

particular, its digital implementation, i.e., digital LDO, recently has emerged as a popular

topology since it can support a wide range of input voltage from nominal to near-threshold

regimes, while the classical analog LDO becomes less effective. However, one of a key

challenge towards fully integrated designs is a off-chip output capacitor for each LDO to

compensate fast load current change challenges. In order to alleviate the requirement for

output capacitor size, we must improve transient performance by reducing control loop

latency. Conventional time-driven digital LDO designs have a trade-off between performance

and power consumption, so higher power dissipation is inevitable to achieve output capacitor

size reduction.

In the course of my research, we introduced the event-driven control to digital LDO

designs to break the trade-off, minimizing output capacitor. We prototyped three different

59

event-driven LDO designs. In the first design, we first applied the event-driven control and

employed binary PI controller instead of shift-registers. Then, we designed the second event-

driven LDO with parallel controller and achieved large reduction in control latency, thereby

improving performance with further reduced output capacitor. Lastly, self-triggering control

and initialization in the most recent design contribute to short settling time and high current

density while maintaining performance. In sum, we accomplished smaller output capacitor,

better performance, and higher current density over time-driven digital LDO designs.

Still, there is more room to improve on LDO designs. Digital LDO is susceptible to power

supply noise because of power transistor operation in the triode region. Recent analog-

assisted LDO designs tackled this challenge, but it would be beneficial to handle power noise

in digital domain systematically. Also, continuous time ADC dissipates large quiescent power

to reflect output voltage change immediately to the controller. This significantly degrades

current efficiency at high input voltage. To cover a wide range of input voltage with high

current efficiency, a novel continuous time ADC design must be accompanied.

60

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