Front-End electronics for Future Linear Collider calorimeters FJPPL meeting @ KEK C. de La Taille N....
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Transcript of Front-End electronics for Future Linear Collider calorimeters FJPPL meeting @ KEK C. de La Taille N....
Front-End electronics for Future Linear Collider
calorimeters
FJPPL meeting @ KEK
C. de La TailleN. Seguin_MoreauIN2P3/LAL Orsay
On behalf of the CALICE collaboration http::/www.lal.in2p3.fr/technique/se/flc
Slides from JC Brient, S. Blin, C. Jauffret, J. Fleury, G. Martin-Chassard, L. Raux, F. Sefkov
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 2
Orsay Micro-Electronics Group
A strong team of 9 ASIC designers… = 20% of in2p3 designers = 60% of department research engineers A team with critical mass Expertise in low noise, low power high level
of integration ASICs 2 designers/ project 2 projects/designer Regular design meetings
…Within an electronics department of 55 Support for tests, mesaurements, PCBs…
A steady production 1-2 large productions/year
A strong on-going R&D Building blocks SiGe 0.35µm (S. Blin, M. Bouchel, R. Chiche, J. Fleury, CdLT,
G. Martin, L. Raux, N.Seguin, V. Tocut)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 3
ASIC production for ATLAS LAr calorimeter
ATLAS 128ch front-end board (1700)
SHAPER_V3 (1999)4 ch. tri-gain (1,10,100) fast-shaper (30ns)BiCMOS 1.2µm70 000 chips
HAMAC (2000)16 ch 12 bits analog memoryEcriture/lecture : 40/5MhzDMILL 0.8µ84 000 chips
ATLAS 128ch calibration board (135)
DAC (2003) R/2R 16 bitsDMILL 0.8µ8 000 chips
LOANA (2002)Low offset opamp (<10 µV) + switch HF (50µV 5V à 1‰)DMILL 0.8µ40 000 chips
(CdLT, N.Seguin, JP Richer)(D. Breton, CdLT, JP Richer, N.Seguin, V. Tocut)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 4
ATLAS : LAr e.m. calorimeter
200 000 channels
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 5
Readout ASIC for multi-anode Photomultiplier (Hamamatsu)
OPERA_ROC (2002)32 channelsVariable gain preampAutotrigger on ¼ p.e.BiCMOS 0.8µ3 000 chips
64 ch front-end board (BERN)
ASIC production for OPERA target tracker
(S. Blin, T. Caceres, CdLT, G. Martin, L. Raux)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 6
« Imaging calorimetry » at ILC
Particle flow algorithm Reconstruct each particle individually Bring jet resolution down to 30%/√E Measure charged particles in tracker Measure photons in ECAL Measure hadrons in ECAL and HCAL Minimize confusion term
Calorimeter design High granularity : typ < 1 cm2
High segmentation : ~30 layers Moderate energy resolution (10%/√E) ECAL : Silicon-Tungsten HCAL : analog vs digital
CALICE collaboration « a high granularity calorimeter
optimized for particle flow algorithm 190 phys./eng., 9 countries, 3
regions
©J.C Brient (LLR)F. Sefkow (DESY)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 7
ILC Challenges for electronics
Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress Front-end embedded in detector Ultra-low power : ( « 100µW/ch) 108 channels Compactness
« Tracker electronics with calorimetric performance »
ATLAS LAr FEB 128ch 400*500mm 1 W/chFLC_PHY3 18ch 10*10mm 5mW/ch ILC : 100µW/ch
W layer
Si pads
ASIC
Ultra-low POWERis the
KEY issue
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 8
CALICE physics prototype(s)
1 m3 prototype for physics tests Goal : study particle flow algorithm Check modelization of hadronic
showers
3 calorimeters to go to testbeam ECAL : W-Si 24X0 20x20 cm2
AHCAL : Tiles + fibers + SiPMs DHCAL : RPCs or GEMS Already 104 to 4 105 channels ! Run at DESY (05), CERN (06), FNAL
(07)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 9
ECAL
TCMT HCAL
Testbeam at CERN SPS
Common DAQ18’000 ch
ECAL
HCAL
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 10
14 layers, 2.1 mm thick70 boards made in Korea
ECAL W-Si prototype
ECAL prototype 1 cm2 Si PADS, 550 µm 1 MIP = 40 000 e- 216 channels/slab 10 000 channels total
Readout electronics FLC_PHY3 ASIC [LAL] Calibration ASIC [LAL] CRC DAQ boards [UK]
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 11
FLCPHY3 front-end ASIC
AmpOPA
OPA
G1
G10
1 channel Chip architecture 18 Channels/chip Low noise charge preamp optimized
for Cd=70pF. Variable gain (Cf = 0.2 -> 3 pF) ENC = 1000e- + 40 e-/pF @ tp=200ns series noise : en = 1.6nV/√Hz @ 600 µA poor 1/f noise : 25 e-/pF
Dual gain shaper (G1-G10) tp = 200 ns splits 15bit dynamic range in 2 x 12 bits
Differential shaper and Track&Hold => better pedestal stability and dispersion : pedestal dispersion : 5 mV rms
Multiplexed output : 5 MHz
Power dissipation : 6mW/channel Technology : AMS 0.8µm BiCMOS 2000 chips produced in 2003, yield :
86%
Synoptic of 1 channel of FLCPHY3
©J. Fleury (LAL)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 12
FLC_PHY3 : performance
Measured on all preamp gains Cf = 0.2, 0.4, 0.8, 1.6, 3 pF Well within ± 0.2 %
Dynamic range (G1, Cf=1.6pF) Max output : 3 V linear (0.1%) range : 2.5V
= 500 MIPS @ Cf = 1.6 pF
Noise : • 200 µV (Cd = 0)• 410 µV (Cd = 68pF)
• = 0.1 MIP @ Cd = 68 pF
Dynamic range : > 12 bits• 13 000 (14 bits) @ Cd = 0• 6500 (12 bits) @ Cd = 68 pF
Can be extended to 13-14 bits by using the bi-gain outputs
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 13
Results with detector
Testbeam at DESY (jan 05) and at CERN (2006) Calorimeter complete in depth (24
X0, 8000 channels) MIP/noise = 8 => clean cut at ½
MIP Calibration done with cosmics
Noise, MIP
2 adjacent 2 GeV electrons
©G. Gayken (LLR)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting
14
AHCAL testbeam prototype
• 1 cubic metre, • 38 layers, 2cm steel plates• 8000 tiles with SiPMs• Electronics based on ECAL design
Mechanics and front end boards: DESYFront end ASICs: LAL
©F. Sefkow (DESY)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting
15
SiPMs for calorimetry
• Multipixel Geiger Mode APDs– Gain 106, bias ~ 50 V, size 1 mm2
– Insensitive to magnetic fields
3x3 cm scintillator tile with WLS fibre
ITEP
1156 pixels with individual quenching resistor on common substrate
MEPHI / PULSAR
Auto-calibratingbut non-linear
New era for scintillator–based
detectors:High granularity at relatively low cost
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 16
SiPM readout ASIC
Readout AHCAL (DESY) SiPM detector (MEPHI ) >3000 channels : first large scale use G ~ 106 e ~10% HV ~ 50 V
FLC_SiPM readout ASIC 18 channel variable gain preamp and
shaper Dynamic range : 13 bits (2 gains) 8 bit DAC for SiPM gain adjustment 1000 chips produced in 2004
©L. Raux (LAL)
Single photoelectron spectrum © E. Popova
Power consumption : ~200mW (supply : 0-5V)
Technology : AMS 0.8 m CMOS
Chip area : ~10mm²
Package : QFP-100
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 17
SiPM Connection
SiPM connected with followed biasing scheme : HV = 45 V No external circuitry around SiPM
+HV
Preamp input
50Ω
100nF
SiPM
100kΩ 100nF 8-bit DAC
ASIC
Need 10k here to filter noise
High voltage on the cable shielding
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 18
Channel architecture for SiPM readout
100nF
10pF
Charge Preamplifier :Low noise : 1300e- @40ns
Variable gain :
4bits : 0.67 to 10 V/pC
CR-RC² Shaper :Variable time constant : 4 bits (12 to 180ns)
12ns photoelectron measurement (calibration mode)180ns Mip measurement (physic mode)
compatibility with ECAL read-out
12kΩ
4kΩ 24pF
12pF
3pF
in
8pF 4pF 2pF 1pF
40kΩ
8-bit
DAC
0-5V
ASIC
Rin =
10kΩ
50Ω
100MΩ 2.4pF
1.2pF
0.6pF
0.3pF
0.1pF
0.2pF
0.4pF
0.8pF
6pF
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 19
MIP and photo-electron responses
Physics mode :
Cf=0.4pF- =180ns - Rin ON
1 MIP = 16 p.e. injected (9.5mV in 270pF)
Vout = 23 mV @ tp = 160 nsNoise : 1 mV rms
Calibration mode :
Cf=0.2pF - =12ns - Rin OFF1 SPE = 0.16pC injected
(0.6mV in 270pF)
Vout = 11 mV @ tp = 35 nsNoise : 1.2 mV rms
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 20
Linearity measurement (physic mode)
Linearity Rin ON =180ns
0
500
1000
1500
2000
2500
0 50 100 150 200 250 300 350
Qinj (MIP)
Vo
ut
(mV
)
Cf=0,1pF
Cf=0,8pF
Cf=0,4pF
Cf=0,2pF
Cf=1,5pF
Linearity Residuals for physics mode (%)
-1
-0,8
-0,6
-0,4
-0,2
0
0,2
0,4
0,6
0 10 20 30 40 50 60 70 80 90
Injected charge (MIP=16p.e.)
0.5%
-0.5%
•Voltage swing : ~2.1V
•Dynamic Range: 80 MIPs
•Linearity: <1%
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 21
Cross-talk measurement
Set-up: Cf=0.4pF, =180ns Channel-to-Channel cross-talk : ~ 1-2‰ :negligible
2 contributions : Capacitive coupling
between neighboring channels
Long distance crosstalk in all channels (comes from a reference voltage)
Non-Direct neighbouring channel
x100
Sampling time
Capacitive coupling
contribution
Direct neighbouring channel x100
Long Distance cross-talk
contribution
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 22
Digital HCAL physics prototype
GEM based DHCAL RPC based DHCAL
Signal PadMylar sheet
Mylar sheet Aluminum foil
1.1mm Glass sheet
1.1mm Glass sheet
Resistive paint
Resistive paint
1.2mm gas gap
-HV
GND
Charged particles
©A. White (U. Arlington)J. Repond (ANL)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 23
DHCAL front-end electronics ©J. Hoff, A. Mekaoui (FNAL)
DCAL chip 64 inputs with gain choice
GEM/RPC Triggerless or triggered operation Output hit pattern & time stamp Prototyped in 0.25µm in march
2005
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 24
DCAL chip performance
DCAL chip performance All digital functions operationnal Excellent efficiency curves Threshold adjustable between 2-8 fC
DCAL2 chip Submission foreseen july 06 Reduced preamp gain Threshold RPC ~ 100 fC Threshold GEMS ~10 fC
©G. Drake (ANL)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 25
Next steps
FLC_PHY3 (2003)
HaRD_ROC (2006)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 26
Technological prototype : “EUDET module”
Front-end ASICs embedded in detector Very high level of integration Ultra-low power with pulsed mode FLC_TECH1 ASIC prototype in 0.35 µm SiGe
All communications via edge 4,000 ch/slab, minimal room, access, power small data volume (~ few 100 kbyte/s/slab)
« Stitchable motherboards »
Elementary motherboard ‘stitchable’ 24*24 cm ~500 ch. ~8 FE ASICS
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 27
NovosibirskProtvinoITEPMPHIMSUObninsk
KEK (Japan)
The EUDET Map EUDET partners EUDET associates
May 2006
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 28
EUDET : ECAL emodule
Electromagnetic calorimeter Prototype of a (~ 1/6) module 0 :
one line & one column 150 cm long, 12 cm wide 30
layers 1800 + 10800 channels Test full scale mechanics + PCB Can go in test beam Test full integration + edge
communications Similar in #channels as physics
prototype
©M. Anduze (LLR)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 29
EUDET module FEE : main issues
Mixed signal issues Digital activity with sensistive
analog front-end
Pulsed power issues Electronics stability Thermal effects To be tested in beam a.s.a.p.
No external components Reduce PCB thickness to <
800µm Internal supplies decoupling
FE chip (1mm)Wafer (400µm)PCB (600µm)
Tungsten (1 mm)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 30
Evolution of PCBs
FLC_FEV1
FLC_FEV2
ILC_FEV3
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 31
ECAL Front-End ASIC
PowerCycling
Auto-trigger on ½ MIP
Internal ADC
Readout integration is the key element of compact detector Keep small Moliere radius for good shower separation Many features have never been used before e.g. power cycling (ON 2ms OFF
200 ms)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 32
EUDET DHCAL RPC ASIC
Move towards ILC specs Power pulsing Data internally saved during bunch train Data transferred to DAQ during inter-bunch
Chip based on MAROC will be submitted in sep 06
Close
to M
AROC chip
64 chan
nels f
or m
ulti-a
node
PM
C h a n n e l 0
C h a n n e l 1
C h a n n e l 2
C h a n n e l 3
C h a n n e l 6 2
C h a n n e l 6 3
T h r e sh o ld 0
T h r e sh o ld 1
T h r e sh o ld 2
T h r e sh o ld 3
T h r e sh o ld 6 2
T h r e sh o ld 6 3
>
B unc h c ro s s ing ID
Dig
ital m
emor
y[ 6
4 bi t s
(da
t a)
+ 12
bi ts
(B
CID
)]*d
e pht
mem
ory write
D a ta o u t
an a lo g u e f r o n t- en d
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 33
MAROC : 64 ch MAPMT chip for ATLAS lumi
Characteristics 64 PMT channels input (50-100 Ω) Variable gain current conveyor (0-2)
6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16
64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron
(50fC). Counting rate up to 2 MHz Common threshold loaded by internal
10bit DAC 1 multiplexed charge output with variable
shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC) Crosstalk < 1%
Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm2
Dissipation 130 mW @ VDD=3.5V
Can be accomodated to DHCAL Adding power pulsing and digital readout
Synoptic diagramm of MAROC1
Hold signal
Variable
GainPream
p.
VariableSlow
Shaper
S&H
BipolarFast Shaper
64 Trigger outputs
Gain correction6 bits/channel
discriminator
threshold10 bits DAC
Multiplexed charge output
64 PM inputs
10 bit DAC
Chip On Board
3*3 cm2
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 34
MAROC Efficiency curves
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 35
HaRDROC architecture Full power pulsing Digital memory: Data saved during bunch train. Only one serial output Store all channels and BCID for every hit. Depth = 128 bits Data format : 128(depth)*[2bit*64ch+32bit(bcid)+8bit(Header] = 20kbits Sequential readout @ 100 MHz : 20k* 10 ns = 200 µs (read up to 1000
chips/inter bunch)
64 INPUTS
1 OUTPUTTransfered to DAQ during Inter-bunch
Hold: Ext signal or OR output
Variable Gain
Preamp.
VariableSlow Shaper
20-100 ns
S&H
BipolarFast Shaper
Gain correction
64*6bitsG=0 to 4
2 discri thresholds (2*10 bits)
2 DACs10 bits
Latch
Latch
Vth1 -
Vth0 -
-Vth1 -Vth0
OR
trig1<0>
trig1<63>
trig0<0>
trig0<63>
MultiplexedAnalog charge
output
trig1<63>
trig1<0>
WR
SRAM
128*
160
32 bit counter BCID
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 36
HaRDROC layout 64 inputs, 1 data output Vss of the analog, mix and digital part separated 180 pads
64 Analog
Channels
Digital memory
Control signals and power supplies
Control signals and power supplies
Dual DAC
Bandgap
Discris
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 37
Digital architecture towards 2nd generation DAQ
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 38
Inter chip communication
Open collector common control and data line
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 39
Acquisition mode
Store upto 128 events in RAM Stop acquisition when ram_full signal asserted
Common collector bus for ram_full signal
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 40
Readout mode
Token ring mechanism initiated by DAQ Possibility to bypass a chip by slow control
One data line activated by each chip sequentially Readout rate few MHz to minimize power dissipation With 500 pF bus capacitance, power dissipation is ~10uW/chip i=CdV/dt = 1 mA => 1 mW for up to 100 chips on bus Readout time max (ram full) 10kbit * 1 µs = 10 ms/chip
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 41
EUDET ECAL ASIC
72 channels Scales with the 4 factor reduction in pad size and is compatible with
physics prototype
Detector DC coupling Prepares the case the on-detector MMIC HV capacitance is not
affordable Provides leakage current monitoring, up to 1 µA/Ch
Auto-trigger If one channel is hit during a bunch crossing, then the whole chip is
recorded with a time tag (BCID) The auto trigger activates the T&H
Analogue pipeline, ADC & digital registers 8-depth analog pipeline to store « in bunch » events Wilkinson 12 bit 100MHz ADC On chip storage, inter-bunch data outputting
Digital data output Daisy chained with redundancy : one output for 40 ASICs Common architecture for ECAL and HCAL
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 42
Present status on noise & power cycling
FLC_TECH1 : moving into SiGe 0.35µ 30 µW in pulsed mode ENC = 1000 e- @ Cd=27pF (MIP=40 000e-) NOISE WELL BELOW MIP First demonstration of power cycling : Target power of 100 µW/channel
appears within reach : to be validated in testbeam in 2006 with FLC PHY4 ASIC
FLC shaping
Detector capacitance
Autotrigger
ON
signal
Ready for pulse
RFCF
20 µs
POWER CYCLING MEASUREMENTNOISE MEASUREMENT
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 43
General block scheme
Ch. 0
Ch. 1
Analog channel Analog mem.
72-channelWilkinson
ADC
Analog channel Analog mem.
Ch. 71 Analog channel Analog mem.
Bunch crossing 24 bit counterTime
digital mem.
Eventbuilder
Memorypointer
Triggercontrol
MainMemory
SRAM
Commodule
EC
AL
SLA
B
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 44
One channel
20M
1M 200ns
G=10
G=1
200ns
Analog Memory
Depth = 5
Analog Memory
Depth = 5
G=100G=5
12 bits
ADC
Gain selection
0=>6pF
3-bit threshold adjustment
10-bit DAC
Common to the 72
Channels
T100ns
DAC output
Q
HOLD
Preamp
Ampli
Slow Shaper
Slow Shaper
Fast Shaper
Time measurement
Charge measurement
3pF
Calibration input
input
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 45
Time considerations
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns Train length 2820 bunch X
(950 us)
Acquisition
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
1% duty cycle
IDLE MODE
99% duty cycle
199ms (99%)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 46
Wilkinson ADC description
Ch.0
Ch.1
Ch.62
Ch.63
Ramp generator
12 bits register
12 bits register
12 bits register
12 bits register
12 bits gray counter
12
startstop
resetoverflow
Start Ramp
Reset Ramp
64Channel hitRegister in Wilkinson control
116 start_ADC*
184 RST*
115 out_ADC
114 ADC_DAV
Vref_sh
Start Cmpt
95 vslope99 vref_Ramp 97 Ramp
Description :- 12 bits- 64 channels- conversion time < 80µs- clock 40 MHz-Serial output
ADC= Integrated in MAROC2 and tested
ADC count versus Vin
0
500
1000
1500
2000
2500
3000
3500
4000
4500
1,3 1,6 1,9 2,2 2,5
Vin (V)
# A
DC
cou
ntWilkinson ADC results
Vref shaper
INL versus Vin
-2,5
-2
-1,5
-1
-0,5
0
0,5
1
1,5
2
1,3 1,6 1,9 2,2 2,5
Vin(V)
INL
(ADC
cou
nt)
INL (ADC count) vs Vin
+1.5
-1.5
ADC count vs Vin
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 48
Digital part Store all channels and BCID for every hit. Depth ~8 bits Event size : 8(depth)*[16bit*72ch+16bit(bcid)] = 9344 bits Sequential readout : 9344*10ns = 100 µs : open collector
level
Register 16bits
OR
16 bit counter BCID
Register 16bits
DiscriCH 0
DiscriCH 71
Register 16*16 bit BCID
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting
49
HCAL architecture
Typical layer2m2
2000 tiles
38 layers80000 tiles
FEE: 32 ASICs (64-fold)
4 readout lines / layer
Layer dataConcentrator
(control, clock and read FEE)
Module data concentrator
Instrument one tower (e.m. shower size)
+ 1 layer (few 1000 tiles)
To DAQ
EUDET: Mechanical structure, electronics integration:
DESY and Hamburg U
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 50
Prospective for A-HCAL SiPM Chip
Similar developments for AHCAL Chip fully dedicated to SiPMs developped after ECAL chip Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing
T&Hx1
Variable gain Preamplifier
Discri
TDC
12-bit ADC
8 bit DAC (0-5V)
in
Fast Shaper
Shaper tp~30-40ns
Auto-trigger
12-bit DAC
Threshold
Capacitance for AC
coupling
…
Analogue Memory
Charge Ouput
Time Ouput
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 51
Conclusion
Several large dynamic range ASICs developped for CALICE physics prototypes ECAL W-Si calorimeter : FLC_PHY3 = 104
channels in beam, dynamic range 0.1-600 MIPS
AHCAL Tile-SiPM calorimeter : FLC_SiPM = 103 channels installed, beam in summer 06
DHCAL GEM/RPC
ASICs for technological prototypes now in development Power pulsing, Zero-suppress, Auto-trigger…
System aspects not to be forgotten Power supplies ! Mechanics, reliability…
Help welcome Measurements on test bench and test beam EUDET postdoc position open at LAL