Developing a Video Strategy Framework - MCA - Tuesday 1st October 2013
Free video lectures for mca
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Free Video Lectures for MCA By: video.edhole.com
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Transcript of Free video lectures for mca
Free Video Lectures for MCA
By:video.edhole.com
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Chapter Four
Register Transfer and Micro operations
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Contents
• 4-1 Register Transfer Language
• 4-2 Register Transfer
• 4-3 Bus and Memory transfers
• 4-4 Arithmetic Micro operations
• 4-5 Logic Micro operations
• 4-6 Shift Micro operations
• 4-7 Arithmetic logic shift unit
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Register Transfer Language
The set of register it contains and their functions.
The sequence of micro operations performed on the binary information stored in the register.
The control that initiated the sequence of micro operations.
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Figure 4-1
Block diagram of register
R1
R2
7 6 5 4 3 2 1 0
PC(H) PC(L)
15 0 07815
Showing individual bitsRegister R
Divide into two partsNumbering of bits
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Figure 4-2
Transfer from R1 to R2
P: R2 R1
R2Contr
ol
circuit
Load P
n
Clock
R1
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Figure 4-2 b
Timing diagram
Clock
t t+1
load
Transfer occurs here
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Table 4-1
Basic symbols for register transfer
Symbol Description
Examples
Letters
(and numerals)
Parentheses ( )
Arrow
Comma ,
Denotes a register
Denotes a part of a register
Denotes transfer of information
Separates two micro operations
MAR, R2
R2(0-7),R2(L)
R2 R1
R2 R1, R1 R2
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Figure 4-3
BUS AND MEMORY TRANSFER
4 – L I N E
C O M M O N
B U S
3 2 1 0
4 x 1M U X 0
3 2 1 0
D0 C0 B0 A0
4 x 1M U X 1
3 2 1 0
4 x 1M U X 2
3 2 1 0
4 x 1M U X 3
3 2 1 0
D1 C1 B1 A1D2 C2 B2 A2
3 2 1 0 3 2 1 0 3 2 1 0
A2 A1 A0 B2 B1 B0 C2 C1 C0 D2 D1 D0
REGISTER C REGISTER AREGISTER BREGISTER D
S1
S0
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Table 4-2
Function table for bus
s1 s2 Register selected
A B C D
0 0 0 11 01 1
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Figure 4-4
Graphical symbol for Three-state Bus Buffers
Normal input A
Control input C
Output Y=A if C=1High-impedance if C=0
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Figure 4-5
Bus line with three state-buffers
Bus line for bit 0 A0
B0
C0
D0
Select
Enable
0
1
2
3
2 x 4
Decoder
S0
S0
E
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Memory Transfer
Read: DR M[AR]
Write: M[AR] R1
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Arithmetic Micro operations Register transfer micro operations transfer binary
information from one register to another.
Arithmetic micro operation performs arithmetic operations on numeric data stored in register.
Logic micro operations perform bit manipulation operations on nonnumeric data stored in register.
Shift micro operations perform shift operations on data stored register.
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Table 4-3Arithmetic Micro operation
Symbolic
designationDescription
R3 R1+ R2
R3 R1- R2
R2 R2
R2 R2 + 1
R3 R1+ R2 + 1
R1 R1 + 1
R1 R1 - 1
Contents of R1 plus R2 transferred to R3
Contents of R1 minus R2 transferred to R3
Complement the contents of R2( 1’s complement)
2’s complement the contents of R2(negate)
R1 plus the2’s complement of R2(subtraction)
Increment the contents of R1 by one
Decrement the contents of R1 by onevideo.edhole.com
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Figure 4-6
4 – Bit binary adder
FA FA FA FA
A0 B0
C0
S0 S1 S2 S3 C4
A1 B1 B2 B3 A2 A3
C1 C2 C3
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Figure 4-7
4 – bit adder subtractor
FA FA FA FA C0 C1 C2 C3
C4 S3 S2 S1 S0
A0 B0 A1 B1 B2 B3 A2 A3 M
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Figure 4-8
4 – Bit binary Incrementer
HA HAHAHA
C C C C SSSS
S0S1S2S3C4
x y x y x y x y
A0 1 A1A2A3
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S1S00123
S1
1
32
0S0
Figure 4-9
4-bit arithmetic circuit
Cin
S0S1
A0
B0
B1
B2
B3
Xo Co
X1 C1
X2 C2
X3 C3
Do
D1
D2
D3
Cout
yo C1
y1 C2
y2 C3
y3 C4
0 1
S1
1
32
0S0
S1
1
32
0S0
4 x 1
MUX
4 x 1
MUX
4 x 1
MUX
4 x 1
MUX
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Table 4-4Arithmetic circuit function table
SelectS1 S0 Cin
Input OutputD = A + Y + Cin Y
Micro operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
B
B
B
B
0
0
1
1
D = A + B
D = A + B + 1
D = A + B
D = A + B + 1
D = A
D = A + 1
D = A - 1
D = A
Add
Add with carry
Subt. with borrow
Subtract
Transfer A
Increment A
Decrement A
Transfer A
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Table 4 – 5
Truth table for 16 Function of two variables
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
x y F0 F1 F2 F3 F4
F5 F6 F7 F8 F9F10 F11 F12F13 F14 F15
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TABLE 4-6
SIXTEEN LOGIC MICRO OPERATIONS
Boolean function Micro operations Name
F0 = 0 F 0 Clear
F1 = xy F A ^ B And
F2 = xy’ F A ^ B
F3 = x F A Transfer A
F4 = x’y F A ^ B
F5 = y F B Transfer B
F6 = x y F A BExclusive-or
F7 = x + y F A ٧ B OR
F8 = (x + Y)’ F A V B NOR
F9 = (x Y)’ F A B Exclusive-NOR
F10 = y’ F B Complement B
F11 = x + y ‘ F A V B
F12 = x’ F A Complement A
F13 = x’ + y F A v B
F14 = (xy)’ F A ^ BNAND
F15 = 1 F all 1’s Set to all 1’s
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Figure 4-10
One stage of logic circuit
4x1MUX
S1 S0 Output Operation
0
0
1
1
0
1
0
1
E = A v B
E = A ^ B
E = A B
E = A
AND
OR
XOR
COMPLEMENT
E i
S1 S0
A iB i 0
1
2
3
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Figure 4-12
4-bit combinational circuit shifter
0
1
S
S
S
S
0
1
0
1
0
1
Mux
Mux
Mux
Mux
0
1
Select
S
OutputH0
H0
H1
H2
H3
H1 H2 H3
IR
A1
A0
A2
A1
A3
A2
Il
Ao
A1
A3
A4
Serial input (IL)
Serial input (IR)
Select0 for shift right
1 for shift left
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Figure 4-13
One stage of arithmetic logic shift unit
Select
0
1
2
3
Di
Ei
shr
shl
Ai -1Ai+1
Ai
Bi
Ci
Ci+1
S0
S1
S2S3
One stage of logic circuit
One stage of arithmetic
circuit
F i4 x 1
MUX
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Operation SelectS0S1S2S3 Cin
Operation Function
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
x
x
0
0
1
1
0
0
1
1
0
1
0
1
x
x
0
1
0
1
0
1
0
1
x
x
x
x
x
x
F = A
F = A + 1
F = A + B
F = A + B +1
F = A + B
F = A + B + 1
F = A -1
F = A
F = A ^ B
F = A v B
F = A B
F = A
F = shr A
R = shl A
Transfer A
Increment A
Addition
Add with carry
Subtract with borrow
Subtraction
Decrement A
Transfer A
AND
OR
XOR
Complement A
Shift right A into F
Shift left A into F
Table 4-8
Function table for arithmetic logic shift unit
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