FPGA Heterogeneous Packaging Applications: Trends and...
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© Copyright 2018 Xilinx FPGA Heterogeneous Packaging Applications: Trends and Challenges Suresh Ramalingam Fellow, Advanced Packaging © Copyright 2018 Xilinx Agenda >> 2 Deep Learning and Inference Package Technology – Industry trends – Heterogeneous packaging – Progression to lower cost per interconnect – Thermal What’s Next – ALVEO U200/U250 – Versal ACAP SCV Chapter, Electronics Packaging Society November 14, 2018 www.cpmt.org/scv
Transcript of FPGA Heterogeneous Packaging Applications: Trends and...
© Copyright 2018 Xilinx
FPGA Heterogeneous Packaging Applications: Trends and Challenges
Suresh RamalingamFellow, Advanced Packaging
© Copyright 2018 Xilinx
Agenda
>> 2
Deep Learning and InferencePackage Technology– Industry trends– Heterogeneous packaging– Progression to lower cost per interconnect– Thermal
What’s Next– ALVEO U200/U250– Versal ACAP
SCV Chapter, Electronics Packaging Society November 14, 2018
www.cpmt.org/scv
11/14/2018
© Copyright 2018 Xilinx
Alveo accelerator cards deliver significant performance advantages over a broad set of applications. For machine learning, the Alveo U250 increases real-time inference throughput by 20X versus high-end CPUs, and more than 4X for sub-two-millisecond low-latency applications versus fixed-function accelerators like high-end GPUs*. Moreover, Alveo accelerator cards reduce latency by 3X versus GPUs, providing a significant advantage when running real-time inference applications.** And some applications like database search can be radically accelerated to deliver more than 90X, versus CPUs.***
Deep Learning: Training vs. Inference
© Copyright 2018 Xilinx
Alveo accelerator cards deliver significant performance advantages over a broad set of applications. For machine learning, the Alveo U250 increases real-time inference throughput by 20X versus high-end CPUs, and more than 4X for sub-two-millisecond low-latency applications versus fixed-function accelerators like high-end GPUs*. Moreover, Alveo accelerator cards reduce latency by 3X versus GPUs, providing a significant advantage when running real-time inference applications.** And some applications like database search can be radically accelerated to deliver more than 90X, versus CPUs.***
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Deep Learning: Solution Flexibility is Key
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Deep Learning on Xilinx Adaptable Devices
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Virtex 16nm UltraScale+: Full Spectrum of Memory
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Cavity Down BGAs
Multi Chip Module
Flip Chip BGAs – EU bump
QFPs
2000-2010 2011 - 2016 2017 - 2022
Package Technology Trends
Flip Chip BGAs – High Pb/EU bump
PBGAs
CSPs/PBGAs
Flip Chip CSP
Flip Chip BGAs – Pb-free/Cu pillar bump/Low Loss Substrate
Homogeneous SSIT
2.5D: SOC + HBM
InFO-oS/MS
Surface Mount Leadframe 1st Generation BGAs 2nd Generation BGAs: Flip Chip 3rd Generation: WL, 2.5D, 3D 3D & Photonics Integration
Active Stacking
Photonics IOs
1990-2000
Cu-wire
Flip Chip PoP
SiP
Wafer level fan-out
3D TSV
Cu-pillar BOT and ETS
Until 1990
PCB HDI/Fan-out PoP
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Virtex 16nm UltraScale+ FPGA-HBM Product
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Partitioned FPGA co-packaged with stacked DRAM (HBM)using Xilinx 3rd Gen Stacked Silicon InterconnectTechnology (SSIT) based on CoWoS platform
Revolutionary increase in memory performance delivering10x bandwidth per HBM stack and 4X lower power vs DDR4
Reduced board space and complexity
55mm2 Lidless package for enhanced thermal performance,< 12mil co-planarity
Copper Pillar C4 bump with Pb-free solder for fine pitchinterconnect to substrate
Passed JEDEC component & board level reliability
Customer Sampling
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HD Multi Chip Package – Side by Side
Intel EMIBTSMC InFO-oS/MS, ASE FOCoS Shinko iTHOP
EMIB
CoW-last
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Technology Progression to Lower Cost per Interconnect
>> 11 Routing density: 1/(line pitch) (1/um)
102
103
104
0.1 1.0 10
Connecti
on (
bum
p)
densi
ty:
1/(
bum
p p
itch)2
(1/m
m2)
InFO-oS/MS,
FOCoS
Monolithic Flipchip
CoWoS
Si interposer
105
102
Cu/SiO2
bonding
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Next Challenges
˃ Thermal dissipation through stacked dies and increasing total power˃ Design flow, CAD tools and environment˃ Yield and reliability of fine-pitch multiple die and wafer stacking˃ Yield and reliability of fine-pitch TSV˃ TSV keep-out zone of transistors
>> 12
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Ever Increasing Power Density
SoC Are Growing, FastProgrammable logic capacity growing 2-3X every 2-3 yearsHeavy Hard-IP (SoC) content driving up power density“More than Moore” 2.5 and 3D IC TechnologyBut device/package size is not growing ‒ More than doubling the capability in the same
footprint
Increasing Power Density Driving Thermal Management Innovation
This is why industry roadmap is very focused on improving thermal design
Thermal Load
?
Gen 1: FCBGA Gen 2: 2.5D TSV Gen3: 2.5D TSV and HBM Gen4:?
Gen 4
Gen 3
Gen 2
Gen 1
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High Conductivity TIM – Watch for the Pitfalls…
Material X, k= 4.8 W/mk
Material K. k= 3.5 W/mk
Material S, k=1.92 W/mk
Material SD, k= 3.5 W/mk
Material K, K= 3.5 W/mk
48.77W
End of Life: Ambient 24C
Characterizing different TIM with Target BLT 70um in the packaging assembly in special Thermal TV
Tim 0: Ambient 24C
Material K Material K
Material Time 0 EOL(TCB1200)
X
K
S
SD
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Extending Thermal Performance
US9,812,374B1. Nov 7, 2017, Refai-Ahmed et al & ASME 2107 & IEEE EPTC 2018
~35% Improvement
1X W 1.5X W
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ALVEO for Data Center Workloads
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Versal ACAP – Delivering Breakthrough AI Inference Performance
