FPGA Editor Lab Introduction

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© 2003 Xilinx, Inc. All Rights Reserved FPGA Editor Lab Introduction

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FPGA Editor Lab Introduction. Objectives. After completing this lab, you will be able to: Analyze the contents of a slice Add a probe Change I/O locations and contents View a constrained path and take steps to improve the performance of a net. Rhett Whatcott: - PowerPoint PPT Presentation

Transcript of FPGA Editor Lab Introduction

Page 1: FPGA Editor Lab Introduction

© 2003 Xilinx, Inc. All Rights Reserved

FPGA Editor Lab Introduction

Page 2: FPGA Editor Lab Introduction

FPGA Editor Lab Intro - 19a - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Objectives

After completing this lab, you will be able to:• Analyze the contents of a slice• Add a probe • Change I/O locations and contents• View a constrained path and take steps to improve the performance

of a net

Page 3: FPGA Editor Lab Introduction

FPGA Editor Lab Intro - 19a - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Lab Design: Correlate and Accumulate

Rhett Whatcott:

v6.1: Added note on design description.

Rhett Whatcott:

v6.1: Added note on design description.

Page 4: FPGA Editor Lab Introduction

FPGA Editor Lab Intro - 19a - 4 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

General Flow

• Step 1: Implement the Design and Launch FPGA Editor• Step 2: Analyze Slice Contents• Step 3: Add a Probe• Step 4: Modify IOB Properties• Step 5: Move an IOB’s Location• Step 6: Analyze Timing Results• Step 7: View a Path• Step 8: Reroute a Net

Rhett Whatcott:

v5.2: Changed slide.

Rhett Whatcott:

v5.2: Changed slide.


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