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Content Up-to-date as of: December 3rd, 2009

General Chair’s Welcome

Welcome to DVCon 2010! DVCon is the premier conference for functional design and verification of digital electronic systems. The conference is focused on bringing you information from the leading edge of technology, techniques, standards and methods. We are gratified that DVCon continues to be one of the most respected technical conferences around, as our growth will attest, and we invite you to be a part of it.

The Conference has been expanded an extra half-day this year!The strength of DVCon is undoubtedly our high-quality technical program, which we expanded last year by adding additional paper sessions. This year we continue to grow by adding another half-day to the conference, with three more sponsored tutorials being presented on Monday afternoon. This growth, combined with the substantial increase in submissions for the technical program, is further evidence that the leaders of our industry view DVCon as the place to be.

The Keynote Session and Industry Leaders Panel is free to all this year!Our keynote speaker is Cadence Design Systems CEO Lip-Bu Tan, giving us his perspective as the CEO of a leading EDA solutions provider on our industry’s challenges and evolution. Following the keynote will be our popular “Industry Leaders” panel, moderated this year by JL Gray, of the “Cool Verification” EDA blog. This year’s panel will ask the panelists “What Keeps You Up At Night?” and other pressing questions about what they see as the market’s challenges and opportunities, as well as no-holds-barred questions from the audience.

As our industry grows and evolves, DVCon will grow and evolve with it. Remember, we’ve added an extra half-day to the program, so book your travel accordingly so you’ll be able to attend one of the new Monday tutorials. These added tutorial sessions provide even more opportunities for in-depth learning about leading-edge verification techniques as you’ve come to expect. This year’s program continues our tradition of providing a high level of educational and practical material that everyone can use in their daily work life. And don’t forget to visit our exhibit floor, where you can learn first-hand about state-of-the-art solutions from all of the leading EDA vendors.

We endeavor to deliver on the charter of DVCon by improving the functional design and verification of electronic systems. I believe you will find the expanded DVCon 2010 a great forum for learning from vendors, consultants, colleagues and friends about the latest in the design and verification industry.

We look forward to seeing you there!

On behalf of the DVCon 2010 Steering and Program committees, we invite you to attend the ExPanDED Design & Verification Conference & Exhibition.

Tom FitzpatrickMentor Graphics Corp.2010 General Chair

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Table of ContentsGeneral Chair’s Welcome.............................................................................................................................................................................................................................. 1Steering Committee ....................................................................................................................................................................................................................................... 3Program Committee ....................................................................................................................................................................................................................................... 4Conference Sponsor ....................................................................................................................................................................................................................................... 5Accellera Luncheon ........................................................................................................................................................................................................................................ 6Monday at a Glance ........................................................................................................................................................................................................................................ 7Tuesday at a Glance ........................................................................................................................................................................................................................................ 8Wednesday at a Glance ................................................................................................................................................................................................................................. 9Thursday at a Glance ....................................................................................................................................................................................................................................10Tutorial Descriptions ............................................................................................................................................................................................................................. 11-17Wednesday Sessions: 1 - 4 .................................................................................................................................................................................................................. 18-19Wednesday Lunch Presentation ..............................................................................................................................................................................................................20Keynote Address ............................................................................................................................................................................................................................................21Wednesday Panel ..........................................................................................................................................................................................................................................22Thursday Sessions: 5 - 10 ..................................................................................................................................................................................................................... 23-25Thursday Lunch Presentation ...................................................................................................................................................................................................................26Thursday Sessions: 11 - 13 .................................................................................................................................................................................................................. 27-28Thursday Panel ...............................................................................................................................................................................................................................................28DVCon Expo .............................................................................................................................................................................................................................................. 29-39NASCUG Meeting ..........................................................................................................................................................................................................................................40Conference Registration .............................................................................................................................................................................................................................41Transportation and Hotel ...........................................................................................................................................................................................................................42Hotel Floorplan ..............................................................................................................................................................................................................................................43

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General Chair Tom FitzpatrickMentor Graphics Corp.18 Whistle Post Ln.Groton, MA [email protected]

Past Chair Stephen BaileyMentor Graphics Corp.1811 Pike Rd. Bldg. #2, Ste. FLongmont, CO [email protected]

Social Media ChairKaren BartlesonSynopsys, Inc.1125 Point of The Pines Dr.Colorado Springs, CO [email protected]

Conference ManagerKathy EmblerMP Associates, Inc.1721 Boxelder St., Ste. 107Louisville, CO [email protected]

Program Chair ambar SarkarParadigm Works, Inc.300 Brickstone Sq.Andover, MA [email protected]

Finance ChairLynn HorobinAccellera1370 Trancas St., Ste. 163Napa, CA [email protected]

accellera RepresentativeDavid LinDenali Software, Inc.1000 Hamlin Ct.Sunnyvale, CA [email protected]

Program Vice ChairShankar Hemmady Synopsys, Inc.700 East Middlefield Rd. Mountain View, CA [email protected]

Publicity/Marketing ChairBarbara Benjamin HighPointe Communications14359 SE Donatello LoopHappy Valley, OR [email protected]

Tutorial/Panel ChairStanley J. Krolikoski, Ph.D.Cadence Design Systems, Inc.2655 Seely Ave.San Jose, CA 95134 408-944-7260 [email protected]

Steering Committee

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Program Committee

Dan BenuaSynopsys, Inc.Hillsboro, OR

J. BhaskereSilicon Corp.Allentown, PA

Shalom BrestickerIntel Corp.Jerusalem, Israel

Kenneth ChangCadence Design Systems, Inc.San Jose, CA

Ben ChenCisco Systems, Inc.San Jose, CA

Clifford E. CummingsSunburst Design, Inc.Beaverton, OR

Joanne E. DeGroatThe Ohio State Univ.Columbus, OH

Jack DonovanTBD EnterprisesRound Rock, TX

Harry FosterMentor Graphics Corp.Plano, TX

JL GrayVerilab, Inc.Austin, TX

ning GuoParadigm Works, Inc.Shrewsbury, MA

Kaiming HoFraunhofer IISErlangen, Germany

Bhanu KapoorMimasicRichardson, TX

Kelly LarsonMediaTek Wireless, Inc.Austin, TX

Paul MarriottXtremeEDA Corp.Ottawa, ON, Canada

Don MillsMicrochip Technology, Inc.Chandler, AZ

Dave RichMentor Graphics Corp.Fremont, CA

Erik Seligman Intel Corp.Hillsboro, OR

alicia StrangMarvell Semiconductor, Inc.Aliso Viejo, CA

Greg TumbushTumbush Enterprises, LLCColorado Springs, CO

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Accellera, the sponsor of DVCon, celebrates its ten years of Electronic Design Automation (EDA) and Intellectual Property (IP) standards development at DVCon 2010.

Since the organization was formed through the unification of Open Verilog International and VHDL International, Accellera has delivered on its promises to focus on identifying new standards, to develop standards and to foster the adoption of new methodologies, resulting in many widely adopted EDA standards that have been transferred to and ratified by the IEEE. On June 11, 2009, Accellera announced a merger with The SPIRIT Consortium to further extend the development of its EDA standards to IP deployment and reuse.

Accellera’s mission is to drive the worldwide development and use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. Its Board guides all the operations and activities of the organization, and is comprised of representatives from ASIC manufacturers, systems companies and design tool vendors.

MembershipAccellera’s members directly influence development of the most important and widely used standards in the EDA industry. Member companies protect and leverage their investment in design methodologies through their funding. Accellera members have a high level of visibility in the EDA and IP industries as active participants in Accellera-sponsored activities and as contributors. Join now!

http://www.accellera.org/join/

Technical CommitteesAccellera Technical Committees (TC) develops, updates and extends EDA and IP standards. Accellera supports the activities of IEEE working groups and cooperates with other EDA industry standards groups.EDA and IP standards that are under active development include: SystemRDL™ (Register Description Language), IPtagging, Interface Technical Committee (ITC), Open Verification Library (OVL), Unified Coverage Interoperability (UCI), Verilog Analog/Mixed Signal (AMS), Verification IP (VIP) and IP-XACT™.

Conference Sponsor

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Room: Pine/Cedar Time: 12:00pm - 1:30pmaccellera Standards Update and 10 year anniversary CelebrationOrganizers:

Lynn Horobin - AccelleraDavid Lin - Accellera Board Representative, Denali Software, Inc.

Come join Accellera, sponsor of the Design & Verification Conference and the industry’s leading EDA and IP standards organization, as we celebrate 10 years of standards development and provide an update of our current standards activity, including the recent merger with SPIRIT and progress towards the development of a standard Verification IP (VIP) methodology.

Speakers: Shrenik Mehta - Accellera Chair, Sun Microsystems, Inc.Karen Pieper - Accellera Technical Committee Chair, Tabula, Inc.

Accellera Luncheon

Sponsored by:

Room: Pine/Cedar Ballroom Tuesday, February 23 Time: 12:00 - 1:30pm

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Colocated Event - North American SystemC User Group (NASCUG) Meeting Event: 8:30am - 12:30pm (Fir Ballroom)

Monday, February 22, 2010

Fir BallroomOak Ballroom Pine BallroomTutorial 2

The OSCI TLM-2.0 Standard and Synthesis Subset

Tutorial 3

Achieving Productivity Gains Through Formal Assertion-Based Verification (ABV)

Tutorial 1

Advanced Verification Techniques Using VMM

Sponsored by: Sponsored by: Sponsored by:

1:30TO5:00pm

Reception: 5:00 - 6:00pm (Gateway Foyer)

Registration Hours: 12:30 - 6:30pm (Bayshore Foyer)

We added one more day!Join us for three Sponsored Tutorials!

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Registration Hours: 7:00am - 6:30pm (Bayshore Foyer)

DVCon Expo: 2:00 - 6:30pm (Bayshore Ballroom)

Tuesday, February 23, 2010

8:30amTO

12:00pm

1:30TO5:00pm

Reception: 5:00 - 6:30pm (Bayshore Ballroom)

Fir Ballroom Oak Ballroom

Tutorial 4

Experience with VIP Interoperability Best Practices

Tutorial 7

A Step-By-Step Guide to Advanced Verfication

Tutorial 5

FPGA-based Rapid Prototyping Made Easy:A Hands-On Tutorial

Tutorial 6

OVM Advanced Applications

Accellera Standards Update and 10 year Anniversary Celebration Luncheon12:00 - 1:30pm (Pine/Cedar Ballroom)

Sponsored by:

Sponsored by:

Sponsored by:

Co-Sponsored by:

Sponsored by:Sponsored by:

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Reception: 5:00 - 6:30pm (Bayshore Ballroom)

Coffee Break: 3:00 - 3:30pm

Fir Ballroom Oak Ballroom

Session 1

SystemC/TLM Based Approaches

Session 3

User Case Studies - I

Keynote address (Oak/Fir Ballroom)

“Breaking Through the Efficiency Barrier “ Lip-Bu Tan - President and Chief Executive Officer, Cadence Design Systems, Inc.

Industry Leaders Panel: “What Keeps You Up At Night?”(Oak/Fir Ballroom)

Lunch Presentation: 12:30 - 1:45pm (Pine/Cedar Ballroom)

Session 2

Using SystemVerilog

Session 4

Multiple Languages

Coffee Break: 10:30 - 11:00am

DVCon Expo: 2:00 - 6:30pm (Bayshore Ballroom)

9:00TO

10:30am

8:45am

11:00amTO

12:30pm

2:00TO3:00pm

3:30TO5:00pm

Wednesday, February 24, 2010

Opening Session

Sponsored by:

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Closing Session/Best Paper Award: 5:00 - 6:00pm (Donner/Siskiyou Ballroom)

Donner Ballroom Cascade Ballroom Siskiyou Ballroom

Session 5

Formal/Semiformal Methods - I

Session 8

Formal/Semiformal Methods - II

Session 11

Assertions

Panel: Ever-Onward! Minimizing Verification Time and Effort(Donner/Siskiyou Ballroom)

“Real-World Verification” Luncheon: 12:00 - 1:30pm (Pine/Cedar Ballroom)

Session 7

Potpourri

Session 10

Low Power Verification

Session 13

User Case Studies - III

Session 6

User Case Studies - II

Session 9

Methodology - I

Session 12

Methodology - II

Coffee Break: 10:00 - 10:30am

Coffee Break: 3:00 - 3:30pm

8:30TO

10:00am

10:30amTO

12:00pm

1:30TO3:00pm

3:30TO5:00pm

Thursday, February 25, 2010

Sponsored by:

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Room: Oak Ballroom Time: 1:30 - 5:00pmTutorial 1 • advanced Verification Techniques

Using VMMOrganizer:

Rob Hurley - Doulos A tutorial on advanced verification techniques based on the latest VMM release.

INTRODUCTION With verification complexity increasing for each new design, verification engineers must continuously take advantage of advances in verification methodologies to stay productive. The VMM methodology first introduced in 2005 and deployed on many successful designs has evolved to meet growing verification requirements. The latest release of VMM enables higher productivity with SystemC/SystemVerilog TLM2 support, enhanced block-to-system reuse, more ease-of-use features and an enhanced register abstraction layer. Each speaker will focus on a set of new features in the latest release of the VMM methodology and show how they can be used to solve real-world verification challenges.

LEARNING OBJECTIVES To help verification engineers get maximum benefit from VMM, this tutorial provides application-oriented information on key VMM features that will boost engineers’ productivity and encourage reuse throughout a project’s life-cycle and across projects. Attendees will be provided with theoretical background, familiarity with extended VMM features, and a selection of real-world examples of best-practice VMM usage, giving them confidence to begin using those features in their own projects.

Speakers: Doug Smith - DoulosJL Gray - Verilab, Inc.Faisal Haque - Verification CentralAmbar Sarkar - Paradigm Works, Inc.

Monday, February 22, 2010Sponsored by:

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Room: Fir Ballroom Time: 1:30 - 5:00pmTutorial 2 • The OSCI TLM-2.0 Standard and

Synthesis SubsetOrganizer:

Steve Svoboda - Cadence Design Systems, Inc.

The current resurgence of high-level synthesis tools under the label of “ESL Synthesis” is being linked in the minds of many observers to the success of the OSCI TLM standard. There has also recently been a synthesis subset published by the OSCI Synthesis Working Group. With these events in mind, we explore the lessons being learned from the practical adoption of the TLM-2.0 standard, the resurgence of SystemC synthesis, and the synergy between the two.

We start with a brief review of SystemC and the TLM-2.0 standard for newcomers. Topics covered will be based on the most frequently asked questions concerning the current TLM-2.0 standard, such as: when to use the base protocol and when to create a new protocol, how to extend the generic payload, how to use a memory manager, how best to pass transactions through interconnect components, and how to model non-bus-based communication.

We continue with a review of the new OSCI Synthesis subset developed by the Synthesis Working Group. We will review supported language constructs as well as how to manage processes, clocks, resets, etc. We also discuss how the SystemC synthesizable subset fits within the overall context of the different abstraction levels defined for TLM.

Speakers: John Aynsley - DoulosMichael Meredith - Forte Design SystemsMichael McNamara - Cadence Design Systems, Inc.


Sponsored by:

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Room: Pine Ballroom Time: 1:30 - 5:00pmTutorial 3 • achieving Productivity Gains Through

Formal assertion-Based Verification (aBV)Organizer:

Michael Siegel - OneSpin Solutions

This tutorial gives a practical introduction to Formal ABV and demonstrates recent advances which deliver significant, every-day productivity gains to design and verification engineers. Using design verification examples and OneSpin’s 360 MV tool, we describe simple use cases and applications which reduce verification effort compared to simulation, and which are effective starting points for Formal ABV newcomers.

We also outline the productivity gains achieved by the use of more advanced transaction-level assertions. We present a simple SystemVerilog Assertion-modeling layer that enables users to develop such assertions directly from timing diagrams, easing assertion development, readability and maintenance. We also present powerful root cause analysis techniques critical to the efficient debug of advanced transaction-level SVAs.

These techniques also enable non-experts to leverage high-level assertions to increase verification productivity and design confidence.

Finally, we describe a unique, closed-loop Formal ABV process for the efficient, systematic verification of high-level design operations and transactions. You will learn how this process (1) simplifies verification planning, (2) guides high-coverage assertion development and (3) enables automatic detection of verification gaps in assertion sets to achieve earlier verification closure, obsoleting high-effort, error-prone manual approaches to increase verification coverage.

Join this tutorial to discuss how to reduce RTL analysis and verification effort in your daily work. If you are new to Formal ABV, you will learn how to best get started. If you already use formal techniques, you will learn how to achieve additional productivity gains and higher verification confidence.

Speaker: Anders Nordstrom, Sarah Li - OneSpin Solutions

Sponsored by:


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Room: Fir Ballroom Time: 8:30am - 12:00pmTutorial 4 • Experience with VIP Interoperability

Best PracticesOrganizers:

Yatin Trivedi - AccelleraStan Krolikoski - AccelleraDennis Brophy - AccelleraDavid Lin - Accellera

Accellera’s Verification IP Technical Subcommittee (VIP-TSC) released its Best Practices document in August 2009.

This was a collective effort by the TSC members to address the real problem of integrating Verification IP components built using VMM or OVM base classes under a single verification environment. It contains an entire chapter devoted to introducing the high level concepts of interoperability and component integration. It outlines a process that the verification environment writer can use to determine which cross-referenced best practice sub-chapter(s) applies to his/her specific integration challenge.

The main chapter of the document contains twelve sub-chapters dealing with the most common interoperability issues from phase synchronization to data conversion, communication, and messaging. It also contains an API to outline the interoperability library.

We, and our colleagues, will share our experiences (See Note 1) of using the recommendations in the Best Practices document on real life projects - what worked, what came up short, and our insights into making it better. We will also present our thoughts on any additional efforts necessary to make the verification components/environments easily interoperable.

Speakers: Thomas Alsop - Intel Corp.Edgar Jimenez - Freescale Semiconductors, Inc.Sharon Rosenberg - Cadence Design Systems, Inc.Janick Bergeron - Synopsys, Inc.


Sponsored by:

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Room: Oak Ballroom Time: 8:30am - 12:00pmTutorial 5 • Rapid Prototyping Made Easy:

a Hands-On TutorialOrganizer:

Neil Songcuan - Synopsys, Inc.

The success of large-budget ASIC projects depends on the up-front choices made for their verification. Because of the increase in design complexity, speed, and large amounts of embedded software in today’s designs, the choice of the hardware-assisted verification method to be used is more important than ever before. This technical hands-on tutorial, designed for SoC design and verification engineers, system validation engineers and software and firmware developers, will detail how rapid prototyping solves the challenges associated with traditional verification approaches and brings together all of the critical components into a complete and affordable solution that enables you to find even the hardest-to-find hardware bugs, start software development earlier in the design cycle and integrate hardware and software well ahead of chip fabrication.

To fully demonstrate how rapid prototyping is used for pre-silicon validation and software development, multiple laptops with pre-installed software and actual rapid prototyping boards will be available in a workshop lab environment. The tutorial is based on a synthesizable model of a 32-bit processor compliant with the SPARC V8 architecture and will guide users on how to take the design from implementation to full debug visibility.

After completing this unique hands-on tutorial, users will have a comprehensive understanding of how the different components of an integrated software and hardware solution fit together into a seamless debug flow.

Seating for this workshop is limited to 40 registrants.

Due to the proprietary nature of the discussions, the presenting company reserves the right to refuse access to employees or contractors of competitors.

Speaker: Neil Songcuan, Frank Schirrmeister - Synopsys, Inc.


Sponsored by:

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Room: Fir Ballroom Time: 1:30 - 5:00pmTutorial 6 • OVM advanced applications

Organizer: Adam Sherer - Cadence Design Systems, Inc.

As users become more adept at building and reusing OVM-based verification IP, it is natural to leverage that experience to related parts of the verification process. The most obvious one is to apply the OVM to multiple languages, including SystemVerilog, e, and SystemC, enabling the widest possible reuse among verification teams. In turn, the advanced concepts in the OVM are leading teams to seek OVM-based VIP to replace more simplistic bus-functional model VIP for protocol verification. Just as the OVM can be used to steer a test to a specific state for formal ABV, it can also steer a test to a specific set of sequences for low-power verification. The OVM is also unique in its ability to scale to system verification which is where the OVM accelerated application is needed with its ability to leverage hardware acceleration.

Attendees of this techtorial will learn how to apply the OVM in each of these advanced applications - multi-language, VIP, ABV, low-power, and acceleration along with code examples and demonstrations that leverage an IDE to increase coding efficiency and correctness.

Speakers: To Be Announced


Sponsored by:

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Room: Oak Ballroom Time: 1:30 - 5:00pmTutorial 7 • a Step-By-Step Guide to advanced

VerficationOrganizer:

Rebecca Granquist - Mentor Graphics Corp.In order to improve verification productivity, engineers are faced with a classic choice: work harder or work smarter. Working harder means either putting in more hours or determining how to apply the same verification techniques you’ve been using to larger and more complex designs without going insane. Working smarter, on the other hand, involves adopting new techniques and advanced technologies that complement what you’re used to doing, but rely on tools and automation to accomplish the necessary efficiencies.This tutorial will demonstrate an advanced verification flow, showing how the latest verification technologies can be combined within an efficient methodology to provide a highly effective and productive verification of an SoC design. Beginning with a discussion of verification requirements, we will show how to create a verification plan that involves requirements beyond just random constraints and coverage, and to build a comprehensive verification environment to meet those requirements.

The tutorial will cover the following:• Tracking requirements from design requirements to initial

verification plan to full electronic closure • Creating and verifying RTL blocks synthesized from C++ models

using high level synthesis • Creating and reusing OVM compatible verification components for

block and system-level verification• Applying automated Formal verification and Clock Domain

Crossing verification to automate key block-level verification challenges and increase functional coverage

• Integrating multiple block-level verification IP into a system-level environment

• Generating efficient coverage-driven stimulus• Debugging processor-based system tests and hardware with an

overall 6-10x speedup in the time spent finding a defect• Accelerating the OVM transaction-based testbench using hardware

emulation• Managing the process through a metric-driven verification flow

providing automation, visibility, control and predictability

Speaker: Tom Fitzpatrick - Mentor Graphics Corp.


Sponsored by:

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Room: Fir Ballroom Time: 9:00 - 10:30amSession 1• SystemC/TLM based approaches

1.1 Defining TLM+Wolfgang Ecker, Volkan Esen, Robert C. Schwencker, Michael Velten - Infineon Technologies AG

1.2 Bridging the Gap between TLM-2.0 aT Models and RTL - Experiments and OpportunitiesZhu Zhou, Atul Kwatra, Rajesh Gadiyar, Paul Heraty - Intel Corp.

1.3 Transaction-Level State Charts in UML and SystemC with Zero-Time EvaluationRainer Findenig - Upper Austria Univ. of Applied Sciences, Thomas Leitner, Michael Velten, Wolfgang Ecker - Infineon Technologies AG

Room: Oak Ballroom Time: 9:00 - 10:30amSession 2• Using SystemVerilog

2.1 The Problems with Lack of Multiple Inheritance in SystemVerilog and a SolutionDave Rich - Mentor Graphics Corp.

2.2 SystemVerilog-2009 Enhancements: Priority/Unique/Unique0Clifford E. Cummings - Sunburst Designs, Inc.

2.3 Using SystemVerilog “Interfaces” as Object-Oriented RTL ModulesGeoff L. Barnes - Thales Systems Canada


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Room: Fir Ballroom Time: 11:00am - 12:30pmSession 3• User Case Studies - I

3.1 Strategy and Environment for SoC Mixed-Signal Validation: a Case StudyErik A. McShane, Srini Iyengar - Intel Corp.

3.2 Verifying Clock-Domain Crossing at RTL IP Level Using Constraint-Driven MethodologyJean-François Vizier, Thomas Goust - ST-Ericsson

3.3 Experiencing Checkers for a Cache Controller DesignSrinivasan Venkataramanan - CVC Pvt. Ltd.Ben Cohen - VhdlCohen PublishingAjeetha Kumari - Design Verification ConsultantLisa Piper - Consultant

Room: Oak Ballroom Time: 11:00am - 12:30pmSession 4• Multiple Languages

4.1 SystemVerilog Meets C++: Re-Use of Existing C/C++ Models Just Got EasierJohn aynsley - Doulos

4.2 apples Versus apples HVL Comparison Finally arrivesBrett Lammers, Riccardo Oddone, Adam Sherer - Cadence Design Systems, Inc.

4.3 Comprehensive SystemVerilog-SystemC-VHDL Mixed-Language Design MethodologyRudra Mukherjee, Gaurav Kumar Verma, Sachin Kakkar - Mentor Graphics Corp.


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Lunch Presentation

Room: Pine/Cedar Time: 12:00pm - 1:30pmCadence Lunch Presentation

TO BE annOUnCED

Sponsored by:

Room: Pine/Cedar Ballroom Wednesday, February 24 Time: 12:30 - 1:45pm

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Keynote Address

Title: Breaking Through the Efficiency Barrier Lip-Bu Tan - President and Chief Executive Officer, Cadence Design Systems, Inc.

Lip-Bu Tan is President and Chief Executive Officer of Cadence® Design Systems, Inc. A member of the Cadence Board of Directors since 2004, he is also the chairman of Walden International, a venture capital firm he founded in 1987.

Tan received an M.S. in nuclear engineering from the Massachusetts Institute of Technology, an MBA from the University of San Francisco, and a B.S. from Nanyang University in Singapore. He serves on the Board of Directors of both the Electronic Design Automation Consortium (EDAC) and the Global Semiconductor Association (GSA).

With world markets beginning to show signs of improved conditions, the electronics industry must anticipate a strong rebound and prepare for significant growth throughout 2011 – and beyond. To effectively manage this upcoming shift, the industry must approach the product development process much differently. The classic “brute force” methods cannot scale to support the complexity of today’s SoCs and Systems. These traditional methods result in mounting costs and unpredictable schedules that are detrimental to profitability. In this session, Cadence President and CEO Lip-Bu Tan will share his insights on how today’s electronics companies can break through the efficiency barrier formed by insurmountable complexity and costs. He will explain how embracing higher abstractions of design and verification, reuse, metrics, and up-front tradeoffs can boost productivity and reduce tail-end iterations. Learn how these improvements will result in reduced SoC realization costs and increased predictability and ultimately prepare the industry to drive the next wave of technology innovation.

Room: Oak/Fir Ballroom Wednesday, February 24 Time: 2:00 - 3:00pm

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Industry Leaders Panel

Room: Pine/Cedar Time: 12:00pm - 1:30pm“What Keeps You Up at night?”Moderator:

JL Gray - Verilab, Inc. This year’s panel will ask the panelists “What Keeps You Up At Night?” and other pressing questions about what they see as the market’s challenges and opportunities, as well as no-holds-barred questions from the audience.

Panelists: To Be Announced

Room: Oak/Fir Ballroom Wednesday, February 24 Time: 3:30 - 5:00pm

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Room: Donner Ballroom Time: 8:30 - 10:00amSession 5• Formal/Semiformal Methods - I

5.1 Formal Methods to Verify the Power Manager for an Embedded Multiprocessor ClusterKesava R. Talupuru - MIPS Technologies, Inc.

5.2 Combining Simulation with Formal Techniques to Reduce the Overall Verification Cycleaneet agarwal - Texas Instruments, Inc.Gaurav Gupta - Synopsys, Inc.

5.3 Designers Work Less for Quality Formal Equivalence CheckingOrly Cohen - Intel Corp. IsraelMoran Gordon - Intel Corp.Michael Lifshits, Alexander Nadel - Intel Corp. IsraelVadim Ryvchin - Intel Corp.

Room: Cascade Ballroom Time: 8:30 - 10:00amSession 6• User Case Studies - II

6.1 Using Covergroups Inside a DUT (without Modifying the DUT) for Coverage Driven Testing with an OVM TestbenchMike Baird - Willamette HDL

6.2 Using SystemVerilog Packages In Real Verification ProjectsKaiming Ho - Fraunhofer IIS

6.3 Low Power Verification with UPF: Principle and PracticeJianfeng Liu, Mi-Sook Hong, Bonghyun Lee, Jung Yun Choi, Hyosik Won, Kyu Myung Choi - Samsung Harsha Vardhan, Aditya Kher - Synopsys, Inc.


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Room: Siskiyou Ballroom Time: 8:30 - 10:00amSession 7• Potpourri

7.1 Where OOP Falls Short of Verification needsMatan Vax - Cadence Design Systems, Inc.

7.2 Source Control... $100; Regression Script... $500; Good automated Release Steps... Priceless!Jeffrey J. Wren - Paradigm Works, Inc.

7.3 automatic Verification for assertion Based Verification: How a Spirit Standard Extension Can Help?Sofiene Mejri, Mirella Negro Marcigaglia - STMicroelectronics

Room: Donner Ballroom Time: 10:30am - 12:00pmSession 8• Formal/Semiformal Methods - II

8.1 Reusing Testbench Components in Hybrid-Formal EnvironmentRitero Chi - Entropic Communications, Inc.Xiaolin Chen - Synopsys, Inc.

8.2 Using Model Checking to Prove Constraints of Combinational Equivalence Checkingxiushan Feng, Joseph Gutierrez - Advanced Micro Devices, Inc.Mel Pratt, Mark Eslinger - Mentor Graphics Corp.

8.3 an Experience of Complex Design Validation: How to Make Semiformal Verification WorkSabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, Alexander Nadel - Intel Corp. Israel


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Room: Cascade Ballroom Time: 10:30am - 12:00pmSession 9• Methodology - I

9.1 The OVM-VMM Interoperability Library:Bridging the GapTom Fitzpatrick, adam Erickson - Mentor Graphics Corp.

9.2 Testbench Configuration MantraStephen J. Donofrio - Paradigm Works, Inc.

9.3 Tweak-Free Reuse Using OVMSharon Rosenberg - Cadence Design Systems, Inc.Cristian Amitroaie - AMIQ srl

Room: Siskiyou Ballroom Time: 10:30am - 12:00pmSession 10• Low Power Verification

10.1 Understanding the Low Power abstractionGary Delp - Silver Loon SystemsErich Marschner, Ken Bakalar - Mentor Graphics Corp.

10.2 Static Power-Management Verification of Cypress’ PSOC© Programmable System-on-Chip for Embedded SystemsJohnie au - Cypress Semiconductor Corp.Prapanna Tiwari - Synopsys, Inc.

10.3 Mixed-Signal Verification of Dynamic adaptive Power Management in Low Power SoCneyaz Khan - Cadence Design Systems, Inc.


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“Real-World Verification” Luncheon Organizer: Michael Sanie - Synopsys, Inc.

Synopsys invites you to join us for lunch and a highly informative session covering the latest verification trends, challenges and solutions. You will hear leading industry experts discuss complex real-world verification challenges and present insights into best practices that help address them. This luncheon provides a valuable opportunity to learn about new innovations in verification technology that enable improved performance and productivity. If you are a verification engineer or manager, you won’t want to miss this special event.

Lunch PresentationRoom: Pine/Cedar Ballroom Thursday, February 25 Time: 12:00 - 1:30pm

Sponsored by:

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Room: Donner Ballroom Time: 1:30 - 3:00pmSession 11• assertions

11.1 IEEE 1800-2009 SystemVerilog: assertion-Based Checker LibrariesEduard Cerny, Surrendra Dudani - Synopsys, Inc.Dmitry Korchemny - Intel Corp. Israel

11.2 asynchronous Behaviors Meet Their Match with SystemVerilog assertionsDoug Smith - Doulos

11.3 Using assertions in an active Way to Design and Verify Interface between analog and Digital BlocksHyundon Kim - Samsung Wesley Park, Jiang Long - Mentor Graphics Corp.Chi Ho Cha, Jae Beom Kim, Byeong Min, Kyu Myung Choi - Samsung

Room: Cascade Ballroom Time: 1:30 - 3:00pmSession 12• Methodology - II

12.1 Stimulating Scenarios in the OVM and VMMJL Gray, Scott Roland - Verilab, Inc.

12.2 Effects of abstraction in Stimulus Generation of Layered Protocols within OVMJosh Rensch, Jesse Prusi - Lockheed Martin Corp.Mike McMahon, Andreas Meyer - Mentor Graphics Corp.

12.3 You are In a Maze of Twisty Little Sequences, all alike - or Layering Sequences for Stimulus abstractionRich Edelman, Adam Rose, Andreas Meyer, Raghu Arde ishar, Jason Polychronopoulos - Mentor Graphics Corp.


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Room: Siskiyou Ballroom Time: 1:30 - 3:00pmSession 13• User Case Studies - III

13.1 Functional Coverage - Without SystemVerilog!Alan P. Fitch, Doug Smith - Doulos

13.2 Efficient Simulation Based Verification by ReorderingChao Yan - Univ. of British ColumbiaKevin Jones - Rambus, Inc.

13.3 a Holistic View of Mixed-Language IP ReusePankaj Singh - Infineon Technologies AGGaurav Kumar Verma - Mentor Graphics Corp.


Room: Pine/Cedar Time: 12:00pm - 1:30pmPanEL: Ever-Onward! Minimizing Verification Time and EffortOrganizer/Moderator:

Brian Bailey - Brian Bailey Consulting and TechBites.comAccording to the “general” consensus, companies are spending 70% of their total time and effort on verification and the trend is moving upwards. While IP and reuse has helped constrain total design times, it has, if anything, had a detrimental effect on verification. How do we ensure that we minimize the total amount of time, effort and engineering expense spent in verification, while maximizing the total design quality? Possible ways out include a greater use of formal verification, migration to ESL, additional use of emulation and physical prototyping, intelligent testbenches, etc. While it can be argued that each of these can add to verification productivity, this panel will attempt to decide which emerging techniques provides the best value for your money.

Each of the panelists has experience in various approaches and several different points of view.

Panelists: Janick Bergeron - Synopsys, Inc.JL Gray - Verilab, Inc.Rajeev Ranjan - Jasper Design Automation, Inc.Ran Avinun - Cadence Design Systems, Inc.Shawn McCloud - Mentor Graphics Corp.

Room: Donner/Siskiyou Ballroom Time: 3:30 - 5:00pm

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Cadence Design Systems, Inc.Consultants’ Corner Innovative Logic, Inc.Denali Software, Inc.Dini GroupDoulos EDACafe.comeInfochips Inc.EVE

ExpertIO, Inc.GateRocket, Inc.Jasper Design AutomationMentor Graphics Corp.OneSpin SolutionsOSCIReal Intent, Inc.SpringSoft, Inc.Synopsys, Inc.

505402

702904501705804902

8058026019015021002602701905

The DVCon Expo 2010 consists of vendors displaying the latest in Hardware Description Languages, Hardware Verification Languages and EDA tools for the design and verification of electronic systems and integrated circuits.

Tuesday, February 23 2:00 - 6:30pmWednesday, February 24 2:00 - 6:30pm

Bayshore Ballroom

Exhibiting Companies (as of December 3, 2009)

Expo Hours

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Denali Software, Inc. Booth # 702 1000 Hamlin Ct. Sunnyvale, Ca 94089 408-743-4200 www.denali.comDenali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denalis EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world. For more information about Denali, please visit www.denali.com.

Dini Group Booth # 904 7469 Draper ave. La Jolla, Ca 92037 858-454-3419 www.dinigroup.comThe Dini Group offers advanced FPGA boards for ASIC Prototyping, Algorithmic Acceleration, IP Validation, Reconfigurable, and Networked Computing. These boards feature the latest Xilinx, Virtex-6 and Altera, Stratix IV technologies, and offer ASIC gate counts of over 100 Million on a single board. Since 1998, from their offices in La Jolla California, Dini Group employees have supplied over 5 billion ASIC gates, and driven the costs down to less than ¼ cent/ASIC gate.

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Cadence Design Systems, Inc. Booth # 505 2655 Seely ave. San Jose, Ca 95134 408-943-1234 www.cadence.com

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world. More information about the company, its products, and its services is available at www.cadence.com.

Consultants’ Corner Booth # 402 Innovative Logic, Inc. 2953 Bunker Hill Lane, Ste. 400 Santa Clara, Ca 95054 408-824-1313 www.inno-logic.comInnovative Logic is the leading provider of reusable standard based IP solutions as well as high quality and reliable design services in ASIC, FPGA, and Embedded Systems Design. Our flexible business model allows you to choose onsite, offsite, or offshore consulting. We have expertise in Logic Design & Verification, Design for Testability (DFT), Circuit Design, Physical Design & Verification, Board Design, and FPGA Design. Innovative Logic is headquartered in Santa Clara, CA and has state of art Design Centers in Bangalore, India. For details, please visit our website at www.inno-logic.com.

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Doulos Booth # 501 16165 Monterey Rd., Ste. 109 Morgan Hill, Ca 95020 408-776-1370 www.doulos.comDoulos is the global leader for the development and delivery of world class training solutions for SoC, FPGA and ASIC design and verification. Fully independent, Doulos sets the industry standard for high quality training including SystemVerilog, Verilog®, VHDL, SystemCTM , and ARM-based design. Since 1991, Doulos has contributed to the success of more than 700 companies across 35 countries. The natural partner for leading tool and technology companies, Doulos schedules classes across the US and Europe and delivers in-house training world-wide.

EDaCafe.com Booth # 705 496 Salmar ave. Campbell Ca 95008 408-850-9246 www.edacafe.comThousands of IC, and system designers visit EDACafé.com to learn about the latest company news and research the latest design tools and services. As the #1 EDA portal it attracts more than 75,000 unique visitors each month and leverages TechJobsCafe.com to bring you targeted job opportunities. EDACafé reaches out to more than 30,000+ EDA professionals with its daily CaféNews. EDACafe staff will be doing video interviews of industry executives at its booth. Please visit to hear all the conference buzz.

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eInfochips Inc. Booth # 804 1230 Midas Way, Ste. 200 Sunnyvale, Ca 94085 408-496-1882 www.einfochips.comeInfochips is a technology design services & solutions company offering IPs & services in Application Software, Embedded System and ASIC/FPGA since 1995. Our ASIC capabilities extend from spec to silicon to system, with expertise spanning ASIC/SoC/FPGA RTL Design, Verification, Physical Design, ASIC Prototyping (pre & post silicon validation), system-level validation and Design and Verification IP development. With over 14 years in existence, close to 2500 man-years experience and over 145 first pass silicon successes across various industries, einfochips is your right choice for managed ASIC design & verification services & solutions.

EVE Booth # 902 2290 n. First St. San Jose, Ca 95131 408-457-3200 www.eve-usa.comEVE offers a selection of hardware-assisted verification solutions, from acceleration and fast emulation to easy-to-use prototyping with the most cycles per dollar. Its products shorten the verification cycle of complex chips and electronic systems design and work with Verilog, SystemVerilog and VHDL-based simulators. ZeBu (for zero bugs) is accessible to SoC engineers and embedded software developers and used throughout the design cycle by groups with modest budgets. Designs target a variety of fast-paced markets, including networking, communications, multi-media, graphics, computer and consumer.

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ExpertIO, Inc. Booth # 805 www.expertio.com

ExpertIO, Inc. is a leading edge provider of high quality Verification IP, specializing in PCI-Express, Networking, and Storage protocols. When first pass success is required, ExpertIO is the company to trust.Looking for DV experts? ExpertIO also offers Design and Verification consulting services for ASICs, SoC, FPGAs. With an extensive industry experience and a proven track record, you can expect the highest quality results.

GateRocket, Inc. Booth # 802 19 Crosby Dr., Ste. 100 Bedford, Ma 01730 781-908-0082 www.gaterocket.comGateRocket is the only company that focuses exclusively on verification and debugging solutions for today’s most advanced FPGAs. GateRocket’s products work seamlessly with your existing HDL simulation environment to identify bugs in your RTL, IP and tool flow that would otherwise slip through to your system-integration lab. With GateRocket’s unique “soft-patch” capability you’ll be able to try out fixes to your FPGA without going through lengthy synthesis and P&R runs. As a result you’ll accelerate the bring-up process and shave months off your verification and debugging schedule.

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Jasper Design automation Booth # 601 100 View St., Ste. 101 Mountain View, Ca 94041 650-966-0200 www.jasper-da.comJasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. See how JasperGold, JasperCore, and ActiveDesign deliver targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, Japan and Korea. Visit www.jasper-da.com

Mentor Graphics Corp. Booth # 901 8005 SW Boeckman Rd. Wilsonville, OR 97070 503-685-1907 www.mentor.comThe Mentor Graphics® Questa® functional verification platform, 0-In® functional coverage tools, and Veloce®, a high-performance system verification solution, deliver the most comprehensive verification flow in the industry. Mentor supports the Open Verification Methodology (OVM), which is the first truly open, interoperable, and proven verification methodology based on SystemVerilog IEEE 1800-2005. Mentor’s portfolio of electronic system level (ESL) technologies, including Catapult® C Synthesis and the Vista platform, complement the OVM to enable design and verification at higher levels of abstraction. For more information, go to www.mentor.com.

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OneSpin Solutions Booth # 502 Theresienhoehe 12 D-80339 Munich Germany +49-89-99-013-0 www.onespin-solutions.comOneSpin’s 360 MV product family is the most comprehensive formal assertion-based verification (ABV) solution for ASIC/FPGA designs available today. It supports the full range of formal ABV applications from early automatic RTL analysis all the way to certified gap-free IP verification providing entry points for formal ABV starters, as well as unique, patented capabilities for experienced users and experts. Come see our new, automated RootCauseAnalyzerTM that speeds debug of SystemVerilog Assertions and RTL designs by up to 10X.

OSCI Booth # 1002 1455 Carrington Circle San Jose, Ca 95125 408-266-9753 www.systemc.orgOSCI is dedicated to advancing SystemC as an open standard for system-level modeling, design and verification. Leading companies use SystemC for architectural exploration and to deliver high-performance interoperable models of their hardware blocks at various abstraction levels. With approval of the IEEE 1666-2005 Standard for SystemC, OSCI achieved a key milestone in advancing electronic design and continues to make contributions through the diligent efforts of its technical working groups: Analog/Mixed-signal; Configuration, Control and Inspection; Language; Synthesis; Transaction-level Modeling; and Verification. To find out more go to www.systemc.org.

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Real Intent, Inc. Booth # 602 505 north Mathilda ave., Ste. 210 Sunnyvale, Ca 94085 408-830-0700 www.realintent.comReal Intent, Inc. delivers verification confidence by providing automatic verification solutions for ASIC and FPGA designs. Through innovation and unique application of formal techniques, the Real Intent tools provide powerful solutions to important design and verification problems. Exhibited products at DVCon include Ascent for early functional verification, Meridian for Clock Domain Crossing verification; and PureTime for design constraints validation. In use at over 40 major customers worldwide, Real Intent tools help make the most complex designs possible.

SpringSoft, Inc. Booth # 701 2025 Gateway Pl., Ste. 400 San Jose, Ca 95110 408-467-7889 www.springsoft.comSpringSoft, Inc. is the leading global EDA Company that specializes in delivering unique automation technologies to the design and verification community. The Springsoft NovasTM Verification Enhancement product line focuses on providing automated debug solutions that cut debug time in half, visibility automation solutions that minimize simulation overhead, and functional qualification solutions that remove verification uncertainty. In addition, the Springsoft LakerTM Custom IC Design solutions deliver unsurpassed controllable automation for superior layout results with less effort. Visit us at booth #701.

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Synopsys, Inc. Booth # 905 700 E. Middlefield Rd. Mountain View, Ca 94043 650-584-5000 www.synopsys.comSynopsys is a world leader in software and IP for semiconductor design, verification and manufacturing. Synopsys’ comprehensive software-to-silicon verification solution delivers proven tools, IP, services and methodologies to give chip and system development teams a competitive edge in bringing products to market quickly while reducing costs and risk. Synopsys verification technology includes virtual platforms and FPGA-based ASIC prototypes for early embedded software development and system validation, high-performance multicore functional and mixed-signal simulation, low power and static verification and a large portfolio of proven system-level models and verification IP.

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North American SystemC Users Group Meeting (NASCUG)

Room: Pine/Cedar Time: 12:00pm - 1:30pmThe north american SystemC Users Group (naSCUG) provides a unique forum for sharing SystemC experiences among business, research and universities, while influencing the growth and evolution of SystemC standards. A central component of the NASCUG meeting is a number of 20 minute user experience presentations discussing practical design, modeling and verification techniques using SystemC. Several “how-to” presentations will focus on clarifying poorly understood or misused SystemC features.

TOPICS include: • Architectural Modeling with SystemC • Transaction-Level Modeling and TLM-2.0 • SystemC Analog/Mixed-signal (AMS) extensions • Software Co-Design with SystemC • Verification Techniques using SystemC • Integrating SystemC into the Design Flow • SystemC Tool Flows and Methodologies • SystemC Language Development

Registration is FREE for industry professionals. Find out more at www.nascug.org

NASCUG operates independently but works in collaboration with the Open SystemC Initiative (OSCI) to provide open forums for promoting information exchange. Our goal is to make SystemC end-users more effective through shared knowledge and collaboration.

To find out more about OSCI, visit www.systemc.org

Room: Fir Ballroom Monday, February 22 8:30am - 12:00pm

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COnFEREnCE FEES Before Jan. 29 After Jan. 29Full Conference $485 $565Student $280 $300One-day only $320 $350Exhibit Only Complimentary Exhibit Only w/Tutorial $60 /Tutorial

Conference fees include the tutorialsTUTORIaL REGISTRaTIOn - Monday, February 22 and Tuesday, February 23Monday Sponsored Tutorials include coffee breaks and reception. Tuesday Sponsored Tutorials include coffee breaks and lunch. All Tutorials include the presentation notes to the tutorial(s) you selected.

1. DVCon full conference, student full conference and one-day registration includes access to one tutorial on Monday afternoon; and two tutorials on Tuesday one morning and one afternoon tutorial. DVCon tutorial notes are not available for sale.

2. If you do not select a tutorial at the time of your registration, there is no guarantee that you will be able to add tutorials when you pick up your registration materials.

Please note for Tutorial 5: Due to the proprietary nature of the discussions, the presenting company reserves the right to refuse access to employees or contractors of Please Note: Due to the proprietary nature of the discussions, the presenting company reserves the right to refuse access to employees or contractors of competitors.

Cancellation Policy: Written requests for refunds received before January 29, 2010 will be subjected to a $35 processing fee. No refunds will be made for cancellations after January 29, 2010 and all registration fees will be forfeited.

Tutorial notes will not be distributed to attendeeswho have not selected a tutorial.

Log on to the DVCon website at www.dvcon.org for more information and to register for the conference.

Full Conference and Student registration fee includes:• Tutorials• DVCon Expo• Technical Sessions• CD Rom proceedings• Coffee breaks, Tuesday, Wednesday and Thursday luncheons, Tuesday and

Wednesday receptions.

One-day only registration fee includes:• Wednesday or Thursday• Tutorials• DVCon Expo• Technical Sessions• CD Rom proceedings• Coffee breaks, luncheon on day attending, Wednesday reception

Exhibit-only complimentary registration includes:• Access to exhibit hall on Tuesday, 2:00 - 6:30pm, and Wednesday, 2:00 - 6:30pm• Wednesday Keynote at 2:00pm• Eligibility to register for the tutorials on Monday or Tuesday. Each tutorial is $60.

Maximum of three may be selected.

Conference Registration

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2050 Gateway Place San Jose, CA 95110DoubleTree Hotel

Why stay at the conference hotel?It’s the center of conference activity, that’s why! You will be able to network easily with other attendees, and you don’t need to worry about transportation each day to get to the program and functions.

2010 ROOM RaTE:$149 Single/Double(Includes complimentary high-speed internet access.)

Shuttle ServiceFor complimentary shuttle service from the San Jose Airport to the DoubleTree Hotel, call the hotel from the courtesy phone in the baggage claim area at the airport.

Hotel Highlights• DoubleTree’s signature “Sweet Dreams” bed• Complimentary Shuttle from the San Jose International Airport• Complimentary Fitness Center• AAA Four Diamond Hotel• Parking Fees: DVCon Day Rate - $7

DoubleTree Hotel San Jose 2050 Gateway PlaceSan Jose, Ca 95110

408-453-4000www.dtsj.com

Transportation and Hotel

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Hotel FloorplanBayshore Foyer• Conference

Registration

Gateway Foyer• Monday Reception

Pine/Cedar• Tuesday Lunch• Wednesday Lunch• Thursday Lunch

Oak/Fir/Pine• Monday Tutorials• Tuesday Tutorials• WednesdayTechnical

Sessions• Wednesday Keynote• Wednesday Panel

Donner/Sisikiyou/Cascade• Thursday Technical Sessions• Thursday Panel• 2010 Best Paper Award Presentation

Bayshore Ballroom• DVCon Expo• Tuesday Cocktail

Reception• Wednesday Cocktail

Reception

We added one more day!Join us Monday, February 22 for

three Sponsored Tutorials!

Follow us on Twitter:

twitter.com/DVCon

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