First Present 80C51

7/31/2019 First Present 80C51

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Innostor Technology Corp.

80C51

Present: Chien-Yu Chen

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Innostor Technology Corporation

Outline

1. ARCHITECTURE

2. MEMORY ORGANIZATION

1. Program Memory

2. Data Memory

3. Addressing Modes

4. Instructions

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ARCHITECTURE

All 80C51 devices have separate address spaces for program anddata memory, as shown in Figures 2.

data memoryprogram memory

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Program Memory

Program memory (ROM, EPROM) can only be read, not written to.

can be up to 64k bytes.

In the 80C51, the lowest 4k bytes of program are on-chip. In the ROMless versions, all program memory is external.

The read strobe for external program memory is the

PSEN (program store enable).

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Program Memory

Figure 3 shows a map of the lower part of the Program Memory.

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Interrupt Structure

The 80C51 and its ROMless and EPROM versions have 5

interrupt sources:

2 external interrupts, 2 timer interrupts, and the serial port interrupt.

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Data Memory

Data Memory (RAM) occupies a separate address space from Program Memory.

In the 80C51, the lowest 128 bytes(00H~7FH) of data memory are

on-chip.

In the ROMless version, the lowest 128 bytes are on-chip. Up to 64k bytes of external RAM can be addressed in the external

Data Memory space.

As needed during external Data Memory accesses, theCPU generates read signal RD and write signal WR.

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Data Memory

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Data Memory

The Lower 128 bytes of RAM are present in all 80C51 devices as

mapped in Figure 7. The lowest 32 bytes are grouped into 4 banks of8

registers. Program instructions call out these registers as R0 through

R7.

The location whichstack pointer refers

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Data Memory

Figure 9 gives a brieflook at the SpecialFunction Register (SFR)space.

include the Port latches,timers, peripheral controls

etc.

can only be accessed by

direct addressing.

DPTR: DPH + DPLSP: Stack Pointer

IE: Interrupter Enable register

IP: Interrupt Priority Register

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Program Status Word

Program Status Word (PSW) contains several status bits that reflect the current state of the CPU

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Addressing Modes

Immediate Constants Ex. MOV A, #30H ;

Direct Addressing

the operand is specified by an 8-bit address field in the instruction

Onlyinternal Data RAM(00H~7FH) and SFRs can be directlyaddressed.

Ex. MOV A, 3FH ;

Indirect Addressing

the instruction specifies a register which contains the address of the

operand

Bothinternal and external RAM can be indirectly addressed.

Ex. MOV R0, #70H ; MOV A, @R0 ;

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Addressing Modes

Register Instructions carry a 3-bit to indicate one of 8 registers(R0 ~ R7)

One of four banks is selected at execution time by the two bank

select bits in the PSW (RS0 & RS1).

Ex. MOV A, R7 ;

Register-Specific Instructions

Some instructions are specific to a certain register.

no address byte is needed to point to it. The opcode itself does that.

Ex. RR A ;

Indexed Addressing

Onlyprogram Memory can be accessed with indexed addressing,

and it can only be read.

Ex. MOV A, #30H ; MOV DPTR, #300H ; MOVC A, @A+DPTR ;

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Instructions

Arithmetic Instructions

Logical Instructions

Data Transfers

Boolean Instructions

Jump Instructions

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Arithmetic Instructions

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Logical Instructions

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Data Transfer

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Data Transfer

To see how XCHand XCHD can be

used to facilitate

data manipulations,

consider first theproblem of shifting

an 8-digit BCD

number two digits

to the right.

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Data Transfer

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Boolean Instructions

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Jump Instructions

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CPU Timing

CPU Timing

All 80C51 microcontrollers have an on-chip oscillator which can

be used if desired as the clock source for the CPU.

Machine Cycles

A machine cycle consists of a sequence of 6 states, numberedS1 through S6. Each state time lasts for two oscillator periods.

Thus a machine cycle takes 12 oscillator periods or 1s if the

oscillator frequency is 12MHz.

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DP80390

DP80390 is an ultra high performance, speed optimizedsoft core of a single-chip 8-bit embedded controller.

The DP80390 has a Pipelined RISC architecture.

It supports up to 8 MB of linear code and 16 MB of linear

data spaces.

DP80390 soft core is 100% binary compatible with the

industry standard 80390 & 8051 8-bit microcontrollers.

The same C compiler was used for benchmarking of the

core vs 80C51 with the same settings.

First Present 80C51

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