First characterization of the PASTA chip for the ...€¦ · Analog TDC Time-to-Digital Converter...
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DPG Frühjahrstagung 2017, Münster 1 II. Physikalisches Institut, Justus-Liebig-Universität Gießen; 2 INFN, Sezione di Torino; 3 Forschungszentrum Jülich GmbH, Jülich, Germany First characterization of the PASTA chip for the microstrip part of the PANDA MVD Tommaso Quagli 1 , Kai-Thomas Brinkmann 1 , Daniela Calvo 2 , Valentino Di Pietro 1 , Alessandra Lai 3 , Alberto Riccardi 1 , James Ritman 3 , Angelo Rivetti 2 , Manuel Rolo 2 , Robert Schnell 1 , Tobias Stockmanns 3 , Richard Wheadon 2 , André Zambanini 3 , and Hans-Georg Zaunick 1 Tommaso Quagli II. Physikalisches Institut, JLU Heinrich-Buff-Ring 16 D-35392 Gießen [email protected] The Micro-Vertex-Detector • 4 concentric barrels and 6 forward disks • Vertex reconstruction for primary and secondary vertices • Improvement of momentum resolution and PID • Requirements: - spatial resolution (tens of µm) - good time resolution and low material budget - high radiation tolerance (10 14 n 1MeV eq / cm 2 ) Target Spectrometer Forward Spectrometer silicon microstrips silicon hybrid pixels The PANDA Experiment • Fixed target experiment • Almost 4π acceptance • Cooled antiproton beam using electron and stochastic cooling • Proton or heavy nuclear target • Momentum from 1.5 up to 15 GeV/c • Trigger-less readout at ~10 7 interactions / s First PASTA Characterizations Example of chip test signals for an injected pulse Front-end output Comparator output Start of Conversion End of Conversion PANDA STrip ASIC (PASTA) • Front-end readout chip for double-sided silicon strip sensors • Measurement concept inspired by TOFPET Chip Architecture • Number of channels: 64 • Input pitch: 63 µm • Clock frequency: 160 MHz • Rate capability: 100 kHz / ch • Time bin width: 50 - 400 ps • dE/dx measurement: ToT, 8 bits dynamic range • Front-end noise: < 600 e - • Power consumption: < 4 mW / ch • Radiation tolerance: 100 kGy (TID) • Technology: CMOS 110 nm Front-End Architecture • Paperino pippo pluto Chip Simulations 0 5 10 15 20 25 30 0 200 400 600 800 C det [pF] ENC [e - ] p-type n-type 0 10 20 30 40 0 200 400 600 800 1000 1200 Q in [fC] Time over Threshold [ns] p-type MIP n-type Electronic noise with an input charge of 4 fC, for a capacitance from 1 pF to 30 pF ToT linearity in the input charge range from 1 fC to 40 fC Preamplifier Current buffer ToT Amplifier Hysteresis Comparator Analog TDC Time-to-Digital Converter (TDC) architecture (3.125 - 9.375) ns (0.4 - 1.2) μs TDC working principle C TDC = 4 · C TAC ; I TDC = 1/32 I TAC V TDC = V TAC t TDC = 128 · t TAC PASTA Readout Systems • PASTA chips fabricated in UMC CMOS 110nm technology and assembled on dedicated test boards Two readout systems: • Labview-based Torino system - Optimized for parameter scans and chip testing - Acquisition of signal from a radioactive source • Jülich Digital Readout System (JDRS) - Modular, flexible system - Higher rate capability suitable for use during beam tests - See A. Lai et al., HK 63.8 20 30 40 50 T 0 2 4 6 8 10 counts ToT gain [clock counts / signal amplitude NC] counts 20 30 40 50 T 0 2 4 6 8 10 12 ToT gain [clock counts / signal amplitude NC] Significant optimization of TDC control with respect to TOFPET: • Size reduced by ~80% • Overall power consumption halved Radiation-hard logic for Single Event Upset (SEU) protection: • 1 bit: Triple Modular Redundancy • n bits: Hamming encoding Digital Blocks PASTA chip assembled on a test board and connected to a 2x2 cm 2 silicon strip sensor (strip pitch 50 µm) ToT linearity with ToT = t coarse_E - t coarse_T 0 10 20 30 40 10 0 1000 200 0 400 600 800 20 30 40 Pulse amplitude [A.U.] ToT [ns] y = a + b·x a = (-9.0 ± 1.8) ns b = (28.23 ± 0.09) ns/A.U. χ 2 = 106 n.d.f. = 39 Spectrum of a 90 Sr β - source ToT gain calibration after calibration before calibration First characterizations of the ASIC: • measurement of the ToT linearity (using only the coarse timing information); • acquisition of signal from alpha an beta radioactive sources on the strip sensor; • calibration of the ToT gain on all channels on a chip by adjusting the ToT feedback current.
Transcript of First characterization of the PASTA chip for the ...€¦ · Analog TDC Time-to-Digital Converter...
DPG
Frü
hjah
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gung
201
7, M
ünst
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1II. Physikalisches Institut, Justus-Liebig-Universität Gießen; 2INFN, Sezione di Torino; 3Forschungszentrum Jülich GmbH, Jülich, Germany
First characterization of the PASTA chip for themicrostrip part of the PANDA MVD
Tommaso Quagli1, Kai-Thomas Brinkmann1, Daniela Calvo2, Valentino Di Pietro1, Alessandra Lai3, Alberto Riccardi1, James Ritman3, Angelo Rivetti2,Manuel Rolo2, Robert Schnell1, Tobias Stockmanns3, Richard Wheadon2, André Zambanini3, and Hans-Georg Zaunick1
Tommaso QuagliII. Physikalisches Institut, JLU
Heinrich-Bu�-Ring 16D-35392 Gießen
The Micro-Vertex-Detector• 4 concentric barrels and 6 forward disks• Vertex reconstruction for primary and secondary vertices• Improvement of momentum resolution and PID• Requirements: - spatial resolution (tens of µm) - good time resolution and low material budget - high radiation tolerance (1014 n1MeV eq / cm2)Target
SpectrometerForward
Spectrometersilicon microstrips
siliconhybrid pixelsThe PANDA Experiment
• Fixed target experiment• Almost 4π acceptance• Cooled antiproton beam using electron and stochastic cooling• Proton or heavy nuclear target• Momentum from 1.5 up to 15 GeV/c• Trigger-less readout at ~107 interactions / s
First PASTA Characterizations
Example of chip test signals for an injected pulse
Front-endoutput
Comparatoroutput
Start ofConversion
End ofConversion
PANDA STrip ASIC (PASTA)• Front-end readout chip for double-sided silicon strip sensors• Measurement concept inspired by TOFPET
Chip Architecture• Number of channels: 64• Input pitch: 63 µm• Clock frequency: 160 MHz• Rate capability: 100 kHz / ch• Time bin width: 50 - 400 ps• dE/dx measurement: ToT, 8 bits dynamic range• Front-end noise: < 600 e-
• Power consumption: < 4 mW / ch• Radiation tolerance: 100 kGy (TID)• Technology: CMOS 110 nm
Front-End Architecture• Paperino - pippo pluto
Chip Simulations
0 5 10 15 20 25 300
200
400
600
800
Cdet [pF]
ENC
[e- ]
p-type
n-type
0 10 20 30 400
200
400
600
800
1000
1200
Qin [fC]
Tim
eov
erTh
resh
old
[ns]
p-typeMIP
n-type
Electronic noise with an inputcharge of 4 fC, for a capacitance
from 1 pF to 30 pF
ToT linearity in the input chargerange from 1 fC to 40 fC
Preampli�er Currentbu�er ToT Ampli�er Hysteresis
Comparator
Analog TDCTime-to-Digital Converter (TDC) architecture
(3.125 - 9.375) ns (0.4 - 1.2) µs
(3.125 - 9.375) ns (0.4 - 1.2) µs
TDC working principleCTDC = 4 · CTAC ; ITDC = 1/32 ITAC
VTDC = VTAC tTDC = 128 · tTAC
PASTA Readout Systems• PASTA chips fabricated in UMC CMOS 110nm technology and assembled on dedicated test boards
Two readout systems:
• Labview-based Torino system - Optimized for parameter scans and chip testing - Acquisition of signal from a radioactive source
• Jülich Digital Readout System (JDRS) - Modular, �exible system - Higher rate capability suitable for use during beam tests - See A. Lai et al., HK 63.8
20 30 40 50ToT coarse gain clock counts signal amplitude NC0
2
4
6
8
10
countscounts
ToT gain [clock counts / signal amplitude NC]counts
20 30 40 50ToT coarse gain clock counts signal amplitude NC0
2
4
6
8
10
12counts
ToT gain [clock counts / signal amplitude NC]
Significant optimization of TDC controlwith respect to TOFPET:• Size reduced by ~80%• Overall power consumption halved
Radiation-hard logic for Single EventUpset (SEU) protection:• 1 bit: Triple Modular Redundancy• n bits: Hamming encoding
Digital Blocks
PASTA chip assembled on a test boardand connected to a 2x2 cm2
silicon strip sensor (strip pitch 50 µm)
ToT linearity with ToT = tcoarse_E - tcoarse_T
0 10 20 30 40 Input Amplitude A. U.0
200
400
600
800
1000
ToTns
100
1000
200
0
400
600
800
20 30 40
Pulse amplitude [A.U.]
ToT [ns]
y = a + b·xa = (-9.0 ± 1.8) nsb = (28.23 ± 0.09) ns/A.U.
χ2 = 106n.d.f. = 39
Spectrum of a 90Sr β− source
ToT gain calibration
after calibration
before calibration
First characterizations of the ASIC:
• measurement of the ToT linearity (using only the coarse timing information);• acquisition of signal from alpha an beta radioactive sources on the strip sensor;• calibration of the ToT gain on all channels on a chip by adjusting the ToT feedback current.
