Finite State Machines - GitHub Pages · Computing delay from ALU1 A B control[0] Full Adder 0 1...
Transcript of Finite State Machines - GitHub Pages · Computing delay from ALU1 A B control[0] Full Adder 0 1...
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Finite State Machines
Exam 1Discussion groups assigned later
i>clicker grades updated
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State – the central concept of computing
How do we generate control signals for circuits? Finite State Machines
StateStorage
State Manipulations (ALU)
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Today’s lectureGoal: Build a sequential circuit from a state diagram Step 0: Problem specification Step 1: Build the state diagram Setp 2: Build the state table Step 3: Build the sequential circuit using D flip‐flops
Timing diagramAnother example: Sequence recognizer
If a combinational logic circuit is an implementation of a Boolean function, then a sequential logic circuit can be considered an implementation of a finite state machine.
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We want to update all state elements at the same time
Alternate between computation and updating state.
Computation(combinational
logic)
State(memory)
0
1
Time
clk
Compute
STO
RE
Compute
STO
RE
ComputeST
OR
ECompute
STO
RE
Compute
STO
RE
Compute
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The D flip-flop stores its D input as it’s state on the rising edge of the clock
QD
a) 0b) 1
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Asynchronous reset immediately resets a flip-flop to 0 Asynchronous = pertaining to operation without the use of fixed time intervals (opposed to synchronous).
QD
reset
x,y =a) 0,0b) 0,1c) 1,0d) 1,1
x y
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Asynchronous Reset implementationOne example possible implementation
Forces Q output to zero.Ignores inputs and current state.
(Not required material)
NOR
NOR
Q
Q'
reset
set
AND
AND
SR Latch w/Enable
NOR
NORD
AND
AND
enable
D Latch w/Enable
NOT
enable
NOT
clk
NOT
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When enable is 0, the flip flop doesn’t change on the rising edge Behaves normally when enable=1 QD
en
x,y =a) 0,0b) 0,1c) 1,0d) 1,1
x y
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Synchronous Design, reminder
Alternate between computation and updating state.
Computation(combinational
logic)
State(memory)
0
1
Time
clk
Compute
STO
RE
Compute
STO
RE
ComputeST
OR
ECompute
STO
RE
Compute
STO
RE
Compute
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D
Clk
Q
Q
D
Clk
Q
Q
AnextA
BnextB
…
StateNext‐State
LogicOutputLogic OutputsInputs
x
yz
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Step 0: Problem Specification
We have a candy machine that dispenses candies that cost 15‐cents Accepts
nickels (5‐cents) dimes (10‐cents)
Dispenses a candy if the balance is ≥ 15‐cents When the customer overpays
the machine does not return change, but keeps the balance for future transactions
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Step 1: Build the State Diagram Inputs
Ouputs
State identification
d n
c
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Step 1: Build the State Diagram
Outputs: candy or candy’Got‐0
Got‐5 Got‐10
Got‐15 Got‐20
a) candyb) candy'
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Step 1: Build the State Diagram
Inputs: d’n’, d’n, dn’
Got‐0/c’
Got‐5/c’ Got‐10/c’
Got‐15/c Got‐20/c
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Step 1: Build the State Diagram
Inputs: d’n’, d’n, dn’
Got‐0/c’
Got‐5/c’ Got‐10/c’
Got‐15/c Got‐20/c
d’n’
dn’d’n
d’nd’n’
dn’
What are the transitions for state Got‐15?
A: d’n’: Got0; d’n: Got20; dn’: Got20
B: d’n’: Got0; d’n: Got0; dn’: Got0
C: d’n’: Got0; d’n: Got5; dn’: Got10
D: d’n’: Got15; d’n: Got5; dn’: Got10
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Final State Diagram
Got‐0/c’
Got‐5/c’ Got‐10/c’
Got‐15/c Got‐20/c
d’n
d’n’
dn’
d’n
d’n
dn’d’n
d’n’
d’n’
d’n’d’n’
dn’
dn’ d’n
dn’
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What is State? (State is NOT 1s and 0s) Illinois
the remembered information of the computer system
State is the current arrangement of ones and zeros stored in flip flops.
Sorry I accidentally did this hw twice, please see the first instance. (an example of no state information)
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Step 2: Build a State TableCurrentState
Outputcandy
A
B
C
D
E
In a ‘Moore machine’, the outputs are a function only of the current state.
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Step 2: Build a Next-State TableCurrentState Input
NextState
A d’n’
A d’n
A dn’
B d’n’
B d’n
B dn’
C d’n’
C d’n
C dn’
D d’n’
D d’n
D dn’
E d’n’
E d’n
E dn’
A B C D E
A B B B C
B C C D D
C D E A E
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Step 2: Build a Next-State TableCurrentState Input
NextState
A d’n’ A
A d’n B
A dn’ C
B d’n’ B
B d’n C
B dn’ D
C d’n’ C
C d’n D
C dn’ E
D d’n’ A
D d’n B
D dn’ C
E d’n’ B
E d’n C
E dn’ D
Why do we need sequential logic to build this circuit?
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Step 3: Build Sequential Circuit
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Step 3: Build Sequential Circuit (State)CurrentState Input
NextState
A d’n’ A
A d’n B
A dn’ C
B d’n’ B
B d’n C
B dn’ D
C d’n’ C
C d’n D
C dn’ E
D d’n’ A
D d’n B
D dn’ C
E d’n’ B
E d’n C
E dn’ D
State Encoding:
5 states: How many bits?
a) 2b) 3c) 4d) 5e) 6
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Step 3: Build Sequential Circuit (State)CurrentState Input
NextState
A d’n’ A
A d’n B
A dn’ C
B d’n’ B
B d’n C
B dn’ D
C d’n’ C
C d’n D
C dn’ E
D d’n’ A
D d’n B
D dn’ C
E d’n’ B
E d’n C
E dn’ D
D
Clk
Q
Q
D
Clk
Q
Q
D
Clk
Q
Q
D
Clk
Q
Q
D
Clk
Q
Q
AnextA
B
C
D
E
nextB
nextC
nextD
nextE
ABCDEState A = 10000State B = 01000State C = 00100State D = 00010State E = 00001
One hot encoding
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Step 3: Build Sequential Circuit
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Step 3: Build Sequential Circuit (Next-State Logic)
CurrentState Input
NextState
A d’n’ A
A d’n B
A dn’ C
B d’n’ B
B d’n C
B dn’ D
C d’n’ C
C d’n D
C dn’ E
D d’n’ A
D d’n B
D dn’ C
E d’n’ B
E d’n C
E dn’ D
next D?
A: nextD = Ad’n’+ Dd’n’B: nextD= Ad’n + Bd’n’ + Dd’nC: nextD = Bdn’ + Cd’n + Edn’D: nextD= Ad’n’ + Bd’n + Cdn’ E: nextD =1
FFD Q
Q
FFD Q
Q
FFD Q
Q
FFD Q
Q
FFD Q
Q
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Step 3: Build Sequential Circuit
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Step 3: Build Sequential Circuit (output logic)CurrentState Input
NextState Output
A d’n’ A 0
A d’n B 0
A dn’ C 0
B d’n’ B 0
B d’n C 0
B dn’ D 0
C d’n’ C 0
C d’n D 0
C dn’ E 0
D d’n’ A 1
D d’n B 1
D dn’ C 1
E d’n’ B 1
E d’n C 1
E dn’ D 1
nextA = Ad’n’+ Dd’n’nextB = Ad’n + Bd’n’ + Dd’n + Edn’nextC = And’ + Bd’n + Cd’n’ + Ddn’ + Ed’nnextD = Bdn’ + Cd’n + Edn’nextE = Cdn’
Output: Candy = D + E
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Step 3:Build Sequential Circuit (output logic)
nextA = Ad’n’+ Dd’n’nextB = Ad’n + Bd’n’ + Dd’n + Edn’nextC = And’ + Bd’n + Cd’n’ + Ddn’ + Ed’nnextD = Bdn’ + Cd’n + Edn’nextE = Cdn’
Output: c = D + E
FFD Q
Q
FFD Q
Q
FFD Q
Q
FFD Q
Q
FFD Q
Q
AnextA
BnextB
CnextC
DnextD
EnextE
n
d
clk
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Step 3: Build Sequential Circuit (“finished”)
nextA = Ad’n’+ Dd’n’nextB = Ad’n + Bd’n’ + Dd’n + Edn’nextC = And’ + Bd’n + Cd’n’ + Ddn’ + Ed’nnextD = Bdn’ + Cd’n + Edn’nextE = Cdn’
Output = Candy = D + E
FFD Q
Q
FFD Q
Q
FFD Q
Q
FFD Q
Q
FFD Q
Q
AnextA
BnextB
CnextC
DnextD
EnextE
n
d
clk
candy
n’d
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Timing Diagram (update state on clock edges)
clk
D
N
A
B
C
D
E
Output
Time
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Timing Diagram
clk
D
N
A
B
C
D
E
Output
Time
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Computing delay from ALU1
A
B
control[0]
Full Adder
0
1
LogicUnit
carryin
out
carryout
A
B
Cin
Sum
Cout
A
B
R[0]
out
1-bit ALU slice
control[1]control[2]
R[1]
XOR
XOR gate
In Out Delay
A,B out 110ps
R out 10ps
In Out Delay
0,1 out 60ps
S out 80ps
In Out Delay
A,B out 30ps
Logic Unit
2‐to‐1 Multiplexor
What is the worst case propagation delay from B to out?
Full Adder
In Out Delay
A,B Sum 60ps
Cin Sum 30ps
A,B Cout 90ps
Cin Cout 60ps
A: 90psB: 120psC: 150psD: 170psE: 190ps