Finite State Machine (FSM)

• Model of behaviour composed of a finite number of states, input events, transitions between those states (rules or conditions), and actions.

conditionA

Inputs

State

Outputs

conditionB

!conditionA !conditionB/value0

S0 /value1

S1

Sequential systems

• Sequential systems are synchronous, i.e. makes use of a clock

• Outputs are dependent on earlier and the current state of inputs

Qclk

DComb.logic

Synchronous logic

Feedback / Sequential logic

OutputsInputs

next current

Finite State Machines in HW

• Requires registers to store the current state, a block of combinational logic to determine the next state (transition), and a block of combinational logic to determine the output of the FSM

NEXTSTATELOGIC

STATEMEMORY

OUTPUTLOGIC

OUTPUTS

CLK

INPUTS

CURRENT STATE

(MEALY ONLY)

Moore Machine

• Outputs are a function of the current state only• Outputs are synchronous to the clock• Propagation delay through output logic may nevertheless

lead to hazards (glitches)• A Moore machine has a one clock period delay from input

to output.

NEXTSTATELOGIC

STATEMEMORY

OUTPUTLOGIC

OUTPUTS

CLK

INPUTS

CURRENT STATE

Mealy Machine

• Outputs are a function of the current state and the inputs• Outputs change immediately when the input change*

– Combinational path through FSM

• Outputs of mealy machine is one clock cycle ahead of a Moore Machine (faster)• But has more complicated decoding of outputs

NEXTSTATELOGIC

STATEMEMORY

OUTPUTLOGIC

OUTPUTS

CLK

INPUTS

CURRENT STATE

*In an FPGA it is generally recommended to synchronize all signals to the system clock. I.e., it is expected that the inputs are synchronous to the same clock as the state memory. Essentially the outputs of a Mealy machine are therefore also synchronous to the clock. The main difference is that the output changes one clock cycle ahead of the current state, and therefore the Moore machine.

Description of state machines

• State diagrams

• ASM diagram

• State table

Graphic representationof state machine

State graph/diagram Moore

sS0/value0

sS1/value1

conditionA

Inputs

State

conditionB

!conditionA !conditionB

Outputs

State graph/diagram Mealy

sS0 sS1

conditionA / value1

Inputs

State

Outputs

conditionB / value0

!conditionA /value0

!conditionB /value1

ASM

condition

State box Decision box Conditional output box

false

true

• The state box represents the state in the FSM with a list of outputs values that are assigned when entering the state.

• The decision box checks input condition to determine exit path of current ASM block• A conditional output box lists output assignments that should take place when exiting

the state (Mealy outputs). Can only be placed after exit path of decision box.

ASM

condition

condition

State entry

State exit

State entry

State exit

ASM block

ASM block

false

true

false

true

• Unique exit path for a given combination of inputs• Exit path of ASM block must always lead to state box.

ASM diagram Moore

conditionA

conditionB

True

True

False

False

ASM diagram Mealy

conditionA

conditionB

True

True

False

False

State table Moore

Current state next state next state Current outputcondiationA !conditionA conditionB !conditionB

S0 S1 S0 - - value0

S1 - - S0 S1 value1

State table Mealy

Current state

conditionA !conditionA conditionB !conditionBnext state output next state output next state output next state output

S0 S1 value1 S0 value0 - - - -

S1 - - - - S0 value0 S1 value1