Final Report 5

DIGITAL DISPLAY BOARD

PROJECT REPORT SUBMITTED IN PARTIAL FULFILMENT

OF THE REQUIREMENTS FOR THE AWARD OF THE DEGREE

OF

BACHELOR OF ENGINEERING

(MAHARSHI DAYANAND UNIVERSITY, ROHTAK)

IN

ELECTRONICS AND COMMUNICATION

BY

Samyak Sabat 10231

Sanjay Singh Rawat 10234

Sanjeev Kumar Awasti 10235

Sarthak Sawhney 10236

Saurabh Aggarwal 10237

Saurabh Mullick 10238

UNDER THE GUIDANCE OF

Prof. (Mrs.) A.N. Mahajan Prof. (Dr.) H.S. Dua

Project Guide & Coordinator H.O.D. (ECE)

DEPTT OF ELECTRONICS & COMMUNICATION ENGG

DRONACHARYA COLLEGE OF ENGINEERING

FARRUKH NAGAR, GURGAON

2010- 2011


FARRUKHNAGAR, GURGAON

CERTIFICATE OF EXAMINATION

This is to certify that we have examined the Project titled –DIGITAL DISPLAY BOARD and

its Project report submitted by Samyak Sabat(10231), Sanjay Singh Rawat (10234),Sanjeev

Kumar Awasti (10235), Sarthak Sawhney (10236), Saurabh Aggarwal (10237) & Saurabh

Mullick (10238), students of final year B.E. (Electronics and Communication Engineering.).We

hereby accord our approval of it as a project carried out and presented in a manner required for

partial fulfillment for the Bachelor of Engineering (Electronics and Communication) degree of

Maharshi Dayanand University (Rohtak). This approval does not necessarily endorse or accept

every statement made, opinion expressed or conclusion drawn as recorded in the Project report;

it only signifies the acceptance of the Project report for the purpose for which it is submitted.

Prof. (Dr.) H.S. Dua

Examiner (Internal) Examiner (External) H.O.D. (ECE)

Date Date Date


KHENTAWAS, FARRUKH NAGAR

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

CERTIFICATE

This is to certify that the project titled DIGITAL DISPLAY BOARD has been completed by

following final year B.E students of this college in partial fulfillment of Bachelor of Engineering

(Electronics & Communication) degree of Maharshi Dayanand University (Rohtak) during the

academic session 2010 – 2011.

Samyak Sabat 10231

Sanjay Singh Rawat 10234

Sanjeev Kumar Awasti 10235

Sarthak Sawhney 10236

Saurabh Aggarwal 10237

Saurabh Mullick 10238

The project has been completed by the students under our guidance and supervision.

Prof. (Mrs.) A.N. Mahajan Prof. (Dr.) H.S. Dua

Project Guide & Coordinator H.O.D. (ECE)

ACKNOWLEDGEMENT

We are grateful to the authorities of Dronacharya College of Engineering for having permitted

us to go ahead with the project on WEATHER CANVAS in partial fulfillment of Bachelor of

Engineering (Electronics and Communication Engineering.) degree syllabus of Maharshi

Dayanand University (Rohtak). We are very thankful to Prof. (Dr.) H.S. Dua, Head of the

Department of Electronics & Communication Engineering for approving our project, timely

encouragement and supervision.

We are thankful & grateful to Prof. (Mrs.) A.N. Mahajan, Faculty of Electronics and

Communication Engineering Department for her valuable guidance on principles, fundamentals,

concepts and execution regarding the projects which has helped us in design, fabrication and

completion of project & preparation of the project report.

Date:

Samyak

Sabat

Sanjay

Singh

Rawat

Sanjeev

Kumar

Awasti

Sarthak

Sawhney

Saurabh

Aggarwal

Saurabh

Mullick

Table of contents

S.no TOPIC Page no.

1. Synopsis 01

2. Introduction 05

3. Block Diagram 07

4. Circuit Diagram and Explanation 10

5. Computer Application 14

6. Programming 22

7. Description of Components 41

8. Testing Procedure 81

9. Operating Procedure 83

10. Result Analysis 85

11. Problems Faced 87

12. Cost Analysis 89

13. Conclusion 91

14. References 93

List of Figures

Fig.no TOPIC Page no.

1. Project Block Diagram 08

2. Circuit Diagram for the Display Board 11

3. MAX232 Connections for Serial Communication 13

4. Computer Application Form 1 15



7. AT89S52 Pin Diagram 46

8. AT89S52 Block Diagram 47

9. Interrupt Sources 61

10. Crystal Oscillator Connections 62

11. External Clock Drive Information1 62

12. Pin diagram for 74154 64

13. Logic Diagram of 74154 65

14. Application Circuit of 74154 66

15. Pin diagram of UDN2981 67

16. Circuit for one driver of UDN2981 67

17. 8x8 LED dot matrix diagram 69

18. MAX 232 Pin Diagram 70

19. MAX232 Logic Diagram 70

20. AT24C08 Pin Diagram 71

21. AT24C08 Write Cycle 74

22. AT24C08 Read Cycle 76

23. DB9 Pin Configuration 77

24. 7805 Pin Description 78

25. Block Diagram of 7805 78

26. Performance Characteristics of 7805 80

List of Tables

Fig.no TOPIC Page no.

1. Alternate Functions of Port1 48

2. Alternate Functions Of Port3 49

3. AT89S52 SFR Mode and Reset Values 51

4. T2CON Timer/Counter 2 Control Register 52

5. Auxiliary Register 53

6. Auxiliary Register1 54

7. Interrupt enable Register 60

8. Function Table of 74154 65

9. Absolute Maximum Ratings For IC7805 79

1

CHAPTER 1

SYNOPSIS

2

PREFACE

We feel deeply gratified that our project has been successfully completed under the guidance and

supervision of our college facility. The basic need and purpose served by our project is the

automation of humanly work & reduction of chances of miscommunication due to conventional

notice boards. It also makes the mode of presenting the information to the intended user more

secure and eye catching.

The aim of our project is Design and Development of a digital display board made of LEDs

which can receive data from a computer serially and store it, after which it will be displayed in a

scrolling fashion of the board. The interface on the computer is intended to be user-friendly and

secure.

We would like to thank our college faculty for their support and motivation. It has been a

privilege working under their guidance.

3

SUMMARY

The project report consists of detailed explanation of the project DIGITAL DISPLAY BOARD.

The idea is initially ushered to the reader in the simplest and most presentable way. Detailed

theory of operation, block diagrams and specific circuit diagrams follow the explanations. All the

components used in the project are mentioned with specifications. We have also mentioned a

testing procedure for the convenience of the reader or operator. After describing the software, the

result is analyzed. Along with the cost analysis of the project problems faced by us in making the

project are also mentioned for clear understanding of the theory as well as the practical

implication.

Eventually we concluded our innovation and expressed our approach for future scope of our

work.

4

EXECUTION

The heart of our project will be Microcontroller AT89S52. The microcontroller will serve three

purposes. First, it will control the scrolling display of the LED matrix board. Second, it will

perform the read write operation on the serial EEPROM memory. Third, it will be serial

communication enabled which will allow it to receive and store the data coming from the

computer.

We have made a User Friendly and secure application, made using Microsoft Visual Basic,

which can be used to alter the information on the display. The user will simply have to select the

port for communication and enter the data to be displayed. Since, today we rely more on Laptops

than PC‘s and Laptops are not available with a Serial Communication port, we decided to use a

USB to serial converter.

The display is basically a matrix of LEDs which is controlled by Demultipexers (for Scrolling)

and NPN transistor array (for current amplification).

5

CHAPTER 2

INTRODUCTION

6

INTRODUCTION

The aim of our project is to build a LED display board which can display moving texts. The text

displayed on these boards will be modifiable by using a computer to feed new text. The

computer would consist of a secure GUI using which it would be possible to regulate the display

of the text. A graphical user interface (GUI), often pronounced gooey, is a type of user interface

that allows users to interact with programs in more ways than typing such as computers; hand-

held devices such as MP3 players, portable media players or gaming devices; household

appliances and office equipment with images rather than text commands. A GUI offers graphical

icons, and visual indicators, as opposed to text-based interfaces, typed command labels or text

navigation to fully represent the information and actions available to a user. The actions are

usually performed through direct manipulation of the graphical elements. The heart of the project would be a microcontroller which would receive messages from the

system and regularly update the information being displayed on the LED display board. A

microcontroller (sometimes abbreviated µC, uC or MCU) is a small computer on a single

integrated circuit containing a processor core, memory, and programmable input/output

peripherals. The sensors that will act as a detector of the weather conditions will be connected to

the microcontroller through an Analog to Digital Converter.

We will use the concept of Serial Communication for sending new text to the microcontroller for

display on the LED display board. In telecommunication and computer science, the concept of

serial communication is the process of sending data one bit at a time, sequentially, over a

communication channel or computer bus. This is in contrast to parallel communication, where

several bits are sent as a whole, on a link with several parallel channels. Serial communication is

used for all long-haul communication and most computer networks, where the cost of cable and

synchronization difficulties makes parallel communication impractical. Serial computer buses

are becoming more common even at shorter distances, as improved signal integrity and

transmission speeds in newer serial technologies have begun to outweigh the parallel bus's

advantage of simplicity.

The display board will be an array of 5mm Red color LED‘s. A light-emitting diode (LED) is a

semiconductor light source. LEDs are used as indicator lamps in many devices, and are

increasingly used for lighting. Introduced as a practical electronic component in 1962, early

LEDs emitted low-intensity red light, but modern versions are available across the visible,

ultraviolet and infrared wavelengths, with very high brightness. LED‘s are cheap and consume

very less energy as compared conventional lighting sources or LCD displays. This board will be

controlled by using demultiplexers, timers and microcontrollers. The board will be capable of

displaying moving, as well as still texts.

7

CHAPTER 3

BLOCK DIAGRAM

8

BLOCK DIAGRAM OF THE SYSTEM

Fig.1. Block Diagram

COMPUTER MICROCONT-

ROLLER

CONTROL

SYSTEM

LED DISPLAY BOARD

MEMORY

SERIAL

COMM

9

DESCRIPTION OF BLOCK DIAGRAM

As shown in block diagram of the system it has following major blocks.

MICROCONTROLLER AT89S52: - The heart of our project will be Microcontroller

AT89S52. The microcontroller will serve three purposes. First, it will control the scrolling

display of the LED matrix board. Second, it will perform the read write operation on the serial

EEPROM memory. Third, it will be serial communication enabled which will allow it to receive

and store the data coming from the computer.

COMPUTER: - The computer will be responsible to communicate the data to be displayed on

the display board serially to the microcontroller. For this we have made an application which will

run on computer and for serial communication we use a USB to Serial Converter.

MEMORY: - For memory we use a serial EEPROM memory whose main function will be to

store the incoming data from the computer after some modification. When the display will be

switched on, the microcontroller will read the data from the memory and display it on the LED

display board. The read/write operations will be conducted by the microcontroller itself.

CONTROL SYSTEM: - The control system will control the display on the screen. The control

system will use Demultiplexers to control the scrolling and NPN transistor array IC to amplify

the current before it is supplied to the Display Board.

LED DISPLAY BOARD: - The display board used is a 32x8 LED matrix board. It is called a

matrix because all the P junctions of LEDs in one row are shorted and N junctions of the LEDs

in one column are shorted. The LED which has to be laminated is then switched on using the

matrix positions.

10

CHAPTER 4

CIRCUIT DIAGRAM AND

EXPLANATION

11

Fig.2. Circuit Diagram for the Display Board

12

CIRCUIT DIAGRAM EXPLANATION FOR DIGITAL DISPLAY BOARD

Here we have used a DC Adapter to provide us a power of 12V DC, which is brought down to

5VDC using LM7805 voltage regulator.

This +5v voltage is applied to following components.

Microcontroller

Demultiplexers

Memory

UDN 2981

SIP

We start with the Serial communication. When the data is received by the microcontroller

through its RXD pin, it is first stored in the RAM of the Microcontroller. The data received is

basically the string ASCII codes of the characters sent by the User through the PC. Then the

microcontroller converts this ASCII information to a six byte HEX code and stores it in the

Serial EEPROM memory.

A six byte HEX code is used as the data is to be displayed on the LED board and it will use at

least six columns to display one character.

When the writing operation is over the microntroller starts the display operation, where it first

reads the data stored in the memory and then send it to the array of P side of the LEDs after

amplifying it through the NPN transistor array. The display is made possible due to the principle

of ‗Persistence of Vision‘ i.e. human eyes can store an image for a very short duration and if the

image attributes are changed within that time limit , our eyes will feel that the image is moving.

Thus the demultiplexers are controlled by the microcontroller to scroll at a very fast speed, so

that we can feel that the text is scrolling on the board.

13

Circuit Diagram for Serial Communication Module

Fig.3. MAX232 Connections for Serial Communication

The data from computer is sent serially through a USB-DB9 cable to theMAX232 IC. The

function of this IC is to change the voltage level of the incoming signal from 25 V to 5V. It also

stabilizes noise, if any. The various capacitors used are basically to clip the voltage. The

modified data is then sent to the microcontroller RXD pin.

14

CHAPTER 5

COMPUTER

APPLICATION

15

Introduction Form

Fig.4. Computer Application Form 1

16

Authentication Form


17

Code for Authentication Form

Private Sub Command1_Click()

Dim b As Integer

Static a As Integer

a = a + 1

If Text1.Text = "admin" And Text2.Text = "admin" Then

Form3.Show

Unload Me

Else

If a <= 2 Then

b = MsgBox("Wrong Username or Password", vbCritical, "Display Project")

Text1.Text = ""

Text2.Text = ""

Text1.SetFocus

Else

b = MsgBox("Unauthorised Identity", vbCritical, "Display Project")

End

End If

End If

End Sub


End

End Sub

Private Sub Form_Load()

Command1.Enabled = False

End Sub

Private Sub Text1_Change()

18

If (Text1.Text <> "") And (Text2.Text <> "") Then

Command1.Enabled = True

Command1.Default = True

Else


End If

End Sub


If Text1.Text = "" And Text2.Text = "" Then


Else


Command1.Default = True

End If

End Sub

19

Main Form for Data Sending


20

Code for Main Form


MSComm1.CommPort = Combo1.Text

MSComm1.PortOpen = True


End Sub


MSComm1.PortOpen = False

End Sub


Dim s, m As String

s = Text1.Text

MSComm1.Output = s

m = MsgBox("Data Sent Successfully", vbOKOnly, "Display Project")

End Sub


End

End Sub

Private Sub Form_Load()

MSComm1.Settings = "9600,N,8,1"


End Sub


Static a As Integer

Dim b As Integer

21

a = a + 1

Label1.Caption = (45 - a) & " Characters Remaining"

If a = 45 Then

b = MsgBox("Word Limit Crossed", vbOKOnly, "Display Board")

End If

End Sub

22

CHAPTER 6

PROGRAMMING

23

;*****************************************************************************

************;PROGRAM IN ASSEMBLY LANGUAGE FOR THE PROJECT OF

"DIGITAL DISPLAY BOARD"

;*****************************************************************************

************

BUFFER EQU 30H

FADDR EQU 0A0H ; FIXED ADDRESS FOR AT24C08

BLOCK1 EQU 0H ; PROGRAMMABLE MEMORY BLOCK ADDRESS (0..7)

BLOCK2 EQU 1H

BLOCK3 EQU 2H

BLOCK4 EQU 3H

BLOCK5 EQU 4H

BLOCK6 EQU 5H

BLOCK7 EQU 6H

BLOCK8 EQU 7H

SCL BIT P3.6 ; SERIAL CLOCK INOUT

SDA BIT P3.7 ; SERIAL DATA INOUT

ORG 0H

JMP MAIN

ORG 0023H

JMP SERIAL

;************************************************************************

; MAIN SUBROUTINE

;************************************************************************

MAIN:

MOV R7,#BLOCK1 ;INITIALIZATIONS REQUIRED FOR PROGRAM

MOV R6,#2FH

MOV R0,#37H

MOV P0,#0FFH

MOV P1,#0FFH

MOV P2,#0FFH

MOV P3,#0FFH

MOV 37H,#20H

MOV 33H,#00H

MOV 31H,#00H

MOV 32H,#00D

MOV 33H,#00D

MOV SP,#70H

MOV TMOD,#20H ; BAUD RATE SETTINGS IN TIMER1

MOV SCON,#50H

24

MOV TH1,#0FDH ; BAUD RATE 9600 @ 11.0592 MHZ

MOV IE,#90H ; SERIAL INTERRUPT ENABLE

SETB TR1

CLR F0 ;CHECK BIT

JMP LOOP

;***************************************************************************

;FIRST 32 BYTES OF THE MEMORY TO BE LEFT BLANK

;****************************************************************************

WRITE_32:

MOV BUFFER,#80H ; WRITE VALUE 80H

MOV B,#20D ; RETRY COUNTER IN CASE OF FAILURE

MOV 31H,#00H ; SETUP ADDRESSES

X52:

MOV A,R7 ; PROGRAMMABLE PAGE ADDRESS

CALL WRITE_BYTE ; WRITE BYTE

CALL DELAY_5ms

JNC X53

DJNZ B,X52 ; OK OR NOT OK

SETB C ; SET CARRY

JMP X54

X53:

INC 31H

MOV A,31H

CJNE A,#32D,X52

CLR C

X54:

RET

;***************************************************************

; SERIAL SUBROUTINE

;*****************************************************************

SERIAL:

MOV A,SBUF ;STORE INCOMING DATA IN RAM

CJNE A,#2EH,S1 ;CHECK END OF DATA

MOV @R0,A

CALL DELAY

MOV R0,#37H

CALL WRITE_32 ;WRITE DATA IN MEMORY

CLR C

25

CALL WRITE_ALL

CALL RESET

CLR RI

CLR F0

JMP RET3

S1:

MOV @R0,A

SETB F0

INC R0

CLR RI

RET3:

RETI

;****************************************************************

; LOOP FOR DISPLAY

;*****************************************************************

LOOP:

JB F0,$ ;MAIN LOOP OF PROGRAM FOR DISPLAY

CALL READ_BLOCK

LCALL DELAY

LCALL RESET

JMP LOOP

;***********************************************************

;LAST 32 BYTES IN THE MEMORY LEFT BLANK

;***********************************************************

WRITE_32_END:

MOV BUFFER,#80H ; WRITE VALUE 80H

MOV B,#20H ; RETRY COUNTER IN CASE OF FAILURE

X82:

MOV A,R7 ; PROGRAMMABLE PAGE ADDRESS

MOV BUFFER,#80H

CALL WRITE_BYTE ; WRITE BYTE

CALL DELAY_5ms

JNC X83

JMP X82 ; OK OR NOT OK

SETB C ; SET CARRY

JMP X84

X83:

26

CALL INCREMENTW

JNC X

INC 32H

MOV A,32H

CALL BLOCK ; CALCULATE PAGE OF EEPROM (R7=PAGE ADDRESS)

CLR C

X:

DJNZ B,X82

CLR C

X84:

RET

;******************************************************************

; WRITE THE DATA

;******************************************************************

WRITE_ALL:

MOV R7,#BLOCK1 ;WRITE THE COMPLETE DATA IN THE MEMORY

S2:

MOV A,@R0 ;CHECK FOR END OF STRING

CJNE A,#2EH,S3

S4:

CALL WRITE_32_END

MOV BUFFER,#00H

MOV A,R7

LCALL WRITE_BYTE

LCALL DELAY_5ms

JC S4

MOV R0,#37H

MOV 31H,#00H

JMP RET2

S3:

LCALL RECOG ;RECOGNIZE THE LETTER AND CONVERT IT TO SIX BYTE

HEX CODE

LCALL CALCUL

LCALL WRITE

INC R0

JMP S2

RET2:

27

RET

;************************************************************************

; READ DATA

;***********************************************************************

READ_BLOCK:

; READ FROM ONE BYTE TO ONE PAGE OF DATA FROM AN AT24C08B.

; PERFORMS A RANDOM READ WHICH IS EXTENDED INTO A SEQUENTIAL READ

; WHEN MORE THAN ONE BYTE IS READ. CALLED WITH PROGRAMMABLE

ADDRESS

; IN A, ADDRESS OF FIRST BYTE AT ADDRESS 33H.

; RETURNS DATA AT PORT. RETURNS CY SET TO INDICATE THAT THE BUS IS

; NOT AVAILABLE OR THAT THE ADDRESSED DEVICE FAILED TO

ACKNOWLEDGE.

; SEND DUMMY WRITE COMMAND TO ADDRESS FIRST BYTE.

CLR C

MOV R7,#BLOCK1

NEXT_32:

LCALL START

JC X32 ; ABORT IF BUS NOT AVAILABLE

MOV A,R7

RL A ; PROGRAMMABLE ADDRESS TO BITS 3:1

ORL A,#FADDR ; ADD FIXED ADDRESS

MOV BUFFER,A ; SAVE COPY OF DEVICE ADDRESS

CLR ACC.0 ; SPECIFY WRITE OPERATION

LCALL SHOUT ; SEND DEVICE ADDRESS

JC X32

MOV A,33H ; SEND LOW BYTE OF ADDRESS

LCALL SHOUT ;

JC X32

; SEND READ COMMAND AND RECEIVE DATA.

LCALL START ; SECOND START FOR READ

JC X32

MOV A,BUFFER ; GET DEVICE ADDRESS

SETB ACC.0 ; SPECIFY READ OPERATION

LCALL SHOUT ; SEND DEVICE ADDRESS

JC X32

X31:

LCALL SHIN ; RECEIVE DATA BYTE

28

JMP DISPLAY

X32:

RET

;*****************************************************************************

************

; SEND DATA ON PORT 2 READED FROM EEPROM

;*****************************************************************************

************

DISPLAY:

X3:

JB F0,X32

CJNE A,#00H,S6

CALL NAK ; NO ACKNOWLEDGE

CLR C

CALL STOP ; STOP CONDITION

JMP X32

S6:

MOV P2,A ; READED DATA

MOV P1,R6 ; DECODING OUTPUT

CALL DELAY

DEC R6

CJNE R6,#10D,NLB ; CHECK FOR 4 PIECES (8*4=32)

CALL NAK ; NO ACKNOWLEDGE

CLR C

CALL STOP ; STOP CONDITION

CALL INCREMENTR

MOV R6,#2Fh

JMP NEXT_32

NLB:

CALL ACK

JMP X31

INCREMENTR:

INC 33H ;INCREMENTING ADDRESS AFTER A READ THROUGH 32 BYTES

MOV A,33H

CJNE A,#00H,S7

INC 34H

CALL BLOCK_2

MOV 33H,#00H

S7:

RET

29

BLOCK_2:

MOV A,34H ; SUITABLE VALUE OF R7 FOR MEMORY BLOCKS OF EEPROM

WHILE READING DATA

CJNE A,#1D,A1

MOV R7,#BLOCK2

RET

A1:

CJNE A,#2D,A2 ;

MOV R7,#BLOCK3

RET

A2:

CJNE A,#3D,A3 ;

MOV R7,#BLOCK4

RET

A3:

CJNE A,#4D,A4 ;

MOV R7,#BLOCK5

RET

A4:

CJNE A,#5D,A5 ;

MOV R7,#BLOCK6

RET

A5:

CJNE A,#6D,A6 ;

MOV R7,#BLOCK7

RET

A6:

CJNE A,#7D,A0 ;

MOV R7,#BLOCK8

A0:

RET

;**************************************************************************

; RECOGNIZE THE FIRST NIBBLE OF ASCII DATA

;**************************************************************************

RECOG:

MOV R2,A ; CHARACTER COME FROM PC

30

ANL A,#0F0H ; SPLIT BYTE

SWAP A ; SWAP BYTE

MOV R3,A ; SAVE RESULT IN R3

MOV A,R2 ; CHARACTER COME FROM PC

ANL A,#0FH ; SPLIT BYTE

MOV R2,A ; SAVE RESULT IN R2

NEXT6:

CJNE R3,#2D,NEXT1 ; GET SUITABLE VALUE OF DPTR ACCORDING TO

CHARACTER

MOV DPTR,#TABLE1

RET

NEXT1:

CJNE R3,#3D,NEXT2 ;

MOV DPTR,#TABLE2

RET

NEXT2:

CJNE R3,#4D,NEXT3 ;

MOV DPTR,#TABLE3

RET

NEXT3:

CJNE R3,#5D,NEXT4 ;

MOV DPTR,#TABLE4

RET

NEXT4:

CJNE R3,#6D,NEXT5 ;

MOV DPTR,#TABLE5

RET

NEXT5:

CJNE R3,#7D,NEXT6 ;

MOV DPTR,#TABLE6

RET

;*****************************************************************************

************

; CALCULATION FOR ACCUMULATOR FOR SECOND NIBBLE OF ASCII

DATA

;*****************************************************************************

************

CALCUL: ; GET SUITABLE VALUE OF A TO COPY BYTE FROM ROM

31

CLR A

BACK:

ADD A,#06D

DJNZ R2,BACK

MOV R5,A

RET

;*******************************************************************

; WRITE OPERATION FOR ONE CHARACTER

;*********************************************************************

WRITE:

MOV R4,#6D ; NO OF BYTES TO BE WRITTEN

REVERSE:

MOV A,R5

MOVC A,@A+DPTR ; GET BYTE FROM ROM

MOV BUFFER,A

MOV A,R7

LCALL WRITE_BYTE ; WRITE DATA BYTE

LCALL DELAY_5ms

JC REVERSE

CALL INCREMENTW

INC R5

DJNZ R4,REVERSE

RET

;*****************************************************************************

********

; PROCEDURE TO INCREMENT THE ADDRESS WHILE WRITING THE

DATA

;*****************************************************************************

********

INCREMENTW:

INC 31H

MOV A,31H

CJNE A,#00H,RET1

INC 32H

CALL BLOCK

MOV 31H,00H

RET1:

RET

BLOCK:

32

MOV A,32H ; SUITABLE VALUE OF R7 FOR MEMORY

BLOCKS OF EEPROM

CJNE A,#1D,B1

MOV R7,#BLOCK2

RET

B1:

CJNE A,#2D,B2 ;

MOV R7,#BLOCK3

RET

B2:

CJNE A,#3D,B3 ;

MOV R7,#BLOCK4

RET

B3:

CJNE A,#4D,B4 ;

MOV R7,#BLOCK5

RET

B4:

CJNE A,#5D,B5 ;

MOV R7,#BLOCK6

RET

B5:

CJNE A,#6D,B6 ;

MOV R7,#BLOCK7

RET

B6:

CJNE A,#7D,B0 ;

MOV R7,#BLOCK8

MOV 32H,#00D

B0:

RET

;************************************************************************

; STARTING ROUTINE FOR DATA EXCHANGE WITH THE MEMORY IC

;**************************************************************************

START:

; SEND START, DEFINED AS HIGH-TO-LOW SDA WITH SCL HIGH.

; RETURN WITH SCL, SDA LOW.

33

; RETURNS CY SET IF BUS IS NOT AVAILABLE.

SETB SDA

SETB SCL

; VERIFY BUS AVAILABLE.

JNB SDA,X40 ; JUMP IF NOT HIGH

JNB SCL,X40 ; JUMP IF NOT HIGH

NOP ; ENFORCE SETUP DELAY AND CYCLE DELAY

CLR SDA

NOP ; ENFORCE HOLD DELAY

NOP ;

NOP ;

NOP ;

NOP ;

CLR SCL

CLR C ; CLEAR ERROR FLAG

JMP X41

X40:

SETB C ; SET ERROR FLAG

X41:

RET

;*****************************************************************************

************

; STOP CONDITION FOR COMMUNICATION WITH EEPROM

;*****************************************************************************

************

STOP:

; SEND STOP, DEFINED AS LOW-TO-HIGH SDA WITH SCL HIGH.

; SCL EXPECTED LOW ON ENTRY. RETURN WITH SCL, SDA HIGH.

CLR SDA

NOP ; ENFORCE SCL LOW AND DATA SETUP

NOP

SETB SCL

NOP ; ENFORCE SETUP DELAY

NOP ;

NOP ;

NOP ;

NOP ;

34

SETB SDA

RET

;*****************************************************************************

************

; DATA BYTE TRANSFOR FROM MICROCONTROLLER TO EEPROM

;*****************************************************************************

************

SHOUT:

; SHIFT OUT A BYTE TO THE AT24C16, MOST SIGNIFICANT BIT FIRST.

; SCL, SDA EXPECTED LOW ON ENTRY. RETURN WITH SCL LOW.

; CALLED WITH DATA TO SEND IN A.

; RETURNS CY SET TO INDICATE FAILURE BY SLAVE TO ACKNOWLEDGE.

; DESTROYS A.

PUSH B

MOV B,#8 ; BIT COUNTER

X42:

RLC A ; MOVE BIT INTO CY

MOV SDA,C ; OUTPUT BIT


SETB SCL ; RAISE CLOCK

NOP ; ENFORCE SCL HIGH

NOP ;

NOP ;

NOP ;

CLR SCL ; DROP CLOCK

DJNZ B,X42 ; NEXT BIT

SETB SDA ; RELEASE SDA FOR ACK

NOP ; ENFORCE SCL LOW AND TAA

NOP ;

SETB SCL ; RAISE ACK CLOCK


NOP ;

NOP ;

NOP ;

MOV C,SDA ; GET ACK BIT

CLR SCL ; DROP ACK CLOCK

POP B

RET

35

;*****************************************************************************

************

; DATA BYTE TRANSFOR FROM EEPROM TO MICROCONTROLLER

;*****************************************************************************

************

SHIN:

; SHIFT IN A BYTE FROM THE AT24CXX, MOST SIGNIFICANT BIT FIRST.

; SCL EXPECTED LOW ON ENTRY. RETURN WITH SCL LOW.

; RETURNS RECEIVED DATA BYTE IN A.

SETB SDA ; MAKE SDA AN INPUT

PUSH B

MOV B,#8 ; BIT COUNT

X43:


NOP ;

NOP ;



NOP ;

MOV C,SDA ; INPUT BIT

RLC A ; MOVE BIT INTO BYTE


DJNZ B,X43 ; NEXT BIT

POP B

RET

;*****************************************************************************

************

; ACKNOWLEDGEMENT FOR EEPROM TO GET NEXT BYTE

;*****************************************************************************

************

ACK:

; CLOCK OUT AN ACKNOWLEDGE BIT (LOW).

; SCL EXPECTED LOW ON ENTRY. RETURN WITH SCL, SDA LOW.

CLR SDA ; ACK BIT


NOP ;


36


NOP ;

NOP ;

NOP ;


RET

;*****************************************************************************

************

; NO ACKNOWLEDGEMENT FOR EEPROM TO GET NEXT BYTE

;*****************************************************************************

************

NAK:

; CLOCK OUT A NEGATIVE ACKNOWLEDGE BIT (HIGH).

; SCL EXPECTED LOW ON ENTRY. RETURN WITH SCL LOW, SDA HIGH.

SETB SDA ; NAK BIT


NOP ;



NOP ;

NOP ;

NOP ;


RET

;*****************************************************************************

************

; ROUTINE TO WRITE A BYTE IN THE MEMORY

;*****************************************************************************

************

WRITE_BYTE:

CALL START

JC X49 ; ABORT IF BUS NOT AVAILABLE

RL A ; PROGRAMMABLE ADDRESS TO BITS 3:1

ORL A,#FADDR ; ADD FIXED ADDRESS

CLR ACC.0 ; SPECIFY WRITE OPERATION

CALL SHOUT ; SEND DEVICE ADDRESS

37

JC X48 ; ABORT IF NO ACKNOWLEDGE

MOV A,31H ; SEND LOW BYTE OF ADDRESS

CALL SHOUT ;


MOV A,BUFFER ; GET DATA

CALL SHOUT ; SEND DATA


CLR C ; CLEAR ERROR FLAG

X48:

CALL STOP

X49:

RET

;*****************************************************************************

************

; DELAY SUBROUTINE

;*****************************************************************************

************

DELAY: ; DELAY FOR DISPLAY

MOV 35H,#3D

DL1:

MOV 36H,#160D

DJNZ 36H,$

DJNZ 35H,DL1

RET

;*****************************************************************************

**

; RESET ROUTINE

;*****************************************************************************

*****

RESET:

MOV BUFFER,#00D ; RESET VALUES BEFORE NEXT CYCLE

MOV 31H,#00D

MOV 32H,#00D

MOV 33H,#00D

MOV 34H,#00D

MOV R6,#2FH

38

RET

;*****************************************************************************

************

; 5 MILLISECOND DELAY FOR EEPROM WRITE TIME CYCLE

;*****************************************************************************

************

DELAY_5ms: ; 5ms DELAY FOR EEPROM WRITE CYCLE

MOV 35H,#23D

DL:

MOV 36H,#100D

DJNZ 36H,$

DJNZ 35H,DL

RET

;*****************************************************************************

************

; LOOK UP TABLE FOR CHARACTERS

;*****************************************************************************

************

ORG 300H

TABLE1:

DB 80H,80H,80H,80H,80H,80H ; SPACE

DB 80H,80H,5FH,80H,80H,80H ; !

DB 04H,02H,05H,02H,01H,80H ; "

DB 14H,7FH,14H,7FH,14H,80H ; #

DB 26H,49H,7FH,49H,32H,80H ; $

DB 22H,10H,08H,04H,22H,80H ; %

DB 80H,36H,49H,36H,28H,80H ; &

DB 04H,02H,01H,80H,80H,80H ; '

DB 08H,14H,22H,41H,80H,80H ; (

DB 80H,41H,22H,14H,08H,80H ; )

DB 2AH,1CH,08H,1CH,2AH,80H ; *

DB 08H,08H,3EH,08H,08H,80H ; +

DB 80H,58H,38H,80H,80H,80H ; ,

DB 08H,08H,08H,08H,08H,80H ; -

DB 40H,80H,80H,80H,80H,80H ; .

DB 20H,10H,08H,04H,02H,80H ; /

TABLE2:

DB 3EH,41H,41H,41H,3EH,80H ; 0

39

DB 80H,42H,0FFH,40H,80H,80H ; 1

DB 42H,61H,51H,49H,46H,80H ; 2

DB 49H,49H,49H,49H,36H,80H ; 3

DB 07H,08H,08H,08H,77H,80H ; 4

DB 4FH,49H,49H,49H,39H,80H ; 5

DB 3EH,49H,49H,49H,32H,80H ; 6

DB 41H,21H,11H,09H,07H,80H ; 7

DB 3EH,49H,49H,49H,3EH,80H ; 8

DB 06H,09H,09H,09H,7EH,80H ; 9

DB 80H,80H,22H,80H,80H,80H ; :

DB 80H,40H,32H,80H,80H,80H ; ;

DB 08H,14H,22H,41H,80H,80H ; <

DB 14H,14H,14H,14H,14H,80H ; =

DB 80H,41H,22H,14H,08H,80H ; >

DB 06H,01H,51H,09H,06H,80H ; ?

TABLE3:

DB 3EH,4DH,53H,1DH,1EH,80H ; @

DB 7CH,12H,11H,12H,7CH,80H ; A

DB 7FH,49H,49H,49H,36H,80H ; B

DB 3EH,41H,41H,41H,22H,80H ; C

DB 7FH,41H,41H,22H,1CH,80H ; D

DB 7FH,49H,49H,49H,41H,80H ; E

DB 7FH,09H,09H,09H,01H,80H ; F

DB 3EH,41H,49H,49H,7AH,80H ; G

DB 7FH,08H,08H,08H,7FH,80H ; H

DB 80H,41H,7FH,41H,80H,80H ; I

DB 20H,40H,41H,3FH,01H,80H ; J

DB 7FH,08H,14H,22H,41H,80H ; K

DB 7FH,40H,40H,40H,40H,80H ; L

DB 7FH,02H,0CH,02H,7FH,80H ; M

DB 7FH,04H,08H,10H,7FH,80H ; N

DB 3EH,41H,41H,41H,3EH,80H ; O

TABLE4:

DB 7FH,09H,09H,09H,06H,80H ; P

DB 3EH,41H,51H,21H,5EH,80H ; Q

DB 7FH,09H,19H,29H,46H,80H ; R

DB 46H,49H,49H,49H,31H,80H ; S

DB 01H,01H,7FH,01H,01H,80H ; T

DB 3FH,40H,40H,40H,3FH,80H ; U

DB 1FH,20H,40H,20H,1FH,80H ; V

DB 3FH,40H,30H,40H,3FH,80H ; W

DB 63H,14H,08H,14H,63H,80H ; X

40

DB 07H,08H,70H,08H,07H,80H ; Y

DB 61H,51H,49H,45H,43H,80H ; Z

DB 7FH,41H,41H,41H,80H,80H ; [

DB 02H,04H,08H,10H,40H,80H ; "\"

DB 80H,41H,41H,41H,7FH,80H ; ]

DB 04H,02H,01H,02H,04H,80H ; ^

DB 40H,40H,40H,40H,40H,80H ; _

TABLE5:

DB 01H,02H,04H,80H,80H,80H ; '

DB 7CH,12H,11H,12H,7CH,80H ; A

DB 7FH,49H,49H,49H,36H,80H ; B

DB 3EH,41H,41H,41H,22H,80H ; C

DB 7FH,41H,41H,22H,1CH,80H ; D

DB 7FH,49H,49H,49H,41H,80H ; E

DB 7FH,09H,09H,09H,01H,80H ; F

DB 3EH,41H,49H,49H,7AH,80H ; G

DB 7FH,08H,08H,08H,7FH,80H ; H

DB 80H,41H,7FH,41H,80H,80H ; I

DB 20H,40H,41H,3FH,01H,80H ; J

DB 7FH,08H,14H,22H,41H,80H ; K

DB 7FH,40H,40H,40H,40H,80H ; L

DB 7FH,02H,0CH,02H,7FH,80H ; M

DB 7FH,04H,08H,10H,7FH,80H ; N

DB 3EH,41H,41H,41H,3EH,80H ; O

TABLE6:

DB 7FH,09H,09H,09H,06H,80H ; P

DB 3EH,41H,51H,21H,5EH,80H ; Q

DB 7FH,09H,19H,29H,46H,80H ; R

DB 46H,49H,49H,49H,31H,80H ; S

DB 01H,01H,7FH,01H,01H,80H ; T

DB 3FH,40H,40H,40H,3FH,80H ; U

DB 1FH,20H,40H,20H,1FH,80H ; V

DB 3FH,40H,30H,40H,3FH,80H ; W

DB 63H,14H,08H,14H,63H,80H ; X

DB 07H,08H,70H,08H,07H,80H ; Y

DB 61H,51H,49H,45H,43H,80H ; Z

DB 77H,49H,41H,41H,80H,80H ;

DB 80H,80H,77H,80H,80H,80H ; |

DB 80H,41H,41H,49H,77H,80H ;

DB 04H,02H,04H,02H,80H,80H ; ~

END

41

CHAPTER 7

DESCRIPTION OF

COMPONENTS

42

COMPONENTS USED

COMPONENTS QUANTITY

1. Microcontroller IC AT89S52 01

2. 74154 DEMUX 02

3. AT24C08 01

4. UDN2981 01

5. MAX232 01

6. LM7805 01

7. SIP 01

8. LED 8x8 DOT Matrix board 04

9. Crystal Oscillator (11.0592Mhz) 01

10. Resistances

10k Ω 15

330 Ω 15

11. Capacitors

10uF 10

33pF 05

12. Jumpers

8 Pin 10

4 Pin 02

3 Pin 02

13. DC Voltage Adapters 02

14. USB to Serial Connector 01

15. Connecting wires

16. PCB 05

17. LEDs 02

43

MICROCONTROLLER

1. History of the Microcontroller

1.1.1 Introduction

A microcontroller (also MCU or µC) is a computer on a chip. It is a type of microprocessor

emphasizing high integration, low power consumption, self-sufficiency and cost-effectiveness, in

contrast to a general-purpose microprocessor (the kind used in a PC). In addition to the usual

arithmetic and logic elements of a general purpose microprocessor, the microcontroller typically

integrates additional elements such as read-write memory for data storage, read-only memory,

such as flash for code storage, EEPROM for permanent data storage, peripheral devices, and

input/output interfaces. At clock speeds of as little as a few MHz or even lower, microcontrollers

often operate at very low speed compared to modern day microprocessors, but this is adequate

for typical applications. They consume relatively little power (milliwatts), and will generally

have the ability to sleep while waiting for an interesting peripheral event such as a button press

to wake them up again to do something. Power consumption while sleeping may be just

nanowatts, making them ideal for low power and long lasting battery applications.

Microcontrollers are frequently used in automatically controlled products and devices, such as

automobile engine control systems, remote controls, office machines, appliances, power tools,

and toys. By reducing the size, cost, and power consumption compared to a design using a

separate microprocessor, memory, and input/output devices, microcontrollers make it

economical to electronically control many more processes.

1.1.2 Microprocessors V/S Microcontrollers

Microprocessor is a device that doesn‘t contain RAM, ROM, no I/O ports on the chip itself.

Addition of these devices mentioned make the systems bulkier and much more expensive, they

have the advantages of versatility such that the designer can decide on the amount of these

devices needed to fit the task at hand. This is not the case with microcontrollers. It is used in

general purpose applications. It doesn‘t provide data storage facility.

A microcontroller has a CPU in addition to a fixed amount of RAM,ROM, I/O ports and a

timer all on a single chip i.e. they are all embedded together on one chip, so, designer can‘t add

any external memory, I/O ports or timer to it. This makes them ideal for many applications in

which cost and space are critical. It is used in specific purpose applications and provides data

storage facility.

44

1.1.3 Microcontroller for Embedded Systems

In the literature discussing microcontrollers, we often see the term Embedded System.

Microcontrollers are widely used in Embedded System products. An Embedded product uses a

microcontroller to do one task and one task only.

In an Embedded System there is only one application software that is typically burned into

ROM and X-86 PC contains or is connected to various Embedded products such as keyboard,

printer, modem, disk controller, sound card, CD-ROM driver, mouse and so on. Each one of

theses peripherals has a microcontroller inside it that performs only one task.

1.2 Why use 8 bit microcontroller

The following features of 8- bit microcontrollers make it useful to be used for IC testing.

(a) Low cost.

(b) Low power consumption

(c) High speed perform

(d) Represent a transition zone between dedicated, high-volume, 4-bit microcontrollers

and the high performance 16 bit microcontrollers.

(e) Bit addressing used for test pin monitoring or program control flags.

(f) 8 – bit word size adequate for many computing tasks and control or monitoring

applications

45

2. Microcontroller AT89S52:

Features:

• Compatible with MCS®-51 Products

• 8K Bytes of In-System Programmable (ISP) Flash Memory

•Endurance: 1000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Fast Programming Time

• Flexible ISP Programming (Byte and Page Mode)

• Green (Pb /Halide-free) Packaging Option

2.1 Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of

in-system programmable Flash memory. The device is manufactured using Atmel‘s high-density

nonvolatile memory technology and is compatible with the industry- standard 80C51 instruction

set and pin-out. The on-chip Flash allows the program memory to be reprogrammed in-system or

by a conventional nonvolatile memory programmer.

By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip,

the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-

effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM,

32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-

level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In

addition, the AT89S52 is designed with static logic for operation down to zero frequency and

supports two software selectable power saving modes.

46

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt

system to continue functioning. The Power-down mode saves the RAM contents but freezes the

oscillator, disabling all other chip functions until the next interrupt or hardware reset.

2.2 Pin Configuration

Fig.7. AT89S52 Pin Diagram

47

2.3 Block Diagram

Fig.8. AT89S52 Block Diagram

2.4 Pin Description

Vcc Supply Voltage

GND Ground

48

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink

eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high

impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during

accesses to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes

during program verification. External pull-ups are required during program

verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the

internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being

pulled low will source current (IIL) because of the internal pull-ups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input

(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the

table.

Port 1 also receives the low-order address bytes during Flash programming and

verification.

Table I. Alternate Functions of Port 1

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers

can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high

by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally

being pulled low will source current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory

and during accesses to external data memory that uses 16-bit addresses (MOVX @

49

DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During

accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits

the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash

programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers

can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high

by the internal

pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled

low will source current (IIL) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S52, as shown in

the following Table.

Table II. Alternate Functions of Port 3

RST (Reset input)

A high on this pin for two machine cycles while the oscillator is running resets the

device. This pin drives high for 98 oscillator periods after the Watchdog times out. The

DISRTO Bit in SFR AUXR (address 8EH) can be used to disable this feature. In the

default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during

Flash Programming.

50

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and

may be used for external timing or clocking purposes. Note, however, that one ALE pulse

is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the

bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution

mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When the

AT89S52 is executing code from external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each access to

external data memory.

EA/Vpp

External Access Enable, EA must be strapped to GND in order to enable the device to

fetch code from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during Flash

programming.

XTAL 1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL 2

Output from the inverting oscillator amplifier.

2.5 Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

Table III

Note that not all of the addresses are occupied, and unoccupied addresses may not be

implemented on the chip. Read accesses to these addresses will in general return random data,

and write accesses will have an indeterminate effect.

51

User software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the new bits will

always be 0.

Timer 2 Registers:

Control and status bits are contained in registers T2CON (shown in Table IV) and T2MOD

(shown in Table VIII) for Timer 2. The register pair (RCAP2H, RCAP2L) are the

Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the

six interrupt sources in the IP register.

Table III. AT89S52 SFR Map and Reset Values

52

Table IV. T2CON – Timer/Counter 2 Control Register

53

Table V. AUXR: Auxiliary Register

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,

two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H

and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The

user should ALWAYS initialize the DPS bit to the appropriate value before accessing the

respective Data Pointer Register.

Power off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF

is set to ―1‖ during power up. It can be set and rest under software control and is not affected by

reset.

54

Table VI. AUXR1: Auxiliary Register 1

2.6 Memory Organization MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes

each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through

1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to

external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel

address space to the Special Function Registers. This means that the upper 128 bytes have the

same addresses as the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in

the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR

space. Instructions which use direct addressing access the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H

(which is P2).

MOV 0A0H, #data

55

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the

following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at

address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data

RAM is available as stack space.

2.7 Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset

(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a

user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).

When the WDT is enabled, it will increment every machine cycle while the oscillator is running.

The WDT timeout period is dependent on the external clock frequency. There is no way to

disable the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH

and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches

16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every

machine cycle while the oscillator is running. This means the user must reset the WDT at least

every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to

WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When

WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse

duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be

serviced in those sections of code that will periodically be executed within the time required to

prevent a WDT reset.

WDT during Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power

down mode, the user does not need to service the WDT. There are two methods of exiting

Power-down mode: by a hardware reset or via a level-activated external interrupt which is

enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,

servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting

Power-down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent

56

the WDT from resetting the device while the interrupt pin is held low, the WDT is not started

until

The interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service

for the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best

to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether

the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit =

0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode,

the user should always set up a timer that will periodically exit IDLE, service the WDT, and

reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the

count upon exit from IDLE.

2.8 Serial Interface

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates.

It is also receive-buffered, meaning it can commence reception of a second byte before

a previously received byte has been read from the receive register. (However, if the first

byte still hasn‘t been read by the time reception of the second byte is complete, one of

the bytes will be lost). The serial port receive and transmit registers are both accessed

at Special Function Register SBUF. Writing to SBUF loads the transmit register, and

reading SBUF accesses a physically second receive register.

The serial port can operate in 4 modes:

Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits

are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator

frequency.

Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0),

8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special

Function Register SCON. The baud rate is variable.


8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the

9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity

bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into

RB8 in Special Function register SCON, while the stop bit is ignored. The baud rate is

programmable to either 1/32 or 1/64 the oscillator frequency.


8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). In fact, Mode 3 is

57

the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is

variable.

In all four modes, transmission is initiated in Mode 0 by the condition RI = 0 and REN =

1. Reception is initiated in Mde 0 by the condition RI = 0 and REN = 1. Reception is initiated

in the other modes by the incoming start bit if REN = 1.

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

The serial port control and status register is the Special Function Register SCON,

shown in Table 2-17. This register contains not only the mode selection bits, but also the

9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupts bits (TI

and RI).

Baud Rates The baud rate in Mode 0 is fixed:

The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register

PCON.

If SMOD = 0 (which is its value on reset), the baud rate is 1/64 the oscillator frequency.

If SMOD = 1, the baud rate is 1/32 the oscillator frequency.

In the 80C51, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow

rate. In case of Timer2, these baud rates can be determined by Timer 1, or by Timer 2,

or by both (one for transmit and the other for receive).

Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or

RCLK in T2CON (Table 5-2). Note that the baud rates for transmit and receive can be different

if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function.

Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure

11-1. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2

causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and

RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by

Timer 2‘s overflow rate according to the fol-lowing equation. The Timer can be configured for

either timer or counter operation. In most applications, it is con-figured for timer operation

(CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator.

Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a

baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The

baud rate formula is given below. where (RCAP2H, RCAP2L) is the content of RCAP2H and

RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure

11-1. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2

does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a 1-to-0

transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,

TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra

external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate

generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the

Timer is incremented every state time, and the results of a read or write may not be accurate. The

RCAP2 registers may be read but should not be written to, because a write might overlap a

reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before

accessing the Timer 2 or RCAP2 registers.

58

When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are

determined by the Timer 1 overflow rate and the value of SMOD as follows:

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured

for either ―timer‖ or ―counter‖ operation, and in any of its 3 running modes. In the

most typical applications, it is configured for ―timer‖ operation, in the auto-reload mode

(high nibble of TMOD = 0010B). In that case, the baud rate is given by the formula

One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt

enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD =

0001B), and using the Timer 1 interrupt to do a 16-bit software reload.

More About Mode 0 - Serial data enters and exits through RXD. TXD outputs the shift clock. 8

bits are transmitted/

received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator

frequency.

Figure 2-24 shows a simplified functional diagram of the serial port in mode 0, and associated

timing.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The ―write to SBUF‖ signal at S6P2 also loads a 1 into the 9th bit position of the transmit

shift register and tells the TX Control block to commence a transmission. The internal

timing is such that one full machine cycle will elapse between ―write to SBUF‖, and activation

of SEND.

SEND enables the output of the shift register to the alternate output function line of P3.0,

and also enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT

CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1

and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the

transmit shift register are shifted to the right one position.

As data bits shift out to the right, zeros come in from the left. When the MSB of the data

byte is at the output position of the shift register, then the 1 that was initially loaded into

the 9th position, is just to the left of the MSB, and all positions to the left of that contain

zeros. This condition flags the TX Control block to do one last shift and then deactivate

SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after

―write to SBUF.‖

Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 of the next machine

cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in

the next clock phase activates RECEIVE.

RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. Shift

CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every

cycle in which RECEIVE is active, the contents of the receive shift register are shifted to

the left one position. The value that comes in from the right is the value that was sampled

at the P3.0 pin at S5P2 of the same machine cycle.

As data bits come in from the right, 1‘s shift out to the left. When the 0 that was initially

loaded into the rightmost position arrives at the leftmost position in the shift and load

SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI,

RECEIVE is cleared and RI is set.

59

More About Mode 1 - Ten bits are transmitted (through TXD), or received (through RXD): a

start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in

SCON. In the

80C51 the baud rate is determined by the Timer 1 overflow rate. In the microcontroller

having Timer 2 feature, it is determined either by the Timer 1 overflow rate, or the Timer

2 overflow rate, or both (one for transmit and the other for receive).

Figure 2-25 shows a simplified functional diagram of the serial port in Mode 1, and associated

timings for transmit and receive.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The ―write to SBUF‖ signal also loads a 1 into the 9th bit position of the transmit shift

register and flags the TX Control unit that a transmission is requested. Transmission

actually commences at S1P1 of the machine cycle following the next rollover in the

divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter,

not to the ―write to SBUF‖ signal).

The transmission begins with activation of SEND, which puts the start bit at TXD. One bit

time later, DATA is activated, which enables the output bit of the transmit shift register to TXD.

The first shift pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the

data byte is at the output position of the shift register, then the 1 that was initially loaded

into the 9th position is just to the left of the MSB, and all positions to the left of that contain

zeroes. This condition flags the TX Control unit to do one last shift and then

deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after ―write to SBUF‖.

Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is

sampled at a rate of 16 times whatever baud rate has been established. When a transition

is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into

the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the

boundaries of the incoming bit times.

2.9 Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three

timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown

in Figure 2.7.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit

in Special Function Register IE. IE also contains a global disable bit, EA, which disables all

interrupts at once.

Note that Table IX shows that bit position IE.6 is unimplemented. User software should not write

a 1 to this bit position, since it may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON.

Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the

service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

60

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers

overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2

flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

Table VII. Interrupt Enable (IE) Register

61

Fig.9. Interrupt Sources

2.10 Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be

configured for use as an on-chip oscillator, as shown in Figure 2.8. Either a quartz crystal or

ceramic resonator may be used. To drive the device from an external clock source, XTAL2

should be left unconnected while XTAL1 is driven, as shown in Figure 2.9. There are no

requirements on the duty cycle of the external clock signal, since the input to the internal

clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high

and low-time specifications must be observed.

62

Fig.10. Crystal Oscillator Connections

Fig.11. External Clock Drive Information1

63

2.11 Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The

mode is invoked by software. The content of the on-chip RAM and all the special functions

registers remain unchanged during this mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset, the device normally resumes

program execution from where it left off, up to two machine cycles before the internal reset

algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited.

To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by

a reset, the instruction following the one that invokes idle mode should not write to a port pin or

to external memory.

2.12 Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down

is the last instruction executed. The on-chip RAM and Special Function Registers retain their

values until the Power-down mode is terminated. Exit from Power-down mode can be initiated

either by a hardware reset or by an enabled external interrupt.

Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be

activated before VCC is restored to its normal operating level and must be held active long

enough to allow the oscillator to restart and stabilize.

64

3. Demultiplexer (74154)

FEATURES

· 16-line demultiplexing capability

· Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs

· 2-input enable gate for strobing or expansion

· Output capability: standard

· ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT154 are high-speed Si-gate CMOS devices and are pin compatible with low

power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT154 decoders accept four active HIGH binary address inputs and provide 16

mutually exclusive active LOW outputs. The 2-input enable gate can be used to strobe the

decoder to eliminate the normal decoding ―glitches‖ on the outputs, or it can be used for the

expansion of the decoder. The enable gate has two AND‘ed inputs which must be LOW to

enable the outputs. The ―154‖ can be used as a 1-to-16 demultiplexer by using one of the enable

inputs as the multiplexed data input. When the other enable is LOW, the addressed output will

follow the state of the applied data.

3.1 Pin Diagram

Fig.12. Pin diagram for 74154

65

3.2. Function Table

Table VIII

3.3 Logic Diagram

Fig.13. Logic Diagram of 74154

66

3.4 Application Circuit(as used in project)

E

Fig.14. Application Circuit of 74154

4. UDN 2981 Channel Driver

Recommended for high-side switching applications that benefit from separate logic and load

grounds, these devices encompass load supply voltages to 50 V and output currents to -500 mA.

These 8-channel source drivers are useful for interfacing between low-level logic and high

current loads. Typical loads include relays, solenoids, lamps, stepper and/or servo motors, print

hammers, and LEDs. All devices may be used with 5 V logic systems — TTL, Schottky TTL,

DTL, and 5 V CMOS. The device packages offered are electrically interchangeable, and will

withstand a maximum output off voltage of 50 V, and operate to a minimum of 5 V. All devices

in this series integrate input current limiting resistors and output transient suppression diodes,

and are activated by an active high input. The suffix ―A‖ indicates an 18-lead plastic dual in-line

package with copper lead frame for optimum power dissipation. Under normal operating

conditions, these devices will sustain 120 mA continuously for each of the eight outputs at an

ambient temperature of +50°C and a supply of 15 V. The suffix ―LW‖ package is provided in a

20-pin wide-body SOIC package with improved thermal characteristics compared to the 18-pin

SOIC version it replaces (100% pin-compatible electrically). The A2982ELW driver is available

for operation over an extended temperature range, down to -40°C. These packages are lead (Pb)

free, with 100% matte-tin lead frame plating.

67

\

4.1 Pin Description

Fig.15. Pin diagram of UDN2981

4.2 Circuit for one driver

Fig.16. Circuit for one driver of UDN2981

68

5. LED Dot Matrix Display

5.1 LED

A light-emitting diode (LED is a semiconductor light source. LEDs are used as indicator

lamps in many devices and are increasingly used for other lighting. Introduced as a

practical electronic component in 1962, early LEDs emitted low-intensity red light, but

modern versions are available across the visible, ultraviolet and infrared wavelengths,

with very high brightness.

When a light-emitting diode is forward biased (switched on), electrons are able to

recombine with electron holes within the device, releasing energy in the form of photons.

This effect is called electroluminescence and the color of the light (corresponding to the

energy of the photon) is determined by the energy gap of the semiconductor. An LED is

often small in area (less than 1 mm2), and integrated optical components may be used to

shape its radiation pattern. LEDs present many advantages over incandescent light

sources including lower energy consumption, longer lifetime, improved robustness,

smaller size, faster switching, and greater durability and reliability. LEDs powerful

enough for room lighting are relatively expensive and require more precise current and

heat management than compact fluorescent lamp sources of comparable output.

Light-emitting diodes are used in applications as diverse as replacements for aviation

lighting, automotive lighting (particularly brake lamps, turn signals and indicators) as

well as in traffic signals. The compact size, the possibility of narrow bandwidth,

switching speed, and extreme reliability of LEDs has allowed new text and video displays

and sensors to be developed, while their high switching rates are also useful in advanced

communications technology. Infrared LEDs are also used in the remote control units of

many commercial products including televisions, DVD players, and other domestic

appliances.

5.2 Dot Matrix Board

A dot matrix display is a display device used to display information on machines,

clocks, railway departure indicators and many and other devices requiring a simple

display device of limited resolution. The display consists of a matrix of lights or

mechanical indicators arranged in a rectangular configuration (other shapes are also

possible, although not common) such that by switching on or off selected lights, text or

graphics can be displayed. A dot matrix controller converts instructions from a processor

into signals which turns on or off lights in the matrix so that the required display is

produced.

69

5.3 Circuit Diagram for 8x8 LED Dot Matrix Board

Fig.17. 8x8 LED dot matrix diagram

6. MAX 232 6.1 Features

Meets or Exceeds TIA/EIA-232-F and ITU

Recommendation V.28

Operates From a Single 5-V Power Supply With 10 uF Charge-Pump Capacitors

Operates Up To 120 kbit/s

Two Drivers and Two Receivers

±30-V Input Levels

Low Supply Current . . . 8 mA Typical

ESD Protection Exceeds JESD 22

2000-V Human-Body Model (A114-A)

70

Upgrade With Improved ESD (15-kV HBM) and 0.1 uF Charge-Pump Capacitors

is Available With the MAX202

Applications in IA/EIA-232-F, Battery-Powered Systems, Terminals, Modems,

and Computers

6.2 Pin Diagram

Fig.18. MAX 232 Pin Diagram

6.3 Description

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to

supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts

TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical

threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each

driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. The driver, receiver,

and voltage-generator functions are available as cells in the Texas Instruments LinASIC

library.

6.4 Logic Diagram

Fig.19. MAX232 Logic Diagram

71

7. AT24C08

7.1 Features

• Single supply with operation from 4.5-5.5V

• Low power CMOS technology

• 1 mA active current typical

• 10mA standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes (4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I2C compatible

• Schmitt trigger, filtered inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 4,000V

• 1,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• 8-pin DIP, 8-lead or 14-lead SOIC packages

• Available for extended temperature range

7.2 Description

The Microchip Technology Inc. 24C08B/16B is an 8K or 16K bit Electrically Erasable

PROM intended for use in extended/automotive temperature ranges. The device is organized

as four or eight blocks of 256 x 8-bit memory with a 2-wire serial interface. The

24C08B/16B also has a page-write capability for up to 16 bytes of data. The 24C08B/16B is

available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC

packages

7.3 Pin Diagram

Fig.20. AT24C08 Pin Diagram

72

7.4 Functional Description

The 24C08B/16B supports a Bi-directional 2-wire bus and data transmission protocol. A

device that sends data onto the bus is defined as transmitter, and a device receiving data as

receiver. The bus has to be controlled by a master device which generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions, while the

24C08B/16B works as slave. Both, master and slave can operate as transmitter or receiver

but the master device determines which mode is activated.

7.5 Bus Characteristics

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is

HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

defined

Bus not Busy (A)

Both data and clock lines remain HIGH.

Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines

START condition. All commands must be preceded by a START condition.

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a

STOP condition. All operations must be ended with a STOP condition.

Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data

line is stable for the duration of the HIGH period of the clock signal. The data on the line

must be changed during the LOW period of the clock signal. There is one clock pulse per

bit of data. \

Each data transfer is initiated with a START condition and terminated with a STOP

condition. The number of the data bytes transferred between the START and STOP

conditions is determined by the master device and is theoretically unlimited, although

only the last 16 will be stored when doing a write operation. When an overwrite does

occur it will replace data in a first in first out fashion.

7.6 Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse which is

associated with this acknowledge bit. The device that acknowledges, has to pull down the

73

SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW

during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold

times must be taken into account. During reads, a master must signal an end of data to the

slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the

slave. In this case, the slave (24C08B/16B) will leave the data line HIGH to enable the

master to generate the STOP condition.

7.7 Device Addressing

A control byte is the first byte received following the start condition from the master device.

The control byte consists of a 4-bit control code, for the 24C08B/16B this is set as 1010

binary for read and write operations. The next three bits of the control byte are the block

select bits (B2, B1, B0). They are used by the master device to select which of the eight 256

word blocks of memory are to be accessed. These bits are in effect the three most significant

bits of the word address.

The last bit of the control byte defines the operation to be performed. When set to one a read

operation is selected, when set to zero a write operation is selected. Following the start

condition, the 24C08B/16B monitors the SDA bus checking the device type identifier being

transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the SDA

line. Depending on the state of the R/W bit, the 24C08B/16B will select a read or write

operation.

7.8 WRITE OPERATION

Byte Write

Following the start condition from the master, the device code (4 bits), the block address (3

bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter.

This indicates to the addressed slave receiver that a byte with a word address will follow after

it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte

transmitted by the master is the word address and will be written into the address pointer of

the 24C08B/16B. After receiving another acknowledge signal from the 24C08B/16B the

master device will transmit the data word to be written into the addressed memory location.

The 24C08B/16B acknowledges again and the master generates a stop condition. This

initiates the internal write cycle, and during this time the 24C08B/16B will not generate

acknowledge signals.

Page Write

The write control byte, word address and the first data byte are transmitted to the

24C08B/16B in the same way as in a byte write. But instead of generating a stop condition

the master transmits up to 16 data bytes to the 24C08B/16B which are temporarily stored in

the on chip page buffer and will be written into the memory after the master has transmitted a

stop condition. After the receipt of each word, the four lower order address pointer bits are

internally incremented by one. The higher order seven bits of the word address remains

constant. If the master should transmit more than 16 words prior to generating the stop

condition, the address counter will roll over and the previously received data will be

74

overwritten. As with the byte write operation, once the stop condition is received an internal

write cycle will begin.

Fig.21. AT24C08 Write Cycle

7.9 Acknowledge Polling

Since the device will not acknowledge during a write cycle, this can be used to determine

when the cycle is complete (this feature can be used to maximize bus throughput). Once the

stop condition for a write command has been issued from the master, the device initiates the

internally timed write cycle. ACK polling can be initiated immediately. This involves the

master sending a start condition followed by the control byte for a write command (R/W =

0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle

is complete, then the device will return the ACK and the master can then proceed with the

next read or write command.

7.10 Write Protection

The 24C08B/16B can be used as a serial ROM when the WP pin is connected to VCC.

Programming will be inhibited and the entire memory will be write-protected.

7.11 READ OPERATION

Read operations are initiated in the same way as write operations with the exception that the

R/W bit of the slave address is set to one. There are three basic types of read operations:

current address read, random read, and sequential read.

75

Current Address Read

The 24C08B/16B contains an address counter that maintains the address of the last word

accessed, internally incremented by one. Therefore, if the previous access (either a read or

write operation) was to address n, the next current address read operation would access data

from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C08B/

16B issues an acknowledge and transmits the 8-bit data word. The master will not

acknowledge the transfer but does generate a stop condition and the 24C08B/ 16B

discontinues transmission.

Random Read

Random read operations allow the master to access any memory location in a random

manner. To perform this type of read operation, first the word address must be set. This is

done by sending the word address to the 24C08B/16B as part of a write operation. After the

word address is sent, the master generates a start condition following the acknowledge. This

terminates the write operation, but not before the internal address pointer is set. Then the

master issues the control byte again but with the R/W bit set to a one. The 24C08B/16B will

then issue an acknowledge and transmits the 8-bit data word. The master will not

acknowledge the transfer but does generate a stop condition and the 24C08B/16B

discontinues transmission.

Sequential Read

Sequential reads are initiated in the same way as a random read except that after the

24C08B/16B transmits the first data byte, the master issues an acknowledge as opposed to a

stop condition in a random read. This\directs the 24C08B/16B to transmit the next

sequentially addressed 8 bit word. To provide sequential reads the 24C08B/16B contains an

internal address pointer which is incremented by one at the completion of each operation.

This address pointer allows the entire memory contents to be serially read during one

operation.

76

Fig.22. AT24C08 Read Cycle

7.12 Noise Protection

The 24C08B/16B employs a VCC threshold detector circuit which disables the internal

erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA

inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

8. Serial Connector (RS232 9 Pin)

The RS232 connector was originally developed to use 25 pins. In this DB25 connector pinout

provisions were made for a secondary serial RS232 communication channel. In practice, only

one serial communication channel with accompanying handshaking is present. Only very few

computers have been manufactured where both serial RS232 channels are implemented.

Examples of this are the Sun SparcStation 10 and 20 models and the Dec Alpha Multia. Also

on a number of Telebit modem models the secondary channel is present. It can be used to

77

query the modem status while the modem is on-line and busy communicating. On personal

computers, the smaller DB9 version is more commonly used today. The diagrams show the

signals common to both connector types in black. The defined pins only present on the larger

connector are shown in red. Note, that the protective ground is assigned to a pin at the large

connector where the connector outside is used for that purpose with the DB9 connector

version.

The pinout is also shown for the DEC modified modular jack. This type of connector has

been used on systems built by Digital Equipment Corporation; in the early days one of the

leaders in the mainframe world. Although this serial interface is differential (the receive and

transmit have their own floating ground level which is not the case with regular RS232) it is

possible to connect RS232 compatible devices with this interface because the voltage levels

of the bit streams are in the same range. Where the definition of RS232 focussed on the

connection of DTE, data terminal equipment (computers, printers, etc.) with DCE, data

communication equipment (modems), MMJ was primarily defined for the connection of two

DTE's directly.

Fig.23. DB9 Pin Configuration

9. Positive Voltage Regulator IC 7805:-

9.1 Features

3 Terminal device

Output Current up to 1A

Output Voltages of 5

Thermal Overload Protection

Short Circuit Protection

Output Transistor Safe Operating Area Protection

Output voltage tolerance of +-4%

Operating temperature -40°C to +125°C

78

9.2 Pin Description

Fig.24. 7805 Pin Descritpion

9.3 Block Diagram

Fig.25. Block Diagram of 7805

79

9.4 General Description

The LM78XX series of three terminal positive regulators are available in the TO-220

package and with several fixed output voltages, making them useful in a wide range of

applications. Each type employs internal current limiting, thermal shut down and safe

operating area protection, making it essentially indestructible. If adequate heat sinking is

provided, they can deliver over 1A output current. Although designed primarily as fixed

voltage regulators, these devices can be used with external components to obtain adjustable

voltages and currents

9.5 Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which damage to the device may occur.

The datasheet specifications should be met, without exception, to ensure that the system

design is reliable over its power supply, temperature, and output/input loading variables.

Fairchild does not recommend operation outside datasheet specifications.

Table IX. Absolute Maximum Ratings For IC 7805

80

9.6 Typical Performance Characteristics:-

Fig.26. Performance Characteristics of 7805

81

CHAPTER 7

TESTING PROCEDURE

82

TESTING PROCEDURE

Any engineering endeavor remains incomplete without successful testing and implementation.

Testing forms a core area of project completion. The testing procedure of the DIGITAL

DISPLAY BOARD is given step by step as under:

First check all the components working properly.

Assemble all components according to circuit diagram of the schematic shown

Check whether all the components are soldered properly. there must not be any open

circuit otherwise the circuit will not work.

When the power is switched ON, red LED starts glowing.

Now connect the USB to RS232 cable to the computer and check its port from device

manager

Now run the application on the computer and check whether the port is working or not

Give +5 volt supply to the circuit through power supply or battery.

Give +5 volt supply to the microcontroller at 40th

pin.

Feed error free and proper program to begin its working.

Add reset button at port no.9 to reset the microcontroller.

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CHAPTER 8

OPERATING PROCEDURE

84

OPERATING PROCEDURE

To operate the digital Display Board we need to follow the following steps:

First check all the connections and then give power to the circuit

Then the display will display the data previously stored in the Memory IC

Then connect the Serial Communication module to the main PCB and also connect the

USB to Serial Converter to the Serial Communication Module

Then open the Application(Provided in the CD) on the computer

Then select the port of the USB port used in the Application

Open the port

Write the Data to be displayed and end with a Full stop (‗.‘).

Then click on ―Send Data‖

After the data is sent, Close the port and exit the application

85

CHAPTER 9

RESULT ANALYSIS

RESULT ANALYSIS

86

The most important part in the completion of a successful project is the attainment of successful

result along with the analysis of the result. The result should be accurate and satisfactory to the

user who is implementing the project.

The aim of our project was to develop a Digital Display Board which had a memory and was

capable of serial communication i.e. which could receive data serially from computer and store

it. This data could then be displayed in a scrolling fashion.

The aim of our project has been achieved as the prototype of Digital Display Board has been

achieved.

87

CHAPTER 10

PROBLEMS FACED

PROBLEMS FACED:

88

Power consumption was very high in testing. So we had to use two adapters.

LED display was showing a light glow due to a stray field of ground potential.

There were some errors in software programming.

Circuit was complicated which created some problems in fabrication.

When project was finished we decided to make a box for final finishing but during that

work some wire connections were broken up and we had to study whole circuit again to

make those connections again.

89

CHAPTER 11

COST ANALYSIS

COST ANALYSIS OF THE PROJECT

90

Even though the cost is kept as low as possible, no compromise is done with the quality of

components used. The cost of the components used is as follows:

COMPONENT COST (RS)

18. Microcontroller IC AT89S52 80

19. 74154 DEMUX 120

20. AT24C08 80

21. UDN2981 30

22. MAX232 40

23. LM7805 10

24. SIP 05

25. LED 8x8 DOT Matrix board 440

26. Crystal Oscillator (11.0592Mhz) 05

27. Resistances

10k Ω 15

330 Ω 15

28. Capacitors

10uF 20

33pF 05

29. Jumpers

8 Pin 100

4 Pin 30

3 Pin 20

30. DC Voltage Adapters 300

31. USB to Serial Connector 200

32. Connecting wires 80

33. PCB 200

34. LEDs 10

91

CHAPTER 13

CONCLUSION

92

CONCLUSION

After the successful completion of the project it can be very well concluded that this project is

suitable to be used in many commercial places like office, school etc. for information display.

There can be further advancements in the project which can lead to an even better quality of

product:

Some of the possible ways are:

The transfer of information from PC to microcontroller can be made wireless

Real time data like Temperature, Humidity etc can be incorporated

Can be used in Hospitals for monitoring patients, in sports stadiums etc.

93

REFERENCES

BIBLIOGRAPHY:

www.howstuffworks.com

www.wikipedia.com

www.wikibooks.com

http://www.instructables.com/id/LED-Dot-Matrix-Display/

www.electronicsforu.com

The 8051 microcontroller and embedded systems- A. MAZIDI

http://www.howstuffworks.com/

http://www.wikipedia.com/

http://www.wikibooks.com/

http://www.instructables.com/id/LED-Dot-Matrix-Display/

http://www.electronicsforu.com/

Final Report 5

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