Field Programmable Gate Array Testing

Chapter 12Chapter 12

Field Programmable Gate Array TestingField Programmable Gate Array Testing

EE141System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 11

Field Programmable Gate Array TestingField Programmable Gate Array Testing

What is this chapter about?What is this chapter about?

� Field Programmable Gate Arrays (FPGAs)� Have become a dominant digital implementation

media� Reconfigurable to implement any digital logic

function

� Focus on


� Focus on� Testing challenges due to programmability and

complexity� Overview of testing approaches� Test and diagnosis of various resources

� New frontiers in FPGA testing

FPGA TestingFPGA Testing

� Overview of FPGAs� Architecture, Configuration, & Testing Problem

� Testing Approaches� BIST of Programmable Resources


� BIST of Programmable Resources� Logic Resources

– Logic Blocks, I/O Cells, & Specialized Cores– Diagnosis

� Routing Resources

� Embedded Processor Based Testing� Concluding Remarks

Field Programmable Gate ArraysField Programmable Gate Arrays� Configuration

Memory� Programmable

Logic Blocks (PLBs)


(PLBs)� Programmable

Input/Output Cells� Programmable

Interconnect

Typical Complexity = 5 million Typical Complexity = 5 million –– 1 billion transistors1 billion transistors

1110011010001000100101010001011111100110100010001001010100010111000101001010101010010010001000100010100101010101001001000100010101001001001100100100001111000101010010010011001001000011110001100101000100001100100010100010010010100010000110010001010001001001001000101001010101001001001100100100010100101010100100100101000101001010001010010100100010100010100101000101001010010001

Basic FPGA OperationBasic FPGA Operation� Writing configuration

memory (configuration) ⇒defines system function� Input/Output Cells� Logic in PLBs� Connections between

PLBs & I/O cellsChanging configuration


010001010010100010100101001000101000101001010001010010100100010010101011101010101010101010101001010101110101010101010101010101011110111110000000000000011010010111101111100000000000000110100111110000100111000001110010010101111100001001110000011100100101000000001111100100100010100111000000000011111001001000101001110010010100001111000111000100101010100101000011110001110001001010101010101010101001010010101010010101010101010100101001010101001001010101010101010010010010101010101010101001001001

� Changing configuration memory data (reconfiguration) ⇒changes system function� Can change at anytime� Even while system

function is in operation– Dynamic partial

reconfiguration

FPGA ArchitecturesFPGA Architectures� Early FPGAs

� NxN array of unit cells– Unit cell = CLB + routing

� Special routing along center axes

� I/O cells around perimeter� Next Generation FPGAs

� MxN array of unit cells� Added small block RAMs at edges


� Added small block RAMs at edges� More Recent FPGAs

� Added larger block RAMs in array� Added multipliers � Added Processor Cores (PC)

� Latest FPGAs� Added DSP cores w/multipliers� I/O cells along columns for BGA

PC PC

PC

PC

Combinational Logic FunctionsCombinational Logic Functions

� Gates are combined to create complex circuits

� Multiplexer example� If S = 0, Z = A

A

S

B

Z

Truth table


� If S = 1, Z = B� Common digital circuit� Heavily used in FPGAs

– Select input (S) controlled by configuration memory bit

0

1

A

B

S

Z

Logic symbol

01

S A B Z0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Truth table

LookLook--up Tablesup Tables� Using multiplexer

example� Configuration

memory holds truth table

� Input signals

0

1

A

B

S

Z

Multiplexer

S A B Z0 0 0 0

Truth table0 Z

0

1

0

1

0

1

0

0

1

1

1


� Input signals connect to select inputs of multiplexers to select output value of truth table for any given input value

0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

B A S

1

0

1

0

1

0

1

0

1

0

1

1 0 1

1

Basic PLB StructureBasic PLB Structure� Look-up table (LUT) for combinational logic

� Store truth table in LUT (typically 3 to 6 inputs)� Some LUTs can also act as RAM/shift register

� Flip-flops for sequential logic� Programmable clock enable, set/reset


� Special logic� Large logic functions with Shannon expansion� Fast carry for adders and counters

carry in

LUT/RAM Carry &

ControlLogic

Flip-flop/Latch

4

carry out

3

Control

OutputQ output

Input[1:4]

clock, enable, set/reset

Data In

Add

ress

Dec

oder

In0

In1

en0

en1

en2

en3

LookLook--up Table Based RAMsup Table Based RAMs� Normal LUT mode

performs read operations

� Address decoder with write enable 0 Z

0

1

0

1

0

1

0

0

1

1

Wri

te A

dd

ress


Add

ress

Dec

oder

WriteEnable

In2 en4

en5

en6

en7

with write enable generates load signals to latches for write operations

� Small RAMs but can be combined for larger RAMs

In0 In1 In2

1

0

1

0

1

0

1

0

1

0

1

Read Address

Wri

te A

dd

ress

Tri-state Control

Input/Output CellsInput/Output Cells� Bi-directional buffers

� Programmable for input or output signals� Tri-state control for bi-directional operation� Flip-flops/latches for improved timing

– Set-up and hold times


Bi-directional

Buffer

Output Data

Input Data

to/frominternal routing

resources Pad

– Set-up and hold times– Clock-to-output delay

� Pull-up/down resistors

� Routing resources� Connections to core of array

� Programmable I/O voltage & current levels

Interconnect NetworkInterconnect Network

� Wire segments of varying length� xN = N PLBs in length

– Typical values of N = 1, 2, 4, 6, 8

� Long lines– xH = half the array in length

configbit

Wire A

Wire B


– xH = half the array in length– xL = full array in length

� Programmable Interconnect Points (PIPs)� Transmission gate connects to 2 wire segments

– Controlled by configuration memory bit

� Four basic types of PIPs

� Break-point PIP� Connect or isolate 2 wire segments

� Cross-point PIP� 2 nets straight through� 1 net turns corner and/or fans out

� Compound cross-point PIP� Collection of 6 break-point PIPs

Programmable Interconnect PointsProgrammable Interconnect Points


� Collection of 6 break-point PIPs– Can route 2 isolated signal nets

� Multiplexer PIP� Directional and buffered� Main routing resource in recent FPGAs� Select 1-of-N inputs for output

– Decoded MUX PIP – N configuration bits select from 2N inputs– Non-decoded MUX PIP – 1 configuration bit per input

Recent Architectural TrendsRecent Architectural Trends� Addition of specialized cores:

� Memories– Single and dual-port RAMs– FIFO (first-in first-out)– ECC (error correcting codes)

� Digital signal processors (DSPs)– Multipliers– Accumulators


– Accumulators– Arithmetic/logic units (ALUs)

� Embedded processors– Hard core (dedicated processors)

� With dedicated program/data memories

� Otherwise, programmable RAMs in FPGA used for program/data memories

– Soft core (synthesized from a HDL)

= PLBs

= I/O cells

= special cores

= routing resources

FPGA ResourcesFPGA Resources� Types and sizes of resources vary with FPGA family

� Example: LUTs vary from 3-input to 6-input– 4-input LUTs are most common

� Typical ranges for some commercially available FPGAs

FPGA Resource Small FPGA Large FPGA

LogicPLBs per FPGA 256 25,920

LUTs and flip-flops per PLB 1 8


LUTs and flip-flops per PLB 1 8

RoutingWire segments per PLB 45 406

PIPs per PLB 139 3,462

SpecializedCores

Bits per memory core 128 36,864

Memory cores per FPGA 16 576

DSP cores 0 512

OtherInput/output cells 62 1,200

Configuration memory bits 42,104 79,704,832

Configuration InterfacesConfiguration Interfaces� Master mode (Serial or Parallel options)

� FPGA retrieves configuration from ROM at power-up

� Slave (Serial or Parallel options)� FPGA configured by external source (i.e., a µP)� Used for dynamic partial reconfiguration

� Boundary Scan Interface


� Boundary Scan Interface� 4-wire IEEE standard serial interface for testing� Write and read access to configuration memory� Interfaces to FPGA core internal routing network� Not available in all FPGAs

clock

PROM withConfig Data

data out

CCLK

FPGA inMaster ModeDin Dout

CCLK

FPGA inSlave Mode

Din Dout

CCLK

FPGA inSlave Mode

Din Dout

FPGA Configuration MemoryFPGA Configuration Memory

� PLB addressable� Good for partial reconfiguration� X-Y coordinates of PLB location to be written

– “Z” coordinate identifies which resources will be configured

� Frame addressable


� Frame addressable� Vertical or horizontal frame

– Vertical frames most common

� Access to all PLBs in frame– Only portion of logic and routing

resources accessible in a given frame– Many frames required to configure PLBs & routing

Configuration TechniquesConfiguration Techniques� Full configuration & readback

� Simple configuration interface– Automatic internal calculation of frame address

� Long download time for large FPGAs

� Partial reconfiguration & readback� Only change portions of configuration memory with


� Only change portions of configuration memory with respect to reference design

– Reduces download time for reconfiguration� Requires a more complicated configuration interface

– Command Register (CMR)– Frame Length Register (FLR)– Frame Address Register (FAR)– Frame Data Register (FDR)

Configuration TechniquesConfiguration Techniques� Compressed configuration

� Requires multiple frame write capability– Write identical frames of config data to multiple frame

addresses

� Extension of partial reconfiguration interface capabilities


capabilities– Frame address is much smaller than frame of

configuration data

� Reduces download time for initial configuration depending on

– Regularity of system function design– % utilization of array

� Unused portions written with default configuration data

FPGA Testing TaxonomyFPGA Testing TaxonomyTest Approach Attribute Classification

Test pattern application and output response analysis

Internal (BIST) External

System-level testing Off-line On-line

System application Independent Dependent

Target programmable resourcesLogic Routing

PLBs I/O cells Cores Local Global


Target programmable resourcesPLBs I/O cells Cores Local Global

� On-line test while system is operational� Off-line test while system is out-of-service

� Application-dependent testing tests only those FPGA resources used by intended system function� Application-independent testing tests all FPGA resources

FPGA Test ConfigurationsFPGA Test Configurations� More test configurations required for routing

resources than for logic resources� Data below from publications on actual test

configuration implementations in commercial FPGAsFPGA Number of Test Configurations

Vendor Series PLBs Routing Cores ReferenceORCA2C 9 27 0


LatticeORCA2C 9 27 0 [Abramovici 2001]

[Stroud 2002b]ORCA2CA 14 41 0

Atmel AT40K/AT94K 4 56 3 [Sunwoo 2005]

Cypress Delta39K 20 419 11 [Stroud 2000]

Xilinx

4000E/Spartan 12 128 0[Stroud 2003]

4000XL/XLA 12 206 0

Virtex/Spartan-II 12 283 11 [Dhingra 2005]

Virtex-4 15 ? 15 [Milton 2006]

A Simple PLB ArchitectureA Simple PLB Architecture� Two 3-input LUTs

� Can implement any 4-input combinational logic function

� Can implement full adder– Carry in LUT C– Sum in LUT S

� 1 flip-flop� Programmable:

CoutCout

D2D2--00

SoutSout0011 00

11

SmuxSmuxSOmuxSOmux

LUT CLUT C8x18x1

LUT SLUT S8x18x1

33

CC00CC11CC22CC33CC44CC55CC66CC77

111 110 101 100 011 010 001 000111 110 101 100 011 010 001 000D2D2--00

outoutLUTLUT


� Programmable:– Active levels– Clock edge– Set/reset

� 22 configuration memory bits� 8 per LUT

– C7-C0 and S7-S0� 6 control bits

– CB5-CB0

D3D3

FFFF

CBCB44

ClockClock

Set/ResetSet/Reset

CBCB33

11

0011

0011

Clock EnableClock Enable

CBCB = Configuration= ConfigurationMemory BitMemory Bit

CEmuxCEmux SRmuxSRmux

CBCB55

CBCB11CBCB00 CBCB22

8x18x1

Test Configurations for Simple PLBTest Configurations for Simple PLB� All configuration memory bits must be tested for both

logic values (0 and 1) assuming exhaustive input patterns� Output effects for each logic value must be observed

� Exclusive-OR (XOR) and exclusive-NOR (XNOR) functions are good for testing LUTs� Put opposite functions in adjacent LUTs to produce opposite logic

values at inputs to subsequent logic functions

� Fault coverage results below are based on collapsed


� Fault coverage results below are based on collapsed single stuck-at gate-level fault model (174 faults total)

Configuration Bits Configuration #1 Configuration #2 Configuration #3

LUT C (C7 - C0) XNOR (01101001) XOR (10010110) XOR (10010110)

LUT S (S7 - S0) XOR (10010110) XNOR (01101001) XNOR (01101001)

CB0 - CB5 000010 111110 000001

Individual FC 149/174 = 85.6% 149/174 = 85.6% 108/174 = 62.1%

Cumulative FC 85.6% 97.7% 100%

BIST for FPGAsBIST for FPGAs� Basic idea:

� Program some logic resources to act as– Test pattern generators (TPGs)– Output response analyzers (ORAs)– Resources under test


– Resources under test� Logic resources as blocks under test (BUTs)� Routing resources as wires under test (WUTs)

� Goal:� Minimize number of test configurations to

minimize download time– Download time dominates total test time

TPG and ORA ImplementationsTPG and ORA Implementations� TPG implementation depends on test algorithm

� May be implemented in different resources (see table below)� Multiple TPGs prevent faulty TPG from escaping detection� Lower bound on number of PLBs per TPG, TPLB = BIN ÷ NFF

– BIN = number of inputs to BUT– NFF = number of FFs/PLB

� ORAs most efficiently implemented in PLBs� Number of PLBs needed for ORAs, OPLB = (NBUT × BOUT) ÷ NFF


� Number of PLBs needed for ORAs, OPLB = (NBUT × BOUT) ÷ NFF– BOUT = number of outputs from BUT– NBUT = number of BUTs

Resource Under Test TPGs ORAs

PLBs PLBs or DSP cores PLBs

LUT RAMs PLBs or DSP and RAM cores PLBs

I/O cells PLBs or DSP and RAM cores PLBs

Cores (memories, DSPs, etc.) PLBs PLBs

Interconnect PLBs PLBs

TPG AlgorithmsTPG Algorithms� Small logic functions (PLBs, IOBs) can be tested

with pseudo-random test patterns� LFSRs or counting patterns

� Large logic functions (RAMs, DSPs) require specialized test algorithms for high fault coverage� Below are examples of typical RAM test algorithms


� Below are examples of typical RAM test algorithms

Algorithm March Test SequenceMarch Y ↨(w0); ↑(r0, w1,r1); ↓(r1, w0, r0);↑(r0)

March LRw/o BDS

↨(w0); ↓(r0, w1); ↑(r1, w0, r0, r0, w1);↑(r1, w0); ↑(r0, w1, r1, r1, w0); ↑(r0)

March LRwith BDS

↨(w00); ↓(r00, w11); ↑(r11, w00, r00, r00, w11); ↑(r11, w00); ↑(r00, w11, r11, r11, w00);

↑(r00, w01, w10, r10); ↑(r10, w01, r01); ↑(r01)

Notation: w0 = write 0 (or all 0’s), r1 = read 1 (or all 1’s) ↑= address up, ↓= address down, ↨ = address either way

Output Response AnalyzersOutput Response Analyzers� Comparison-based

� XOR with OR feedback from flip-flop

– Latches mismatches observed due to faults

� Results retrieval� ORA with shift register

Pass/Failshift data

shift mode

BUTj outputBUTk output

BUTj output


� ORA with shift register– Requires additional logic

� Configuration memory readback

– Read contents of ORA flip-flops

� Good with partial configuration memory readback capabilities

Pass/Fail

BUTj outputnBUTk outputn

BUTj output1BUTk output1

Pass/Fail

BUTj outputBUTk output

Logic Resource BIST ArchitecturesLogic Resource BIST Architectures

� Basic comparison� Multiple TPGs drive alternating

columns (rows) of blocks under test (BUTs)

� BUTs in center of array observed by 2 sets of ORAs and compared

Basic Comparison


by 2 sets of ORAs and compared with 2 other BUTs

� BUTs along edges of array observed by only 1 set of ORAs

– Some loss of diagnostic resolution

� Originally used to test PLBs– Later used to test specialized cores

=TPG

=BUT

=ORA


� Circular Comparison� Multiple TPGs drive alternating

columns (rows) of blocks under test (BUTs)

� All BUTs observed by 2 sets of Circular Comparison


� All BUTs observed by 2 sets of ORAs and compared with 2 other BUTs

– Good diagnostic resolution

� Originally used to test specialized cores

– Later used to test PLBs and I/O cells

=TPG

=BUT

=ORA


� Expected Results comparison� Multiple TPGs

– One set of TPGs drive BUTs– Other set of TPGs produce expected

results for comparison with outputs of BUTs

� BUTs observed by 1 set of ORAs

Expected Results

expected results

testpatterns


� BUTs observed by 1 set of ORAs and compared with expected results from TPGs

– Simple diagnosis since failing ORA position indicates faulty BUT

� Good when expected results can be algorithmically generated easily

– Example: RAM test algorithms

� Originally used to test RAM cores

=TPG

=BUT

=ORA

Logic Resource Diagnostic ProcedureLogic Resource Diagnostic Procedure1. Record ORA results; 1= failure indication. 2. For every set of 2 or more consecutive ORAs with 0s, enter

0s for all BUTs observed by these ORAs; the BUTs are fault-free.

3. For every adjacent 0 and 1 followed by an empty space, enter 1 to indicate BUT is faulty; continue while such entries exist.

4. If an ORA indicates a failure but both BUTs monitored by the


4. If an ORA indicates a failure but both BUTs monitored by the ORA are fault-free, one of the following conditions exist:

A. A fault in routing resources between one of the BUTs and the ORA, B. ORA is faulty, or C. There are more than 2 consecutive BUTs with equivalent faults (for

circular comparison only); reorder circular comparison and repeat test and diagnostic procedure.

5. Remaining BUTs marked as unknown may be faulty; reorder circular comparison or rotate basic comparison architecture by 90°, repeat test and diagnostic procedure.

Diagnostic Procedure ExamplesDiagnostic Procedure Examples� Note that B4 and B5 have equivalent faults in Example A� Circular comparison provides better diagnostic resolution

� Also indicates when more than 2 consecutive BUTs with equivalent faults (Example C) Example A Example B Example C

BIST Architecture Basic Circular Basic Circular Basic Circular

Diagnostic Step 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3

B1 0 0 0 0 0 0 0 0 1 0 0


B1 0 0 0 0 0 0 0 0 1 0 0O12 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1B2 0 0 0 0 0 0 0 0 0 0 0 0

O23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0B3 0 0 0 0 0 0 0 0 0 0 0 0

O34 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0B4 1 1 1 1 0 0 0 0

O45 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1B5 1 1 ? 1 1 0 0

O56 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0B6 ? 0 0 ? 0 0 1 0 0

O61 0 0 0 0 0 0 0 0 0

Testing Routing ResourcesTesting Routing Resources� Comparison-based BIST approach� Developed for on-line FPGA BIST

� Testing restricted to routing resources for 2 rows or 2 columns of PLBs

� Small Self-Test AReas (STARs)� Comparison-based ORA

WUTsWUTs

TPGTPG

ORAORA


� Comparison-based ORA� Later applied to off-line BIST

� Fill FPGA with STARs� Tests run concurrently� Diagnostic resolution to STAR

� Easier BIST development� But more BIST configurations

STARSTAR

ORAORA

FPGA

TT

OO

TT

OO

TT

OO

TT

OO

TT

OO

Testing Routing ResourcesTesting Routing Resources� Original parity-based BIST approach

� Parity bit routed over fault-free resources– What is fault-free until you’ve tested it?

� Modified parity-based approach� N-bit up-counter with even parity, and� N-bit down-counter with odd parity

– Gives opposite logic values for

parityparity--checkcheckbasedbased--ORAORA

WUTsWUTsparityparity

bitbit

TPGTPG

ORAORA

TPGTPG


– Gives opposite logic values for� Stuck-on PIPs & bridging faults

� Parity used as test pattern– N+1 wires under test

� Good for small PLBs– like our simple PLB example

� Make STARs as small as possible� Better diagnostic resolution� Easier BIST development

OORRAA

WUTsWUTs

TPGTPGCC11ParPar

+

CC00

Testing Routing ResourcesTesting Routing Resources� Testing typically separated by routing resources

� Global - interconnects non-adjacent logic resources� Local - interconnects adjacent logic resources and

connects logic resources to global routing

� Additional test configurations swap positions of TPGs and ORAs to reverse direction of signal flow


TPGs and ORAs to reverse direction of signal flow to test directional, buffered routing resources� Multiplexer PIPs are a good example

=TPG

=ORAglobal routing local routing

PLB feed-throughlocal routing

adjacent PLBs

Reducing Test TimeReducing Test Time� Orient BIST architecture to configuration memory

� Align along rows/columns depending on FPGA structure� Downloading BIST configurations

� Compressed configuration for initial download� Partial reconfiguration for subsequent downloads

– Reduce number of frames written between configurations� Keep routing constant between BIST configurations


� Optimize order of BIST configuration application

� Retrieving BIST results� Partial configuration memory readback

– Eliminates ORA logic for scan chain� Allows concurrent testing of more resources

– Minimize number of frames to be read

� Dynamic partial reconfiguration– Read BIST results after a series of BIST configurations

� Slight loss in diagnostic resolution

Embedded Processor Based BISTEmbedded Processor Based BIST� New area of R&D in FPGA testing� Basic idea:

� Embedded processor core– Hard or soft core

� Configures FPGA for BIST– Via internal configuration access port (ICAP)

� Alternative: download initial BIST configuration

� Executes BIST sequence

Processor core, TPGs and interface

to ICAP circuitryTest session #1


� Executes BIST sequence– May provide TPG functionality

� Retrieves BIST results– May perform diagnostic procedure

� Reconfigures FPGA for subsequent BIST configurations

� Soft core requires two test sessions to test area occupied by processor core during first test session

= ORA

= BUT

Test session #1

Processor core, TPGs and interface

to ICAP circuitry

Test session #2

Embedded Processor BISTEmbedded Processor BIST� Overall reduction in total test time

� Algorithmic reconfiguration faster than external download– ≈10 to 25 times faster– Results below from actual implementation in commercial FPGA

� Can be loaded into processor program memory for on-demand BIST and diagnosis of FPGA� Good for fault-tolerant applications where system function


� Good for fault-tolerant applications where system function is reconfigured around diagnosed fault(s)

Resource Function External Processor Speed-up

PLBBIST

Download 7.680 sec 0.101 sec 76.0Execution 0.016 sec 0.085 sec 0.2Total time 7.696 sec 0.186 sec 41.4

RoutingBIST

Download 20.064 sec 0.110 sec 182.4Execution 0.026 sec 0.343 sec 0.075Total time 20.090 sec 0.453 sec 44.3

Total Test Time 27.786 sec 0.639 sec 43.5

Concluding RemarksConcluding Remarks

� Growing use of FPGAs in systems and SOCs� FPGA testing is necessary but difficult due to

� Programmability� Complex programmable interconnect network� Constantly growing size and changing architectures


� Constantly growing size and changing architectures� Incorporation of new and different specialized cores

� Test & diagnosis allows fault-tolerant applications� New FPGA capabilities assist in testing solutions

� Dynamic partial reconfiguration and readback� Configuration/reconfiguration by embedded processor

cores

Field Programmable Gate Array Testing

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