Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays

Fast Waveform Digitizing in Radiation Detection using Switched Capacitor

Arrays

Stefan RittPaul Scherrer Institute, Switzerland

Sept 25th, 2009 CMOS ET Vancouver 2

Question ?

4 channels5 GSPS1 GHz BW8 bit (6-7)15k$

4 channels5 GSPS1 GHz BW8 bit (6-7)15k$

4 channels5 GSPS1 GHz BW11.5 bits1k$USB Power

4 channels5 GSPS1 GHz BW11.5 bits1k$USB Power


The need for speed

Det chan

Q-ADC

Disc.TDC

Trigger

• Traditional technique•Gated charge ADCs•Constant Fraction Disc.•Time-to-Digital Conv.

• High rate applications•Pile-up becomes an issue Waveform digitizing

•Issues: Limited speed andresolution

• High channel counts•Power consumption•FADC Costs

Det chan FADC

Moving average baseline

hit

s

Needed: >3 GSPS 12 bit


Switched Capacitor Array

Shift RegisterClock

IN

Out

“Time stretcher” GHz MHz“Time stretcher” GHz MHz

Waveform stored

Inverter “Domino” ring chain0.2-2 ns

FADC 33 MHz


DRS4

• Designed for the MEGexperiment at PSI,Switzerland

• UMC 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

• 8+1 ch. each 1024 cells

• Differential inputs,differential outputs

• Sampling speed 700 MHz … 5 GHz,PLL stabilized

• Readout speed 30 MHz, multiplexedor in parallel

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


Comparison with other chipsMATACQ D. Breton

LABRADORG. Varner

DRS4this talk

Bandwidth (-3db) 300 MHz > 1000 MHz 950 MHz

Sampling frequency

50 MHz…2 GHz

10 MHz … 3.5 GHz

700 MHz … 6 GHz

Full scale range ±0.5 V +0.4 …2.1 V ±0.5 V

Effective #bits 12 bit 10 bit 11.5 bit

Sample points 1 x 2520 9 x 256 9 x 1024

Frequency PLL YES NO YES

Digitization 5 MHz N/A 30 MHz

Readout dead time

650 s 150 s 3 s – 370 s

Integral nonlinearity

± 0.1 % ± 0.1 % ± 0.05%

Radiation hard No No Yes (chip)

Board V1729 (CAEN)

- V17xx (CAEN)


Switched Capacitor Array

•Pros (DRS4 chip)

• High speed (5 GHz) high resolution (11.5 bit resol.)

• High channel density (9 channels on 5x5 mm2)

• Low power (10-40 mW / channel)

• Low cost (~ 10$ / channel)

•Cons

• No continuous acquisition

• Limited sampling depth

• Nonlinear timing

t t t t t

Goal: Minimize Limitations


How to minimize dead time ?

• Fast analog readout: 30 ns / sample

• Parallel readout

• Region-of-interestreadout

• Simultaneouswrite / read

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

W SRO UT

CO NFIG REGISTER

RSRLO AD

DENABLE

W SRIN

DW RITE

DSPEED PLLO UT

DO MINO WAVE CIRCUIT

PLL

AGND

DG ND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OU T0

OU T1

OU T2

OU T3

OU T4

OU T5

OU T6

OU T7

OU T8/MUXOUT

BIASO-O FS

RO FSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS

AD922212 bit

8 channels


ROI readout mode

readout shift register

Triggerstop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz 3 us dead time

300,000 events / sec.

e.g. 100 samples @ 33 MHz 3 us dead time

300,000 events / sec.


Daisy-chaining of channels

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Domino Wave

1

clock

0

1

0

1

0

1

0

enableinput

enableinput

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Domino Wave

1

clock

0

1

0

1

0

1

0

enableinput

enableinput

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling

depth

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling

depth


Simultaneous Write/Read

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

0

FPGA

0

0

0

0

0

0

0

1 Channel 0

Channel 11

Channel 0 readout

8-foldanalog multi-event

buffer

Channel 21

Channel 10

Expected crosstalk ~few mVExpected crosstalk ~few mV


Interleaved samplingdela

ys

(167p

s/8 =

21ps)

G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

6 GSPS * 8 = 48 GSPS

Possible with DRS4 if delay is implemented on PCBPossible with DRS4 if delay is implemented on PCB


Trigger and DAQ on same board

• Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS

• FPGA can make local trigger(or global one) and stop DRSupon a trigger

• DRS readout (5 GHz samples)though same 8-channel FADCs

an

alo

g fro

nt e

nd

DRSFADC12 bit

65 MHzM

UX FPGA

trigger

LVDS

SRAM

DRS4

glo

bal tr

igger

bu

s

“Free” local trigger capability without additional hardware

“Free” local trigger capability without additional hardware

Performance of SCA Chips

Test Results


Bandwidth

• Passive Input: Bandwidth is determined by bond wire and internal bus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

• Active Inputs: ~300 MHz with currentCMOS technology (MATACQ)

• Near future: 130 nm technologymight improve this slightly

850 MHz (-3dB)

QFP package

Measurement


Timing jitter

t1 t2 t3 t4 t5

• Inverter chain has transistor variations ti between samples differ “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity” TDi= ti – tnominal

• “Integral temporal nonlinearity”TIi = ti – itnominal

• “Random aperture jitter” = variation of ti between measurements

• Inverter chain has transistor variations ti between samples differ “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity” TDi= ti – tnominal

• “Integral temporal nonlinearity”TIi = ti – itnominal

• “Random aperture jitter” = variation of ti between measurements

TD1 TI5


Fixed jitter calibration

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TDi on a statistical basis

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TDi on a statistical basis


Fixed Pattern Jitter Results

• TDi typically ~50 ps RMS @ 5 GHz

• TIi goes up to ~600 ps

• Jitter is mostly constant over time, measured and corrected

• Residual random jitter (RMS)• 25 ps MATACQ• 10 ps Labrador • 3-4 ps DRS4

SCA technology can replace high resolution TDCs

SCA technology can replace high resolution TDCs

Applications of SCA Chips

What can we do with this technology?


On-line waveform display

click

templatefit

pedestalhisto

848PMTs

“virtual oscilloscope”“virtual oscilloscope”


Pulse shape discrimination

)tt[...]θ.. )tθ(td)/τt(te

/τ)t(te i/τ)t(t

eAV(t)r00

000

CsB

Leading edge Decay time AC-coupling Reflections

Example: / source in liquid xenon detector (or: /p in air shower)Example: / source in liquid xenon detector (or: /p in air shower)


-distribution

= 21 ns

= 34 ns

Waveforms can be clearly

distinguished

= 21 ns

= 34 ns

Waveforms can be clearly

distinguished


Template Fit

• Determine “standard” PMT pulse by averaging over many events “Template”

• Find hit in waveform

• Shift (“TDC”) and scale (“ADC”)template to hit

• Minimize 2

• Compare fit with waveform

• Repeat if above threshold

• Store ADC & TDC values

Experiment500 MHz sampling

Pile-up can be detected if two hits are separated in time by ~rise time of signal

Pile-up can be detected if two hits are separated in time by ~rise time of signal


Experiments using DRS chip

MAGIC-II 400 channels DRS2MAGIC-II 400 channels DRS2MEG 3000 channels DRS4MEG 3000 channels DRS4

BPM for XFEL@PSI1000 channels DRS4 (planned)

MACE (India) 400 channels DRS4 (planned)MACE (India) 400 channels DRS4 (planned) PETPET


Datasheet

http://drs.web.psi.ch/datasheetshttp://drs.web.psi.ch/datasheets


Evaluation Board

• DRS4 can be obtained from PSI on a “non-profit” basis

• Delivery “as-is”

• Costs ~ 15-20 CAN$/chn

• USB Evaluation board as reference design

• Anybody wants to build a pocket scope?


Conclusions

• This is Exciting Stuff!

• DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 4 ps timing accuracy, other chips similar

• More development in the pipeline

• Fast waveform digitizing with SCA chips will have a big impact on particle detection in the next future

• Other fields should benefit from this development

LABRADOR: http://www.phys.hawaii.edu/~idlab/MATACQ: http://matacq.free.fr/DRS4: http://drs.web.psi.ch

Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays

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