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Farhan Mohamed Ali (W2-1)Jigar Vora (W2-2)Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4)

Presentation 8

MAD MAC 525

22nd March, 2006Functional Block and Simulations

W2

Project Objective:Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics.

Design Manager: Zack Menegakis

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MAD MAC 525 Status:Project chosenSpecifications definedArchitecture

DesignBehavioral VerilogTestbenchesVerilog : Gate Level DesignFloor plan Schematics and Analog VerificationsLayout of basic gates and small blocks Large block layouts, extractions, LVS, simulations (in progress) Spring Break

To be doneFull chip layout and simulation

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RegArray A RegArray B RegArray C

Multiplier Exp Calc Align

Adder/SubtractorControlLogic

&Sign

Dtrmin

Normalize

Round

Ovf Checker

Leading 0 Anticipator

10 10 10

5

55

1435225

4

36

14

101

5

5

Input Input Input

Output

16 16 16

16RegY

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1

1

1

Block Diagram

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Design Decisions• Pipelining Stages: Add another stage in

multiplier since adder is very fast. – Projected speed is at least 400 MHz – Exceeds the design goal of 300MHz

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Pipelining Stages

MultiplierAlign

C

Reg A

Reg

BExpCalc

Reg C

Pipeline Reg Pipeline Reg

AdderLd Zero

Pipeline Reg

NormalizeRound

Reg Y

Pipeline Reg

Overflow checker

Pipeline Reg

Pipeline Reg

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Timing DiagramPipeline stage 1

Pipeline stage 2

Pipeline stage 3

Pipeline stage 4

Pipeline stage 5

Multiplier lower 7 outputs

Multiplier mid 4 outputs

Multiplier top 11 outputs

Adder Normalize

Exponent calculator

Holds exponent calculator?

Align Zero Counter

Round

Holds exponent calculator bits

Holds exponent calculator bits

Overflow Checker

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New Floorplan

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Design Decisions• Pipelining Stages: Add another stage in

multiplier since adder is very fast. – Projected speed is at least 400 MHz – Exceeds the design goal of 300MHz

• Optimized adder design which implements carry look ahead architecture – Propagation delay of around 800ps (1250MHz)– Bit slicing the adder in the layout

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Adder Schematic

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Adder Schematic Simulation

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Adder Bit Slice Layout

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Transistor Count

Area in um2

Prop. Delay

Power in mW (350MHz)

Multiplier 3600 16560 4.64n 8.5Exponents 738 3800 942p 1.608Align 500 2990 637p 0.393Adder 3174 15870 1n 5.236Leading 0 364 1222 551p 0.857Normalize 942 3176 430p 2.291Round 462 2310 948p 0.631OvfCheck 100 500 475p 0.13Registers 1850 9200 120p -

Total 11730 55628 - -

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Optimized Round Schematic

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Normalize Layout

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Align Layout

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Align Simulation

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Exponents progress…

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Questions??