Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 9MAD MAC 52529th March, 2006Functional Block SimulationsW2Project Objective:Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

MAD MAC 525 Status:Project chosenSpecifications definedArchitectureDesignBehavioral VerilogTestbenchesVerilog : Gate Level DesignFloor plan Schematics and Analog VerificationsLayout of basic gates and small modulesSpring Break Top level layouts, extractions, LVS, simulations (in progress)To be doneFull chip layout and simulation

Block DiagramRegArray ARegArray BRegArray CMultiplierExp CalcAlignAdder/SubtractorControlLogic&SignDtrminNormalizeRoundOvf CheckerLeading 0 Anticipator10101055514352254361410155InputInputInputOutput16161616RegY15111

Design Decisions

Removed carry select top adder bits Reduced hardware at the cost of speedSpeed still well within required parametersEasier to layout

Pipelining Stages

MultiplierAlign CReg A

Reg B

ExpCalcReg C

Pipeline Reg

Pipeline Reg

AdderLd ZeroPipeline Reg

NormalizeRound

Reg YPipeline Reg

Overflow checkerPipeline Reg

Pipeline Reg

Timing Diagram

New Floorplan

Newer Floorplan

Adder Schematic

Adder Bit Slice Layout

Adder Layout

Adder Schematic Simulation

Adder Layout Simulation

Adder Schematic vs LayoutLayout is 19% slower than schematicLayout = 1150psSchematic = 962ps

Other logic in adder module will slow it down furtherExpecting about 1.6-1.8ns totalWell within 2ns target

Transistor Count Area in um2Prop. DelayPower in mW (350MHz)Multiplier3600165604.64n8.5Exponents738 3800942p1.608Align500 2990637p0.393Adder3174158701.7n5.236Leading 0364 1222551p0.857Normalize 942520434p2.291Round462 2310948p0.631OvfCheck100 500475p0.13Registers1850 9200120p-Total 1173055628--

Normalize Layout

Normalize Layout Simulation

ProblemsCadence refused to extractRC some of our modulesTurns out that Cadence discriminates against certain output pins for a reason we cannot yet determineSolution was to copy output pins from modules that work when running extractRC and rename them

Certain group members not happy with group pictureSolution is to take a new picture, iron out the wrinkles & photoshop our project manager in

Questions??

MAD MAC functionality- design goalsTop 6 bits carry selectlower 31 bits carry look ahead tree Normalize is completely on target