FAN73894 - 3-Phase Half-Bridge Gate-Drive IC

© Semiconductor Components Industries, LLC, 2015

November, 2019 − Rev. 21 Publication Order Number:

FAN73894/D

3-Phase Half-BridgeGate-Drive IC

FAN73894

DescriptionThe FAN73894 is a monolithic three−phase half−bridge gate−drive

IC designed for high−voltage, high−speed, driving MOSFETs andIGBTs operating up to +600 V.

ON Semiconductor’s high−voltage process and common−modenoise−canceling technique provide stable operation of high−sidedrivers under high−dVs/dt noise circumstances.

An advanced level−shift circuit allows high−side gate driveroperation up to VS = −9.8 V (typical) for VBS = 15 V.

The protection functions include under−voltage lockout, inter−lockfunction and inverter over−current trip with an automatic fault−clearfunction. Over−current protection that terminates all six outputs can bederived from an external current−sense resistor. An open−drain faultsignal is provided to indicate that an over−current or under−voltageshutdown has occurred. The UVLO circuits prevent malfunction whenVDD and VBS are lower than the threshold voltage.

Output drivers typically source and sink 350 mA and 650 mA,respectively; which is suitable for three−phase half−bridgeapplications in motor drive systems.

Features• Floating Channel for Bootstrap Operation to +600 V

• Typically 350 mA/650 mA Sourcing/Sinking Current−DrivingCapability for All Channels

• Extended Allowable Negative VS Swing to −9.8 V for SignalPropagation at VDD = VBS = 15 V

• Outputs Out of Phase with Input Signals

• Over−Current Shutdown Turns Off All Six Drivers

• Matched Propagation Delay for All Channels

• 3.3 V and 5.0 V Input Logic Compatible

• Adjustable Fault−Clear Timing

• Signal Interlocking of Every Phase to Prevent Cross−Conduction

• Common−Mode dVs/dt Noise−Canceling Circuit

• Built−in Advanced Input Filter

• Built−in Soft Turn−Off Function

• Built−in Under−Voltage Lockout (UVLO) Functions for All Channels

• This is a Pb−Free Device

Table 1. COMPARISION TABLE

Part FAN73893MX FAN73894MX FAN73895MX FAN73896MX

INPUT Type Inverted Inverted Non−inverted Non−inverted

VDDUV+ / VBSUV+ (Min / Typ / Max) 7.5 / 8.5 / 9.3 [V] 10.2 / 11.2 / 12 [V] 7.5 / 8.5 / 9.3 [V] 10.2 / 11.2 / 12 [V]

VDDUV− / VBSUV− (Min / Typ / Max) 7 / 8 / 8.7 [V] 9.7 / 10.7 / 11.4 [V] 7 / 8 / 8.7 [V] 9.7 / 10.7 / 11.4 [V]

Note (Replacement forFAN73892MX)

− (Replacement forFAN7389MX1)

−

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SOIC−28, 300 milsCASE 751BM−01

MARKING DIAGRAM

FAN73894 = Specific Device Code$Y = ON Semiconductor Logo&Z = Assembly Plant Code&2 = 2−Digit Date Code Format&K = 2−Digits Lot Run Traceability Code

See detailed ordering and shipping information on page 15 ofthis data sheet.

ORDERING INFORMATION

Pin 1

$Y&Z&2&KFAN73894

Applications• 3−Phase Motor Inverter Driver

• Air Conditioner, Washing Machine, Refrigerator, Dish Washer

• Industrial Inverter – Sewing Machine, Power Tool

• General−Purpose Three−Phase Inverter

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TYPICAL APPLICATION DIAGRAM

UU

UL

VU

UL

WU

WL

VMOTOR

VDD

3−PhaseBLDC

Controller

CONTROL

Udn Vdn Wdn

Uup Vup Wup

Uup

Vup

Wup

Udn

Vdn

Wdn

3−Phase Inverter

VS1

VS2

VS3

VS1

VS2

VS3

FAN

7389

4

EN

VSS NC

LIN1

VDD

VS1

HO1

VB1

HIN1

VS2

HO2

VB2

VS3

HO3

VB3

HIN2

HIN3

LIN2

LIN3

NC

LO1

FO

CS

28

27

26

25

24

23

22

21

20

19

18

17

RCIN

CRCIN

RCS

COM

LO3 LO2

16

15

NC

1

2

3

4

5

6

7

8

10

11

12

13

14

9

Figure 1. 3−Phase BLDC Motor Drive Application

UU

UL

VU

UL

WU

WL

Motor

5 V line

INTERNAL BLOCK DIAGRAM

VDD

LO1

NOISECANCELLER

UVLO

RR

SQ

DELAY

VDD_UVLO

DR

IVE

R

VS1

HO1

VB1

W Phase Driver

V Phase Driver

COM

U Phase Driver

LO2

VS2

VH

VB2

VB3

UHIN

ULIN

VDD

VHIN

VDD

WLIN

VDD

HIN1

HIN2

HIN3

LIN1

LIN2

LIN3

WHIN

INPUT NOISEFILTER

{TFLTIN = 250 ns}

SHOOT THOUGHPREVENTION

DEAD−TIME{DT = 320 ns}

ENABLE INPUTFILTER

{TFLTEN = 250 ns}

FO

Protection Circuit

COM

EN

iRCIN

VREF

LO3

VS3

HO3

COM

0.5 V

CS

ENABLE

VRCIN,TH = 3.3 VVRCIN,HYS = 0.7 V

CS_COMP

LEB

PU

LSE

GE

NE

RAT

OR

RCIN

3.3 V

ISOFT

ISOFT

ISOFT

SOFT−OFF

UVLO

VLIN

VSS−COMLEVELSHIFTER

UVLO

VSS

LEB

LATCHS

R

Q

Figure 2. Functional Block Diagram

100 k�

10 k�

10 k�

10 k�

10 k�

10 k�

10 k�

50 k�

50 k�

50 k�

50 k�

50 k�

50 k�

150 k�

DR

IVE

R


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PIN CONFIGURATION

VS

1

HO

1

VS

2

HO

2

VS

3

HO

3

RC

INEN

VS

S

CO

M

LO3

FAN73894MX

LIN

1

VD

DV

B1

HIN

1

VB

2

VB

3

HIN

2

HIN

3

LIN

2

LIN

3

LO2

LO1

28 27 26 25 24 23 22 21 20 19

1 2 3 4 5 6 7 8 9 10 11 12 13 14

18 17 16 15

NC

NC

NC

FO

CS

Figure 3. Pin Assignments

PIN DEFINITIONS

Pin Symbol Description

1 VDD Logic and low−side gate driver power supply voltage

2 HIN1 Logic Input 1 for high−side gate 1 driver



5 LIN1 Logic Input 1 for low−side gate 1 driver



8 FO Fault output with open drain (indicates over−current and low−side under−voltage)

9 CS Analog input for over−current shutdown

10 EN Logic input for shutdown functionality

11 RCIN An external RC network input used to define the fault−clear delay

12 VSS Logic ground

13 COM Low−side driver return

14 LO3 Low−side gate driver 3 output



17, 21, 25 NC No connect

18 VS3 High−side driver 3 floating supply offset voltage

19 HO3 High−side driver 3 gate driver output

20 VB3 High−side driver 3 floating supply








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ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)

Symbol Parameter Min Max Unit

VS High−Side Floating Offset Voltage VB1,2,3 − 25 VB1,2,3 + 0.3 V

VB High−Side Floating Supply Voltage −0.3 625.0 V

VDD Low−Side and Logic−Fixed supply voltage −0.3 25.0 V

VHO High−Side Floating Output Voltage VHO1,2,3 VS1,2,3 − 0.3 VB1,2,3 + 0.3 V

VLO Low−Side Floating Output Voltage VLO1,2,3 −0.3 VDD + 0.3 V

VIN Input Voltage (HINx, LINx, CS, and EN) (Note 1) VSS − 0.3 VSS + 5.5 V

VFO Fault Output Voltage (FO) −0.3 VDD + 0.3 V

dVS/dt Allowable Offset Voltage Slew Rate − ±50 V/ns

PD Power Dissipation (Note 2, 3) − 1.4 W

�JA Thermal Resistance − 70 °C/W

TJ Junction Temperature − 150 °C

TSTG Storage Temperature −55 150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. All input voltage (HINx, LINx, CS, and EN) are referenced to VSS and do not exceed maximum voltage rating.2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material). Refer to the following standards:

JESD51−2: Integral circuit’s thermal test method environmental conditions, natural convection;JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages.

3. Do not exceed maximum power dissipation (PD) under any circumstances.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VB1,2,3 High−Side Floating Supply Voltage VS1,2,3 + 10 VS1,2,3 + 20 V

VS1,2,3 High−Side Floating Supply Offset Voltage 6 − VDD 600 V

VDD Low−Side and Logic Fixed Supply Voltage 12 20 V

VHO1,2,3 High−Side Output Voltage VS1,2,3 VB1,2,3 V

VLO1,2,3 Low−Side Output Voltage COM VDD V

VFO Fault Output Voltage (FO) VSS VDD V

VCS Current−Sense Pin Input Voltage VSS VSS + 5 V

VIN Logic Input Voltage (HIN1,2,3 and LIN1,2,3) VSS VSS + 5 V

VSS Logic Ground −5 5 V

TA Ambient Temperature −40 +125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.


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ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IINparameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COMand are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to VSS. The VBSUVparameters are referenced to VS1,2,3.)

Symbol Parameter Condition Min Typ Max Unit

LOW−SIDE POWER SUPPLY SECTION

IQDD Quiescent VDD Supply Current VLIN1,2,3 = 5 V or open, EN = 0 V − 250 400 �A

IPDD Operating VDD Supply Current fLIN1,2,3 = 20 kHz, rms Value − 550 750 �A

VDDUV+ VDD Supply Under−Voltage Positive−Going Threshold VDD = Sweep 9.7 11.0 12.0 V

VDDUV− VDD Supply Under−Voltage Negative−Going Threshold VDD = Sweep 9.2 10.5 11.4 V

VDDHYS VDD Supply Under−Voltage Lockout Hysteresis VDD = Sweep − 0.5 − V

BOOTSTRAPPED POWER SUPPLY SECTION

VBSUV+ VBS Supply Under−Voltage Positive−Going Threshold VBS1,2,3 = Sweep 9.7 11.0 12.0 V

VBSUV− VBS Supply Under−Voltage Negative−Going Threshold VBS1,2,3 = Sweep 9.2 10.5 11.4 V

VBSHYS VBS Supply Under−Voltage Lockout Hysteresis VBS1,2,3 = Sweep − 0.5 − V

ILK Offset Supply Leakage Current VB1,2,3 = VS1,2,3 = 600 V − − 10 �A

IQBS Quiescent VBS Supply Current VHIN1,2,3 = 0 V or 5 V, EN = 0 V 10 50 80 �A

IPBS Operating VBS Supply Current fHIN1,2,3 = 20 kHz, rms Value 200 320 480 �A

GATE DRIVER OUTPUT SECTION

VOH High−Level Output voltage, VBIAS − VO IO = 0 mA (No Load) − − 100 mV

VOL Low−Level Output voltage, VO IO = 0 mA (No Load) − − 100 mV

IO+ Output HIGH Short−Circuit Pulse Current (Note 4) VO = 0 V, VIN = 0 V with PW ≤ 10 �s 250 350 − mA

IO− Output LOW Short−Circuit Pulsed Current (Note 4) VO = 15 V, VIN = 5 V with PW ≤10 �s

500 650 − mA

VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO

− −9.8 −9.0 V

LOGIC INPUT SECTION

VIH Logic “0” Input Voltage HIN1,2,3, LIN1,2,3 2.5 − − V

VIL Logic “1” Input Voltage HIN1,2,3, LIN1,2,3 − − 0.8 V

IIN+ Logic Input Bias Current (HO = LO = HIGH) VIN = 0 V 77 100 143 �A

IIN− Logic Input Bias Current (HO = LO = LOW) VIN = 5 V − 8.5 25.0 �A

RIN Logic Input Pull−Up Resistance 35 50 65 k�

ENABLE CONTROL SECTION (EN)

VEN+ Enable Positive−Going Threshold Voltage 2.5 − − V

VEN− Enable Negative−Going Threshold Voltage − − 0.8 V

IEN+ Logic Enable “1” Input Bias Current VEN = 5 V (Pull−Down = 150 k�) 15 33 50 �A

IEN− Logic Enable “0” Input Bias Current VEN = 0 V − − 2 �A

REN Logic Input Pull−Down Resistance 100 150 333 k�

OVER−CURRENT PROTECTION SECTION

VCSTH+ Over−Current Detect Positive Threshold 450 500 550 mV

VCSTH− Over−Current Detect Negative Threshold − 440 − mV

VCSHYS Over−Current Detect Hysteresis − 60 − mV

ICSIN Short−Circuit Input Current VCSIN = 1 V 5 10 15 �A

ISOFT Soft Turn−Off Sink Current 25 40 55 mA


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ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IINparameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COMand are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to VSS. The VBSUVparameters are referenced to VS1,2,3.) (continued)

Symbol UnitMaxTypMinConditionParameter

FAULT OUTPUT SECTION

VRCINTH+ RCIN Positive−Going Threshold Voltage 2.7 3.3 3.9 V

VRCINTH− RCIN Negative−Going Threshold Voltage (Note 4) − 2.6 − V

VRCINHYS RCIN Hysteresis Voltage (Note 4) − 0.7 − V

IRCIN RCIN Internal Current Source CRCIN = 2 nF 3 5 7 �A

VFOL Fault Output Low Level Voltage VCS = 1 V, IFO = 1.5 mA − 0.2 0.5 V

RDSRCIN RCIN On Resistance IRCIN = 1.5 mA 50 75 100 �

RDSFO Fault Output On Resistance IFO = 1.5 mA 90 130 170 �

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.4. These parameters are guaranteed by design.

DYNAMIC ELECTRICAL CHARACTERISTICS (TA = 25°C, VBIAS (VDD, VBS1,2,3) = 15.0 V, VS1,2,3 = COM = VSS, CRCIN = 2 nF,and CLoad = 1000 pF unless otherwise specified.)

Symbol Parameter Condition Min Typ Max Unit

tON Turn−On Propagation Delay VLIN1,2,3 = VHIN1,2,3 = 0 V, VS1,2,3 = 0 V 350 500 650 ns

tOFF Turn−Off Propagation Delay VLIN1,2,3 = VHIN1,2,3 = 5 V, VS1,2,3 = 0 V 350 500 650 ns

tR Turn−On Rise Time VLIN1,2,3 = VHIN1,2,3 = 0 V 20 50 100 ns

tF Turn−Off Fall Time VLIN1,2,3 = VHIN1,2,3 = 5 V 10 30 80 ns

tEN Enable LOW to Output Shutdown Delay 400 500 600 ns

tCSBLT CS Pin Leading−Edge Blanking Time 400 650 850 ns

tCSFO Time from CS Triggering to FO From VCSC = 1 V to FO Turn−Off − 850 1300 ns

tCSOFF Time from CS Triggering to Low−Side GateOutputs Turn−Off

From VCSC = 1 V to Starting Gate Turn−Off − 850 1300 ns

tFLTIN Input Filtering Time (Note 5) (HINx, LINx, EN) 170 250 330 ns

tFLTCLR Fault−Clear Time CRCIN = 2 nF − 1.30 2.35 ms

DT Dead Time 230 320 400 ns

MDT Dead−Time Matching (All Six Channels) − − 50 ns

MT Delay Matching (All Six Channels) − − 50 ns

PM Output Pulse−Width Matching (Note 6) PWIN > 1 �s − 50 100 ns

5. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded.6. PM is defined as PWIN − PWOUT.


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TYPICAL CHARACTERISTICS

−40 −20 0 20 40 60 80 100 120350

400

450

500

550

600

650

High−Side Low−Side

−40 −20 0 20 40 60 80 100 120350

400

450

500

550

600

650

−40 −20 0 20 40 60 80 100 1200

102030

4050

60708090

100

−40 −20 0 20 40 60 80 100 1200

102030

4050

60708090

100

−40 −20 0 20 40 60 80 100 120400

450

500

550

600

−40 −20 0 20 40 60 80 100 1201.0

1.2

1.4

1.6

1.8

2.0

Temperature [°C] Temperature [°C]



t ON

[ns]

t OF

F [n

s]

t R [n

s]

t F [n

s]

t EN

[ns]

t FLT

CLR

[ms]




Figure 4. Turn−On Propagation Delay vs. Temperature

Figure 5. Turn−Off Propagation Delay vs. Temperature

Figure 6. Turn−On Rise Time vs. Temperature Figure 7. Turn−Off Fall Time vs. Temperature

Figure 8. Enable LOW to Output Shutdown Delay vs. Temperature

Figure 9. Fault−Clear Time vs. Temperature


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TYPICAL CHARACTERISTICS (continued)

−40 −20 0 20 40 60 80 100 120200

250

300

350

400

DT1 DT2

−40 −20 0 20 40 60 80 100 120−50

−25

0

25

50

−40 −20 0 20 40 60 80 100 120−50

−40−30

−20−10

01020304050

MTONMTOFF

−40 −20 0 20 40 60 80 100 120−13

−12

−11

−10

−9

−8

−7

−40 −20 0 20 40 60 80 100 12050

100

150

200

250

300

350

400

−40 −20 0 20 40 60 80 100 1200

20

40

60

80

100




DT

[ns]

MD

T [n

s]

Del

ay M

atch

ing

[ns]

VS [V

]

I QD

D [�

A]

I QB

S [�

A]

Figure 10. Dead Time vs. Temperature Figure 11. Dead−Time Matching vs. Temperature

Figure 12. Delay Matching vs. Temperature Figure 13. Allowable Negative VS Voltage vs. Temperature

Figure 14. Quiescent VDD Supply Current vs. Temperature

Figure 15. Quiescent VBS Supply Current vs. Temperature


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VB

SU

V−

[V]

VB

SU

V+ [V

]

VD

DU

V−

[V]

−40 −20 0 20 40 60 80 100 120100

200

300

400

500

600

700

−40 −20 0 20 40 60 80 100 120100

200

300

400

500

600

700

−40 −20 0 20 40 60 80 100 12010.0

10.5

11.0

11.5

12.0

−40 −20 0 20 40 60 80 100 1209.5

10.0

10.5

11.0

11.5

−40 −20 0 20 40 60 80 100 12010.0

10.5

11.0

11.5

12.0

−40 −20 0 20 40 60 80 100 1209.5

10.0

10.5

11.0

11.5




I PD

D [�

A]

I PB

S [�

A]

VD

DU

V+ [V

]

Figure 16. Operating VDD Supply Current vs. Temperature

Figure 17. Operating VBS Supply Current vs. Temperature

Figure 18. VDD UVLO+ vs. Temperature Figure 19. VDD UVLO− vs. Temperature

Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO− vs. Temperature


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−40 −20 0 20 40 60 80 100 1200

24

68

10

1214161820

−40 −20 0 20 40 60 80 100 1200

20

40

60

80

100


−40 −20 0 20 40 60 80 100 1200

20

40

60

80

100


−40 −20 0 20 40 60 80 100 1201.0

1.5

2.0

2.5

3.0

−40 −20 0 20 40 60 80 100 1200.5

1.0

1.5

2.0

2.5

3.0

−40 −20 0 20 40 60 80 100 12060

80

100

120

140

160

I IN−

[�A

]

I IN+ [�

A]

VIL

[V]




VO

H [m

V]

VO

L [m

V]

VIH

[V]

Figure 22. High−Level Output Voltage vs. Temperature

Figure 23. Low−Level Output Voltage vs. Temperature

Figure 24. Logic HIGH Input Voltage vs. Temperature

Figure 25. Logic LOW Input Voltage vs. Temperature

Figure 26. Logic Input HIGH Bias Current vs. Temperature

Figure 27. Logic Input LOW Bias Currentvs. Temperature


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I IQB

S [�

A]

RE

N [k

�]

100

200

300

400

500

600

700

10 12 14 16 18 200

20

40

60

80

100

10 12 14 16 18 20100

120

140

160

180

200

10 12 14 16 18 2050

100

150

200

250

300

350

400

10 12 14 16 18 200

20

40

60

80

100

100

200

300

400

500

600

700

Supply Voltage [V] Supply Voltage [V]



I PB

S [�

A]

I PD

D [�

A]

RIN

[k�

]I IQ

DD

[�A

]

Figure 28. Input Pull−Down Resistance vs. Supply Voltage

Figure 29. Enable Pin Pull−Down Resistance vs. Supply Voltage

Figure 30. Quiescent VDD Supply Current vs. Supply Voltage

Figure 31. Quiescent VBS Supply Current vs. Supply Voltage

Figure 32. Operating VDD Supply Current vs. Supply Voltage

Figure 33. Operating VBS Supply Current vs. Supply Voltage

12 14 16 18 20 12 14 16 18 20


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SWITCHING TIME DEFINITIONS

Figure 34. Switching Time Waveform Definitions

Figure 35. Input / Output Timing Diagram

Figure 36. Detailed View of B and C Intervals During Over−Current Protection

50%

90%

50%

tON

10% 10%

90%

HOx(LOx)

HINx

(LINx)

tR tOFF t F

A B C D F

HINx

LINx

EN

CS

VRCIN

HOx

LOx

Shoot−ThroughPrevent Over−Current

Protection

Shutdown Shutdown

FO

E

Shoot−ThroughPrevent

HOx keep high−state this event

t CSFO

50% 50%

90%

VRCIN,TH

VCS,TH+ VCS,TH+

t FLTCLR

t CSOFF

Interval B Interval C

CS

VRCIN

AnyOutput

FO

LOx keep high−state this event


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APPLICATIONS INFORMATION

Dead TimeDead time is automatically inserted whenever the dead

time of the external two input signals (between HINx andLINx signals) is shorter than internal fixed dead times (DT1and DT2). Otherwise, external dead times larger thaninternal dead times are not modified by the gate driver andinternal dead−time waveform definition is shown inFigure 37.

Figure 37. Internal Dead−Time Definitions

HOx

HINx

50%

50% 50%

50%

LINx

LOx

DT1 DT2

50% 50%

Protection Function

Fault Out (FO) and Under−Voltage LockoutThe high− and low−side drivers include under−voltage

lockout (UVLO) protection circuitry that monitors thesupply voltage for VDD and VBS independently. It can bedesigned to prevent malfunction when VDD and VBS arelower than the specified threshold voltage. The UVLOhysteresis prevents chattering during power−supplytransitions. Moreover, the fault signal (power supply voltageFO) goes to LOW state to operate reliably during power−onevents when the power supply (VDD) is below theunder−voltage lockout high threshold voltage for the circuit(during t1~t2). The UVLO circuit is not otherwise activated;shown Figure 38. If VDD is lower than 3.5 V, the fault signalcannot be driven to LOW state because VDD is not enoughto drive internal circuit.

Figure 38. Waveforms for Under−Voltage Lockout

VRCINTH+

UVLO+VDD

LO

FO

UVLO−

t1 t3t2t0 t4

VDD < 3.5 V

Lower Voltage

Lower Voltage

RCIN

Shoot−Through ProtectionThe shoot−through protection circuitry prevents both

high− and low−side switches from conducting at the sametime, as shown Figure 39.

Figure 39. Shoot−Through Protection

After DT

LOx

HOx

After DT


HINx

LINx

Example A

Example B

LOx

HOx


HINx

LINx

An interlock function is a device used to prevent bothhigh− and low−side switches from conducting at the sametime as shown Figure 40. In most applications an interlockis used to help prevent a device from harming its operator ordamaging itself by when two input signals of a same leg areactivated simultaneously, only one output is activated.

Figure 40. Interlock Function

HINx

LINx

HOx

LOx

S1 S2 S3 S4 S5

→S1 : High−side first First input output mode→S2 : Low−side noise No LOx output mode→S3 : High−side noise No HOx output mode→S4 : Low−side first First input output mode→S5 : In−phase mode No HOx output


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Enable InputWhen the EN pin is in HIGH state, the gate driver operates

normally. When a condition occurs that should shut downthe gate driver, the EN pin should be LOW. The enablecircuitry has an input filter; the minimum input duration isspecified by tFLTIN (typically 250 ns).

Figure 41. Output Enable Timing Waveform

90%

50%

t EN

HOxLOx

EN

Fault−Out (FO) and Over−Current ProtectionFAN73894 provides an integrated fault output (FO) and

an adjustable fault−clear timer (tFLTCLR). There are twosituations that cause the gate driver to report a fault via theFO pin. The first is an under−voltage condition of low−sidegate driver supply voltage (VDD) and the second is when thecurrent−sense pin (CS) recognizes a fault. If a fault conditionoccurs, the FO pin is internally pulled to COM, thefault−clear timer is activated, and all outputs (HO1, 2, 3 andLO1, 2, 3) of the gate driver are turned off. The fault outputstays LOW until the fault condition has been removed andthe fault−clear timer expires. Once the fault−clear timerexpires, the voltage on the FO pin returns to pull−up voltage.

The fault−clear time (tFLTCLR) is determined by aninternal current source (IRCIN = 5 �A) and an external CRCINat the RCIN pin, as shown as:

tFLTCLR �

CRCIN � VRCIN,TH

IRCIN

[s](eq. 1)

The RDSRCIN of the MOSFET is a characteristic dischargecurve with respect to the external capacitor CRCIN. The timeconstant is defined by the external capacitor CRCIN and theRDSRCIN of the MOSFET.

The output of current−sense comparator (CS_COMP)passes a noise filter, which inhibits an over−currentshutdown caused by parasitic voltage spikes of VCS.

This corresponds to a voltage level at the comparator ofVCSTH+ − VCSHYS = 500 mV − 60 mV = 440 mV, whereVCSHYS = 60 mV is the hysteresis of the current comparator(CS_COMP), as shown in Figure 42.

Figure 42. Over−Current Protection

Protection Circuit

iRCIN

VREF

0.5 V

CS

Fault

VRCIN,TH = 3.3 VVRCIN,HYS = 0.7 V

CS_COMP

LEBRCIN

3.3 V

ISOFT

LatchS

R

Q

VDD_UVLO

To low side outputVDD

RFO

CRCIN

EN

InputStage ON

To COM

LEB

VSS

SOFT−OFF

FO

100 k�

150 k�

Figure 43 shows the waveform definitions of RCIN, FO,and the low−side driver; which uses a soft turn−off methodwhen an under−voltage condition of the low−side gate driversupply voltage (VDD) or the current−sense pin (CS)recognizes a fault. If a fault condition occurs, the FO Pin isinternally pulled to COM and all outputs (HO1,2,3 andLO1,2,3) of the gate driver are turned off. Low−side outputsdecline linearly by the internal sink current source(ISOFT = 40 mA) for soft turn−off, as shown in Figure 43.

Figure 43. RCIN and Fault−Clear Waveform Definition

90%

tCSBLT

tCSFO

tCSOFF

VCSC

LO

FOtFLTCLR

LINx

VRCINTH+VRCIN

Leading EdgeBranking Time

500 mV440 mV

Noise Filter

Input Noise FilterFigure 44 shows the input noise filter method, which has

symmetry duration between the input signal (tINPUT) and theoutput signal (tOUTPUT) and helps to reject noise spikes andshort pulses. This input filter is applied to the HINx, LINx,and EN inputs. The upper pair of waveforms (Example A)shows input signal duration (tINPUT) much longer than inputfilter time (tFLTIN); it is approximately the same durationbetween the input signal time (tINPUT) and the output signaltime (tOUTPUT). The lower pair of waveforms (Example B)shows an input signal time (tINPUT) slightly longer thaninput filter time (tFLTIN); it is approximately the sameduration between input signal time (tINPUT) and the outputsignal time (tOUTPUT).


FAN73894

www.onsemi.com15

Figure 44. Input Noise Filter Definition

OUTx

Exa

mpl

e B

Exa

mpl

e A

t FLTININx

OUTx

t FLTININx

t INPUT

t OUTPUT

t INPUT

t OUTPUT Output duration issame as input duration

Short−Pulsed Input Noise Rejection MethodThe input filter circuitry provides protection against

short−pulsed input signals (HINx, LINx and EN) on theinput signal lines by applied noise signal.

If the input signal duration is less than input filter time(tFLTIN), the output does not change states.

Example A and B of the Figure 45 show the input andoutput waveforms with short−pulsed noise spikes with aduration less than input filter time; the output does notchange states.

Figure 45. Noise Rejecting Input Filter Definition

OUTx

OUTx

t FLTIN t FLTIN t FLTIN

t FLTIN t FLTIN t FLTIN

(LOW)

(HIGH)

INx

INx

Exa

mpl

e B

Exa

mpl

e A

Figure 46 shows the characteristics of the input filterswhile receiving narrow ON and OFF pulses. If input signalpulse duration, PWIN, is less than input filter time, tFLTIN;the output pulse, PWOUT, is zero. The input signal is rejectedby input filter. Once the input signal pulse duration, PWIN,exceeds input filter time, tFLTIN, the output pulse durations,PWOUT, matches the input pulse durations, PWIN.FAN73894 input filter time, tFLTIN, is about 250 ns for thehigh− and low−side outputs.

Figure 46. Input Filter Characteristic of Narrow ON

200

100

300

500

400

600

700

800

900

1000

0

Out

put P

ulse

Wid

th [n

s]

200100 300 500400

Input Pulse Output Pulse

700600 800 1000900

Input Pulse Width [ns]

ORDERING INFORMATION

Part Number Package Operating Temperature Shipping†

FAN73894MX (Note 7) 28−Lead, Small OutlineIntegrated Circuit, (SOIC)

(Pb−Free)

−40 to +125°C 1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

7. These devices passed wave−soldering test by JESD22A−111.


SOIC−28, 300 milsCASE 751BM−01

ISSUE ODATE 19 DEC 2008

L

h h

E

PIN #1

IDENTIFICATION

D

A1 c�1

b e

E1

AA2

TOP VIEW

SIDE VIEW END VIEW

�1

Notes:(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-013.

�

SYMBOL MIN NOM MAX

θ

A

A1

b

c

D

E

E1

e

h

0º 8º

0.10

0.31

0.20

0.25

17.78

10.11

7.34

1.27 BSC

2.65

0.30

0.51

0.33

0.75

18.03

10.51

7.60

L 0.40 1.27

2.35

A2 2.05 2.55

θ1 5º 15º

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

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DESCRIPTION:

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FAN73894 - 3-Phase Half-Bridge Gate-Drive IC

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