opinion:Critkiueo the F8Mkorcsr

Dave CaulkinsCabledata Associates, Inc.

Introduction

The Fairchild F8 is a control microprocessor whose archi-tecture is considerably different from most machines inthe same price and performance class. Good computerarchitecture is consistent, symmetrical, and coherent; theprogrammer is provided with the maximum amount ofinformation possible after each operation and his freedomof action is limited as little as possible. A machine withthese qualities behaves in the way one expects it to behave;it is free of special cases and peculiar quirks. The F8 fallsconsiderably short of meeting these goals. It predatesmost equivalent micros; its designers seem to have hadlittle contact with others doing similar things. This back-ground has resulted in a machine combining brilliantdesign concepts with ugly flaws.Two of the brilliant concepts deserve special mention:(1) The F8 CPU (3850) has allocated a scarce resource,

package pins, in a novel way. Instead of a conventionaladdress bus, there are two 8-bit I/O ports. A bidirectional8-bit data bus and eight control lines provide all requiredcommunication between the 3850 and associated devices.Program and data counters (PC and DC respectively) areresident outside the 3850.

(2) The 3850 has 64 bytes of resident scratchpad memory.The power of these features is indicated by the fact

that similar controller-type machines of much more recentvintage (the Intel 8048 comes to mind) provide verysimilar capabilities.The F8 flaws are covered in detail below. On balance,

I think the advantages outweigh the flaws, but they turnthe F8 from what might have been a really nice machineinto one which is cost effective but exasperating to use.

F8 architecture

F8 CPU, memory, and I/O ports are partitioned in aunique way; the CPU (3850) package contains the ALU,64 bytes of scratchpad memory, and two 8-bit I/O ports.It contains no program memory; this is contained in oneor more program storage units-3851 or 3856. Each ofthese contains 1K bytes (2K in the 3856) of mask ROM,two 8-bit I/O ports, interrupt circuitry, and an intervaltimer. Access to this ROM for instructions is via a pro-gram counter register. ROM access for data is via thedata counter register. These are both 16-bit registers and(perhaps the most radical feature of all) they are external

August 1977

to the CPU. This structure eliminates the need for a con-ventional memory address bus. The package pins thusfreed are available for I/O functions. The bad news is thatfor systems with more than two LSI packages, there aremultiple program counter and data counter registers.Except for one case discussed below, great care has beentaken to ensure that multiple address registers of thesame kind always contain the same value.The structure of the F8 CPU is shown in Figure 1. There

are six significant registers: the accumulator (8-bit), theindirect scratchpad address register (ISAR; 6-bit), thestatus register W (5-bit), the data counter (16-bit), andprogram counters PCO and PC1 (16-bit). The first three ofthese (A, W, and ISAR) and the 64-byte scratchpad areresident in the 3850 CPU. The data counters and programcounters are resident in memory devices external to theCPU: the program storage unit (3851 or 3856 PSU; 1K or2K bytes of ROM) or the static or dynamic memory inter-faces (3853 SMI or 3852 DMI; they permit attachment ofROMs, PROMs, or conventional static or dynamic RAMs).Table 1 gives a brief description of each of the devices inthe F8 family.A more detailed account of F8 architecture is available

from Osborne' and Fairchild.23

Hardware problems. Most of the hardware problemscenter around the 3852 and 3853 memory interface devices.Both 3852 and 3853 have an input control signal REGDR;there is a 3851 output signal (DBDR', Pin 11) which islogically correct for driving REGDR; unfortunately,REGDR is specified as requiring a driver able to sink14 mA-which far exceeds the drive capability of DBDR'.This means an additional SSI package. The 3852 has asecond signal of this type (CPU SLOT, Pin 5) that re-quires a driver able to sink 16 mA. This is beyond thecapability of any 3850 output. The 3852 and 3853 alsohave no provision for interfacing the RAMs they supportto the F8 internal 8-bit data bus even though these RAMsmust be connected to it. The problem is complicated bythe fact that this internal bus requires a logic "1," levelof 3.9 V; standard RAMs and ROMs are designed to out-Rut 2.4 V. Thus, CMOS or other special drivers must beplaced between the RAMs and the bus; these must betri-state, and the tri-state control logic must also be dealtwith external to the 3852 and 3853. Any F8 system usingROMs, PROMs, or RAMs external to the 3850 and 3851ends up with many more packages than one would expectin a system supposedly designed for a minimal packagecount.

83

7 ACCUMULATORCPU

GENERALREGISTERS

(SCRATCHPAD)

J

HuHL

KuKL

ou0Q

:t*Most FB literature refers to this register as the StackPointer; since have been unable to find the stack beingpointed to, prefer the nomenclature shown here.

63

Figure 1. F8 structure.

Table 1. The F8 family of devices.

NUMBER NAME DESCRIPTION, FUNCTIONS NUMBER NAME DESCRIPTION, FUNCTIONS

3850 Central Processing ALU, 64 byte SP, two 8-bit I/O ports, 3852 Dynamic Memory Interface for standard dynamic RAMs.Unit bus control "head end". Interface Bus interface, 16-bit address bus,

refresh logic, some RAM support logic.3851 Program Storage 1K byte mask ROM, two 8-bit I/O ports,

Unit interval timer, external interrupt, 3853 Static Memory Interface for standard static RAMs. Samebus interface. IInterface as 3852 except refresh logic replaced by

3856 Program Storage 2K byte mask ROM, improved timer; an interval timer and and externalUnit otherwise same as 3851. interrupt.

3861 Program Storage Same as 3851, but with no ROM. Useful 3870 Single Chip F8 ALU, 64 byte SP, four 8-bit I/O ports,Unit in systems with external RAM, ROM, or interval timer, external interrupt, 2K byte

PROM. mask ROM.84 COMPUT_

0 LRr,ALRA, r

0

REGISTERADDRESSPOINTER

0

1

2

3

4

5

6

7

8

9

A

B

CD

E

F

10

3F

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Table 2. F8 instructions.

ADC ADD DATA COUNTER WITH ACCUMULATORAl ADD I MMEDIATE WITH ACCUM ULATORAM ADD BINARY ACCUM U LATOR WITH MEMORYAMD ADD DECIMAL ACCUMULATOR WITH MEMORYAS* ADD BINARY ACCUMULATOR WITH SCRATCHPAD REGISTERASD* ADD DECIMAL ACCUMULATOR WITH SCRATCHPAD REGISTER

BC BRANCH ON CARRYBF BRANCH ON FALSE CONDITIONBM BRANCH IF NEGATIVEBNC BRANCH IF NO CARRYBNO BRANCH IF NO OVERFLOWBNZ BRANCH IF NO ZEROBP BRANCH IF POSITIVEBR ABOLUTE BRANCHBR7 BRANCH IF ISAR IS NOT 7BT BRANCH ON TRUE CONDITIONBZ BRANCH ON ZERO CONDITION

CI COMPARE IMMEDIATECLR CLEAR ACCUMULATORCM COMPARE WITH MEMORYCOM COMPLEMENT ACCUMULATOR

DCI LOAD DATA COUNTER IMMEDIATEDl DISABLE INTERRUPTDS* DECREMENT SCRATCHPAD REGISTER

El ENABLE INTERRUPT

INC INCREMENT ACCUMULATORIN INPUTINS INPUT SHORT

JMP JUMP

LI LOAD ACCUMULATOR IMMEDIATELIS LOAD ACCUMULATOR SHORTLISL LOAD ISAR (LOWER 3 BITS)LISU LOAD ISAR (UPPER 3 BITS)LM LOAD MEMORYLNK LINK CARRY INTO ACCUMULATORLR A,KU LOAD A FROM K (UPPER HALF)LR A, KL LOAD A FROM K (LOWER HALF)LR A,QU LOAD A FROM 0 (UPPER HALF)LR A,QL LOAD A FROM 0 (LOWER HALF)

LR A,r*LR KU, ALR KL, ALR QU,ALR QL,ALRr*,ALR IS,ALR A, ISLR W,JLR J,WLR DC,HLR DC,QLR H,DCLR 0, DCLR, P,KLR K,PLR PO,Q

NINMNOPNS*

01OMOUTOUTS

LOAD A FROM SCRATCHPADLOAD K (UPPER HALF) FROM ALOAD K (LOWER HALF) FROM ALOAD 0 (UPPER HALF) FROM ALOAD 0 (LOWER HALF) FROM ALOAD SCRATCHPAD FROM ALOAD ISAR FROM ALOAD A FROM ISARLOAD W FROM JLOAD J FROM WLOAD DC FROM H**LOAD DC FROM Q**LOAD H FROM DC**LOAD 0 FROM DC**LOAD AUXILIARY PROGRAM COUNTER (PC1) FROM K**LOAD K FROM AUXILIARY PROGRAM COUNTER (PC1 )**LOAD PROGRAM COUNTER (PCO) FROM Q**

LOGICAL AND ACCUMULATOR IMMEDIATELOGICAL AND MEMORY ACCUMULATORNO OPERATIONLOGICAL AND SCRATCHPAD AND ACCUMULATOR

LOGICAL OR IMMEDIATELOGICAL OR MEMORY WITH ACCUMULATOROUTPUTOUTPUT SHORT

Pi LOAD PC1 FROM PCO, SET PCO TO NEW LOCATION**PK LOAD PC1 FROM PCO, SET PCO FROM SCRATCHPAD

REGISTER K**POP LOAD PCO FROM PC1 **

SL SHIFT LEFTSR SHIFT RIGHTST STORE MEMORY

XDCXiXMXS*

EXCHANGE DATA COUNTERSEXCLUSIVE OR IMMEDIATEEXCLUSIVE OR ACCUMULATOR WITH MEMORYEXCLUSIVE OR ACCUMULATOR WITH SCRATCHPAD

*Uses a scratchpad cell (either pointed to by ISAR or directly accessed);ISAR may be incremented, decremented, or left unchanged as a resultof instruction execution.

**A 16-bit operation.

A second group of problems involves the interrupts inthe 3851 and 3861 PSU's. There are two kinds:

(a) external, initiated by a high-to-low transition onEXT INT', Pin 5; and(b) timer, initiated when the internal timer reaches avalue of 0.

Although each type of interrupt has its own unique inter-rupt vector, they are mutually exclusive-an unnecessarylimitation. The timer is mechanized with a feedback shiftregister; its count sequence is non-monotonic and essen-tially random. The timer can be loaded by the programbut not read; once enabled, its sole function is to producean interrupt on the count of 0. The timer runs continuouslyunless loaded with the explicit "stop" value of 255. Aseparate operation can disable the timer interrupt; if thetimer is not reloaded before enabling, the time to the nexttimer interrupt is essentially undefined. The drawbacksof this timer mechanization have been recognized; theinterval timers in Mostek's single-chip 3870 CPU andFairchild's new 3856 program storage unit are mechanizedas binary counters and can be read by the program. Itwould be very nice if these improvements were retrofittedinto the 3851 and 3861.Mostek's 3861 program storage units have the same fixed

interrupt vector assignments as the Fairchild 3861s.

Mostek's stand-alone debug software (DDT-1) is locatedin the first 1K of memory space (0000 to 03FF Hex). Fair-child's stand-alone debug software (FAIR-BUG) is locatedhalfway through the address space (8000 to 83FF Hex).Alas, all but one of the five available 3861 interrupt vectorsets point to random locations in Mostek's DDT-1. The one3861 type with a usable interrupt vector set has I/O portassignments that conflict with those in the 3851 containingDDT-1. Thus, 3861's cannot be used in a system withDDT-1 since I/O port assignments, DDT-1, and the vectorsare in mask ROMs. Mostek has a functional (if hardlyaesthetic) four-SSI package kludge called "The PIO VectorSwitch Trick" which can be used to shift the interruptvectors out of the area occupied by DDT-1. A change inthe 3861 ROM mask to shift all the vectors outside DDT-1would be highly desirable. Fairchild 3861's and FAIR-BUGdo not have this problem. Unfortunately DDT-1 has break-points and FAIR-BUG does not.

Software. The F8 has 74 instructions (see Table 2). Thisset includes 21 different load instructions allowing variousregister-to-register and register-to-scratchpad operations,some more useful than others.Perhaps the most powerful feature of the instruction set

is the series of implied addressing operations using the

August 1977 85

indirect scratchpad address register (ISAR) to accessthe 64-byte scratchpad internal to the 3850 CPU chip. Theaccumulator contents may be either fetched from or storedinto the scratchpad cell designated by ISAR; as part ofthe same instruction, ISAR may be incremented or decre-mented. Logical functions (AND or EXOR) of the scratch-pad cell and the accumulator may be formed, and thecontents Qf the cell may be decremented without disturb-ing the accumulator contents.Another particularly useful instruction is LIS (load

accumulator short). This places a 4-bit constant from theinstruction word in the four least significant bits of theaccumulator. Together with the 4-bit shift instructions(SL 4 and SR 4) this instruction allows convenient mani-pulationi of 4-bit quantities. LIS occupies 1 byte of programspace and executes in a single machine cycle.There are also features which are limiting, dangerous,

or counter-intuitive. I list them below, most disagreeablefirst:

(1) Two instructions allow access to the entire 65Kaddress space without prior operations: JMP and PI. Bothdestroy the contents of the accumulator, preventing whatwould otherwise be a useful way of passing a parameter.

(2) All conditional branches operate on the status register(W) bits; 0 (overflow), Z (zero), C (carry) and S (sign). Thesebits are often not set when they could be. Two particularlypainful examples:

(a) Status bits are not changed by non-I/O load accumu-lator operations. This means that signalling betweenprogram modules via flag bits in scratchpad or RAMrequires cumbersome special sequences (such as CLR,XS S) to set the status bits.(b) The shift left instructions (SL) do not set the carrystatus bit (C) when a "1," is shifted out of bit position 7of the accumulator. This is counter-intuitive and alsoprevents a useful mechanization of the rotate functionin conjunction with the LNK instruction.

(3) The use of the scratchpad is artifically constrainedto a particular style of usage; division into eight cell groups.The ISAR cannot be loaded by a single instruction; itsupper and lower halves must be loaded by two separateinstructions, LISU and LISL. One of the powerful featuresof the machine-automatic incrementing and decrementingof ISAR-is limited to the lower three bits. Thus, ISARincrements 25, 26, 27, 20, 21 ... One branch instruction(BR7) is dedicated to this scheme; it causes a branch if thelower half of ISAR equals 7. The rest of the system is dealtwith in hexadecimal notation; this peculiarity of ISARaddressing requires octal. In my view it would have beenmuch better to allow the ISAR to be incremented acrossits entire range of 0 to 63. The BR7 instruction couldhave been retained, allowing but not requiring the parti-tioning of scratchpad into eight cell groups.

(4) Part of scratchpad (cells 9-15) is used by a series ofload instructions to save or restore the W, PC, and DCregisters. The scheme strikes me as arbitrary and cumber-some; it does not lend itself well to creation of stacks forsaving and restoring context. I believe it would have beenpreferable to use the existing implied addressing viaISAR; the W, PC, and DC registers could then have beenstored or fetched anywhere in scratchpad.

(5) The contents of any scratchpad cell pointed to byISAR can be decremented without affecting the contentsof the accumulator. There is no corresponding incrementinstruction for scratchpad cells. Conversely, the contentsof the accumulator can be incremented by a single instruc-tion; there is no corresponding decrement instruction. Thisasymmetry makes various kinds of indexing operationsmore difficult than they need be.

(6) The instruction set lacks a number of features whichmight have been valuable. The most sifnificant of these isa HALT or PAUSE instruction. This can be simulated byusing a BR instruction that branches to itself, but this isat best a cumbersome substitute for something whichshould have been in the instruction set. Two instructionspermit access to RAM memory external to the F8 CPU.They are load memeory (LM) which loads the contents ofthe memory cell indicated by the data counter into theaccumulator, and store memory (ST), which does the reverse-stores the contents of the accumulator in the memorycell addressed by the data counter. In both cases, the datacounter is incremented; there are no equivalent provisionsfor decrementing the data counter. A pair of instructionscorresponding to LM and ST that decremented the datacounter would be most useful.

(7) The F8 has one instruction (XDC) which exchangesdata between the data counter DCO and the auxiliary datacounter DC1. Only 3852 and 3853 (dynamic and staticmemory interfaces, respectively) devices have DC1's;3851's (program storage units) do not. Consequently,after the execution of an XDC instruction it is possiblefor the data counter registers of 3851's and those of 3852/3853's to contain different values. In this situation twodifferent devices may respond to the same memory refer-ence, resulting in very strange behavior. Executing XDC'sin pairs helps, but the anomaly can still occur after thefirst XDC and before the second. It would be much betterif 3851's were provided with DC1 registers. Until thisoccurs I recommend that the XDC instruction be usedwith great care.

Conclusion

The F8 has many of the features of a powerful controlmicroprocessor. In its single-chip form (the 3870 fromMostek*) it offers a cost-effective solution to a broad rangeof control problems. I know nothing about the tradeoffsbetween silicon real estate and F8 capabilities, but I liketo think that many of the difficulties discussed above couldhave been designed away without significant increases incost. I think the company that produces an 'F8A' thatretains the F8 advantages and eliminates the drawbackswill see a satisfying response from the marketplace. It willcertainly get my business. U

References

1. A. Osborne, "An Introduction to Microcomputers," Vol-ume II, 1976. Pages 2-1 to 2-39.

2. "F8 User's Guide," #67095665, Fairchild Camera & Instru-ment Corp., 1976.

3. "Guide To Programming," #67095664, Fairchild Camera& Instrument Corp., 1976.

David C. Caulkins is the chief engineer atCabledata Associates. He was previously thehead of the hardware group on the Illiac IVproject, Institute for Advanced Computation,NASA-Ames. His current interests are inreal-time microcomputer control systems,distributed computer networks, computermessage systems, and personal computing.Caulkins received his BSEE from Lehigh

University. He is a member of the IEEEComputer Society, ACM, and the Homebrew Computer Club.

*Now second-sourced by Fairchild.

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