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US 20030111682A1 (12) Patent Application Publication (10) Pub. No.: US 2003/0111682 A1 (19) United States Tanaka et al. (43) Pub. Date: Jun. 19, 2003 (54) NONVOLATILE MEMORY AND PROCESSING SYSTEM (75) Inventors: Hitoshi Tanaka, Ome (JP); Masanori Isoda, Sayama (JP); Takayuki Kawahara, Higashiyamato (JP) Correspondence Address: MILES & STOCKBRIDGE PC 1751 PINNACLE DRIVE SUITE 500 MCLEAN, VA 22102-3833 (US) (73) Assignee: Hitachi, Ltd. (21) Appl. No.: 10/308,106 (22) Filed: Dec. 3, 2002 (30) Foreign Application Priority Data Dec. 14, 2001 (JP) .................................... .. 2001-381428 Publication Classi?cation (51) Int. Cl.7 ...................... .. H01L 27/108; H01L 29/76; H01L 29/94; H01L 31/119 (52) Us. 01. ............................................................ ..257/296 (57) ABSTRACT It is an object of the present invention to alloW a voltage generating section Which produces a high voltage to effi ciently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a ?ash memory. The intermediate voltage charge pump circuit comprises sWitching elements, a ?rst charge pump circuit comprising capacitors, a second charge pump circuit com prising sWitching elements, capacitors and an equalizer comprising sWitching elements. These elements are driven by driving signals. Aperiod during Which all of one contacts of parasitic capacities Capacitor are brought into ?oating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the sWitching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced While reusing electric charge While using electric charge discharged to a reference potential by neXt cycle. V(A)>V(B)>V(C) A B O C + p CpZX 11. r) W ‘L “f1 WHW p-Sub
Transcript of “f1 WHW
US 20030111682A1
(12) Patent Application Publication (10) Pub. No.: US 2003/0111682 A1 (19) United States
Tanaka et al. (43) Pub. Date: Jun. 19, 2003
(54) NONVOLATILE MEMORY AND PROCESSING SYSTEM
(75) Inventors: Hitoshi Tanaka, Ome (JP); Masanori Isoda, Sayama (JP); Takayuki Kawahara, Higashiyamato (JP)
Correspondence Address: MILES & STOCKBRIDGE PC 1751 PINNACLE DRIVE SUITE 500 MCLEAN, VA 22102-3833 (US)
(73) Assignee: Hitachi, Ltd.
(21) Appl. No.: 10/308,106
(22) Filed: Dec. 3, 2002
(30) Foreign Application Priority Data
Dec. 14, 2001 (JP) .................................... .. 2001-381428
Publication Classi?cation
(51) Int. Cl.7 ...................... .. H01L 27/108; H01L 29/76;
H01L 29/94; H01L 31/119 (52) Us. 01. ............................................................ ..257/296
(57) ABSTRACT
It is an object of the present invention to alloW a voltage generating section Which produces a high voltage to effi ciently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a ?ash memory. The intermediate voltage charge pump circuit comprises sWitching elements, a ?rst charge pump circuit comprising capacitors, a second charge pump circuit com prising sWitching elements, capacitors and an equalizer comprising sWitching elements. These elements are driven by driving signals. Aperiod during Which all of one contacts of parasitic capacities Capacitor are brought into ?oating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the sWitching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced While reusing electric charge While using electric charge discharged to a reference potential by neXt cycle.
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