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0.6µm Bulk CMOS 3Metal, 2Poly

Extra Credit: Determine the schematic for this cell

All transistors are sized equally

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(Same layout without Metal 3 layer)

M3 M2 M1

poly

N-Well

N-Select P-Select

P-Select

L11/Design Rules/Layout of MOSFETs and Interconnect)

•  Review – Layout editor – L-Edit usage – Technology parameters

•  Reading – Chapter 4 Modeling of MOS Transistors Using

SPICE (very short chapter, refer to Table 4.1 for explanation of SPICE technology parameters)

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Layout •  Assumptions:

–  If using L-Edit Windows version, layer stipple set correctly

–  Technology parameters updated

•  Use of Design Rule Checker (DRC) –  Select DRC in standard toolbar –  Can choose to write errors to file –  DRC will indicate presence of design rule violations

•  Consider NMOS layout –  What is LM? –  What is W?

NMOS Layout

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NMOS Layout •  Generation of cross-section

–  Use \MOSIS\MORBN12.XST for process definition file (not exactly same but ok for qualitative cross section)

PMOS Layout •  How does the PMOS layout differ in the n-well

CMOS process?

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PMOS Layout

Summary •  Layout Examples

– NMOS – PMOS