External Memory Interface (EMIF) Chapter 13 C6000 Integration Workshop Copyright © 2005 Texas...

External Memory Interface (EMIF)

Chapter 13

C6000 Integration Workshop

Copyright © 2005 Texas Instruments. All rights reserved. Technical Training

Organization

T TO

Outline Memory Maps

Device DSK

Memory Types Programming the EMIF Lab Exercise Additional Memory Topics

Technical TrainingOrganization

T TO

Memory Map Review

8000_0000

128MB CE3

9000_0000

B000_0000

128MB CE2

128MB CE1

128MB CE0

A000_0000

128 MB8000_0000CE0

A000_0000CE2

C6000CPU

L2 SRAM

EMIF

64KB L2 SRAM

B000_0000CE3

9000_0000CE1

128 MB

128 MB 128 MB

0000_0000

A Memory Map is atable representationof memory…


T TO

FFFF_FFFF

0000_0000

256KB InternalProgram / Data

Peripheral Regs0180_0000

128MB External

128MB External

8000_0000

9000_0000

A000_0000

B000_0000

128MB External

128MB External

TMS320C6713

Available viaDaughter Card

Connector

‘C6713 DSK

16MB SDRAM

256K byte FLASH

CPLD

C6713 DSK Memory Map

CPLD:LED’sDIP SwitchesDSK statusDSK rev#Daughter Card

9008_0000

Outline

Memory Maps Memory Types

Overview Selecting a Memory Type SDRAM Specifics ASYNC Specifics

Programming the EMIF Lab Exercise Additional Memory Topics


T TO

SDRAM - Synchronous (clocked) DRAM SDRAM provides lowest cost / bit

cheap Operates up to 100 MHz

fast Built-in SDRAM controller makes interfacing simple

easy Only SDRAM can reach full address space

big

Memory Types Overview

16M ByteSDRAMCPU

EDMA

EMIF

ASYNC - Traditional (unclocked) memories Wide array of memories (Flash, SRAM, Regs, FPGA/ASIC) Can use buffer/drivers, address decoding, etc.

flexible Allows multiprocessor access

share

Flash (ASYNC)

I/O Port (ASYNC)

Note: SBSRAM is covered later in the chapter - it's not implemented on the DSK

Selecting Memory Type

Global Control

SDRAM Refresh Prd

SDRAM Control

180_001C

180_0018

180_0000

180_0020

MTYPE7 4

CEx Control Register

RW, +0010

0000b = 8-bit-wide Async



0011b = 32-bit-wide SDRAM

0100b = 32-bit-wide SBSRAM





SDRAM Extension

CE1 Control

CE3 Control

CE0 Control

CE2 Control180_0004

180_0014

180_0008

180_0010


T TO

Outline

Memory Maps Memory Types

Overview Selecting a Memory Type Using SDRAM Using ASYNC

Programming the EMIF Additional Memory Topics


T TO

Using SDRAM

1. Select SDRAM and verify it meets system performance timing Due to high MHz bus frequencies, we provide

some practical suggestions on the next 2 slides

2. Setup SDRAM control registers

3. Calculate SDRAM refresh timing (period)


T TO

DM642 SDRAM Recommendations Due to datasheet requirements, the following is recommended:

1 bank (max of 2 chips) of SDRAM connected to EMIF Up to 1 bank of buffers connected to EMIF for async memories Trace lengths between 1 and 3 inches 183MHz SDRAM for 133MHz EMIF operation 143MHz SDRAM for 100MHz EMIF operation

Therefore: To run the EMIF at 133MHz and meet the above requirements, the largest

memory size available today is 16M Bytes using two 2Mx32 SDRAMs.

Alternatively: The largest memory size achievable using x32 devices is 32MBytes

using 4Mx32 SDRAMs. However, these devices are only available at 166Mhz.

Another option is to use x16 devices, but you have to use four of these since the EMIF is 64 bits wide. Also, the fastest speed grade is 167MHz.

* These guidelines are for DM642 in June 2003. Other C6000 devices require similar consideration.Technical TrainingOrganization

T TO

SDRAM Design Considerations Use Daisy chaining or minimum stub length routing on EMIF signals Keep trace lengths as close as possible to the same length ‘Swizzle’ signals such that they are flow through to avoid signal criss-

crossing as much as possible. For example, on resistor packs or SDRAM data pins on a ‘byte’ boundary

Serial termination resistors should be inserted into all EMIF output signal lines to maintain signal integrity

Use controlled impedance of 50-60 ohms on layout/pwb fabrication Ground layer is a must, and can be duplicated to help with controlled

impedance any time there is an odd number of layers Perform timing analysis to verify A/C timings are met using

I/O Buffer Information Specification (IBIS) In fact, using IBIS modeling you may find you can improve upon the

suggestions provided on the previous slide Refer to application note: Using IBIS Models for Timing Analysis

http://www-s.ti.com/sc/psheets/spra839a/spra839a.pdf


T TO

Using SDRAM

1. Select SDRAM and verify it meets system performance timing

2. Setup SDRAM control registers Read values off SDRAM data sheet to set

control register values

3. Calculate SDRAM refresh timing (period)


T TO

SDRAM Control Register

TRCD = 30ns / 10ns - 1 = 2 TRP = 30ns / 10ns - 1 = 2 TRC = 90ns / 10ns - 1 = 8

From SDRAM

Datasheet

EMIF Clockspeed

TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC

15 12 0

reserved

rsv


T TO


Oh, here’s a couple other small details:

SDRAM Column Size(SDCSZ)

00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved

TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC

15 12 0

reserved

SDCSZrsv




00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved

SDRAM Row Size(SDRSZ)

00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved

TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC

15 12 0

SDRSZ

reserved

SDCSZrsv



TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC

15 12 0

SDRSZ

reserved

SDCSZSDBSZ


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved

SDRAMBank Size(SDBSZ)

0 = 1 pin (2)

1 = 2 pins (4)


0 = 1 pin (2)

1 = 2 pins (4)

rsv



TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC

15 12 0

SDRSZ Init

reserved

SDCSZSDBSZ


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved


0 = 1 pin (2)

1 = 2 pins (4)


0 = 1 pin (2)

1 = 2 pins (4)

Initialization(INIT)

0 = No effect

1 = Initialize


0 = No effect

1 = Initialize

rsv



TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC

15 12 0

SDRSZ INIT

reserved

RFENSDCSZSDBSZ

‘C6x does Refresh(REFEN)

0 = No

1 = Yes

‘C6x does Refresh(REFEN)

0 = No

1 = Yes

rsv


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 9 pins (512)

01 = 8 pins (256)

10 = 10 pins (1024)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved


00 = 11 pins (2048)

01 = 12 pins (4096)

10 = 13 pins (8192)

11 = reserved


0 = 1 pin (2)

1 = 2 pins (4)


0 = 1 pin (2)

1 = 2 pins (4)


0 = No effect

1 = Initialize


0 = No effect

1 = Initialize

Using SDRAM

1. Select SDRAM and verify it meets system performance timing

Setup SDRAM control registers

3. Calculate SDRAM refresh timing And program SDRAM refresh timing register


T TO

SDRAM Refresh Timing Register

= 1562 (0x61A)

From the SDRAM data sheet:

Refresh Rate = “4K Auto Refresh each 64ms”

= 64 ms / 4096

PeriodCounterreserved

31 26 25 24 23 12 11 0

R, +0 RW, +00 R, +010111011100 RW, +010111011100

XRFR

Assuming 100MHz EMIF Clockspeed

= (64ms/4096) / 10ns

Period = tRefresh Rate / tECLK


T TO

Outline - Memory Types

Overview Selecting a Memory Type Using SDRAM Using ASYNC

Generic Read Timing Async Example - Flash Flash Read Timing Flash Write Procedure


T TO

Async Read Timing

ECLKOUT

EA, CE, BE

AOE

Async Read Timing

Setup Strobe Hold

ECLKOUT

AOE

ARE

ED

EA, CE, BE


T TO

Setup = 1 Strobe = 2 Hold = 1

Async Read Timing

ECLKOUT

AOE

ARE

C6x11 range: 1 - 15 1 - 63 0 - 7

Read HoldMTYPERead Strobe Read Setup

CEx Register

ED

EA, CE, BE

19 16 13 8 7 4 2 0


T TO

Flash Read Timing

9008 0000h

Available viaDaughter Card

Connector

C6711 DSK

16MB SDRAM

128KB FLASH

4 byte I/O Port

LED’s Switches DSK status DSK rev#

9000 0000h

DSK has 128K Flash Provides re-programmable,

non-volatile memory Pre-program with code, init

values and boot-strap program Stores non-volatile, run-time data

Looking more closely at the timing …Technical Training

Organization

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Flash Read Timing

Setup = ______

Strobe = ______

Hold = ______

Let's figure out the timing for the DSK's async Flash memory …

150ns

100ns

150ns

0ns

50ns

Use EMIF’sARE pin


T TO

Flash Read Timing

150ns

100ns

150ns

0ns

50nsSetup = ______

Strobe = ______

Hold = ______

Note: Memory timing is highly dependent upon board-related design factors. While this example approximates the DSK timing, your board requirements may differ.

5105

Use EMIF’sARE pin

Writing to DSK's Flash Flash is a non-volatile memory,

i.e. it can't normally be written to

To change it's content, you must "unlock" it with a special procedure:

PC based tools available for Flash programming

BSL functions allow runtime writing to Flash

1. Write 0xAA to 0x55552. Write 0x55 to 0x2AAA3. Write 0xA0 to 0x55554. Write new data to 128 byte sector

(data must be written in 128 byte chunks)

Flash requires 20ms to complete internal write cycle. Data I/O7 can be polled to determine when write cycle is complete.


T TO

Using Async

Generic Read Timing Flash Read Timing Flash Write Procedure Optional

Maximum Async Performance Generic Async Write Timing Bus Turnaround Time


T TO

Outline Memory Maps Memory Types Programming the EMIF

C language via CSL Assembly GEL

Additional Memory Topics


T TO

Program EMIF with CSL

far const EMIFA_Config C6416DskEmifConfigA = {EMIF_GBLCTL_RMK( // 0x00012070

EMIF_GBLCTL_EK2RATE_FULLCLK, // bits 18-19 = 00EMIF_GBLCTL_EK2HZ_CLK, // bit 17 = 0EMIF_GBLCTL_EK2EN_ENABLE, // bit 16 = 1EMIF_GBLCTL_BRMODE_MRSTATUS, // bit 13 = 1EMIF_GBLCTL_BUSREQ_LOW, // bit 11 = 0...EMIF_GBLCTL_CLK6EN_DISABLE, // bit 3 = 0

);0x00000000, /* cectl0 **/...0x00000000 /* cesec3 */

};

void emifInit(){EMIFA_config(&C6416DskEmifConfigA);

}

Program EMIF similar to other peripherals. Since EMIF is not a multi-channel periperhal, no _open function is required.


T TO

Program EMIF with Assembly (1)EMIF .equ 0x01800000GBLCTL .equ 0x________CE0CTL .equ 0x________CE1CTL .equ 0x________CE2CTL .equ 0x________CE3CTL .equ 0x________SDCTL .equ 0x________SDTIM .equ 0x________SDOPT .equ 0x________

cEMIF: mvkl EMIF, A0mvkh EMIF, A0mvkl GBLCTL, A1mvkh GBLCTL, A1stw A1, *+A0[0]mvkl CE0CTL, A1mvkh CE0CTL, A1stw A1, *+A0[2]

…mvkh SDOPT, A1stw A1, *+A0[8]

Global Control

SDRAM Ref Prd

SDRAM Control

180_001C

180_0018

180_0000

180_0020 SDRAM Extension

CE1 Control

CE3 Control

CE0 Control

CE2 Control

180_0004

180_0014

180_0008

180_0010

Add the desired register values to the blank spaces and code will program EMIF

Assembly code will work for all devices, if you …

Better yet, …Technical Training

Organization

T TO

Program EMIF with Assembly (2)

/* Include Header File #include “csl_emif.h”

/* Config Structures */far const EMIF_Config myEM 0x00003078, /* Global Control Reg. (GBLCTL) */ 0x00000020, /* CE0 Space Control Reg. (CE0CTL)*/ 0xFFFF3F23, /* CE1 Space Control Reg. (CE1CTL)*/ 0x00000030, /* CE2 Space Control Reg. (CE2CTL)*/ 0xFFFF3F23, /* CE3 Space Control Reg. (CE3CTL)*/ 0x0388F000, /* SDRAM Control Reg.(SDCTL) */ 0x00000040 /* SDRAM Timing Reg.(SDTIM) */ 0x00F02AE0 /* SDR};

.global _myEMIF

EMIF .equ 0x01800000

cEMIF: mvkl EMIF, A0 mvkh EMIF, A0 mvkl _myEMIF, A1 mvkh _myEMIF, A1 ldw *A1, A2 stw A2, *A0 ldw *++A1[1], A2 stw A2, *+A0[2] ... ldw *++A1[1], A2 stw A2, *+A0[8]

Create EMIF_Config structure and use assembly to write configuration values to peripheral

Note: must use “far const” declaration for this method to work


T TO

init_emif(){ // First we define the EMIF addresses#define EMIF_GCTL 0x01800000#define EMIF_CE1 0x01800004#define EMIF_CE0 0x01800008#define EMIF_CE2 0x01800010#define EMIF_CE3 0x01800014#define EMIF_SDRAMCTL 0x01800018#define EMIF_SDRAMTIMING 0x0180001C#define EMIF_SDRAMEXT 0x01800020 // Now we set the values*(int *)EMIF_GCTL = 0x00003300; // EMIF global*(int *)EMIF_CE0 = 0x00000030; // CE0-SDRAM*(int *)EMIF_CE2 = 0xFFFFFF23; // CE2-32bit async on daughtercard*(int *)EMIF_CE3 = 0xFFFFFF23; // CE3-32bit async on daughtercard*(int *)EMIF_SDRAMCTL = 0x07227000; // SDRAM control register(100 MHz)*(int *)EMIF_SDRAMTIMING = 0x0000061A; // SDRAM Timing register *(int *)EMIF_SDRAMEXT = 0x00054529; // SDRAM Extension register}

init_emif(){ // First we define the EMIF addresses#define EMIF_GCTL 0x01800000#define EMIF_CE1 0x01800004#define EMIF_CE0 0x01800008#define EMIF_CE2 0x01800010#define EMIF_CE3 0x01800014#define EMIF_SDRAMCTL 0x01800018#define EMIF_SDRAMTIMING 0x0180001C#define EMIF_SDRAMEXT 0x01800020 // Now we set the values*(int *)EMIF_GCTL = 0x00003300; // EMIF global*(int *)EMIF_CE0 = 0x00000030; // CE0-SDRAM*(int *)EMIF_CE2 = 0xFFFFFF23; // CE2-32bit async on daughtercard*(int *)EMIF_CE3 = 0xFFFFFF23; // CE3-32bit async on daughtercard*(int *)EMIF_SDRAMCTL = 0x07227000; // SDRAM control register(100 MHz)*(int *)EMIF_SDRAMTIMING = 0x0000061A; // SDRAM Timing register *(int *)EMIF_SDRAMEXT = 0x00054529; // SDRAM Extension register}

Program EMIF with GEL

When does this GEL script get executed?

/* * The StartUp() function is called every time you start Code Composer. * You can customize this function to perform desired initialization. * This function may be commented out if no initialization is needed. */

StartUp() { setup_memory_map(); GEL_Reset(); init_emif();}

/* * The StartUp() function is called every time you start Code Composer. * You can customize this function to perform desired initialization. * This function may be commented out if no initialization is needed. */

StartUp() { setup_memory_map(); GEL_Reset(); init_emif();}

OpenDSK6211_6711.gel

GEL Startup


T TO

Outline Memory Maps Memory Types Programming the EMIF Additional Memory Topics


T TO


Performance Considerations Fanout / System Shared Memory (HOLD, HOLDA) Overview of SBSRAM SDRAM Optimization C6000 Family EMIF Comparison


T TO

DMC

1

2

mem

‘C6201

PC

3

4regs

CPU Load from Internal Memory

Even though an internal memory access requires a four cycle access time, as with most modern RISC processors, the C6000’s pipelined architecture provides means to overcome this delay

CPU Load from External MemoryDMC‘C6201

PC 1

1617

18 mem

EMIF

2

SBSRAM

8

15 9

4

13

5

12

6

11

7

10

3

14

Even providing a zero wait-state off-chip memory, the CPU’s access time for external memory will be upwards of 18 cycles.

Total affect is a 14 cycle delay. (18 cycles less four afforded by C6000’s hardware pipelining.)

C6201 details are shown here. Similar issues affect all C6000 devices (in fact, all high perf P), but they are manifested differently. For example, the cache in more recent devices mitigate the affect of these delays by keeping often used code and data in faster on-chip memory.

Even providing a zero wait-state off-chip memory, the CPU’s access time for external memory will be upwards of 18 cycles.

Total affect is a 14 cycle delay. (18 cycles less four afforded by C6000’s hardware pipelining.)

C6201 details are shown here. Similar issues affect all C6000 devices (in fact, all high perf P), but they are manifested differently. For example, the cache in more recent devices mitigate the affect of these delays by keeping often used code and data in faster on-chip memory.

Besides cache, what is a better way to increase EMIF throughput?Technical Training

Organization

T TO

Load from External MemoryDMC‘C6x

PC 1

1617

18 mem

EMIF

2

SBSRAM

8

15 9

4

13

5

12

6

11

7

10

3

14

Unlike the CPU, the EDMA (and DMA) can pipeline-up access through the EMIF delays to achieve single-cycle throughput from zero wait-state external memories.

While the first access may take 14 cycles, subsequent accesses can get down to a single cycle.

Unlike the CPU, the EDMA (and DMA) can pipeline-up access through the EMIF delays to achieve single-cycle throughput from zero wait-state external memories.

While the first access may take 14 cycles, subsequent accesses can get down to a single cycle.

EDMA


T TO


Performance Considerations Fanout / System Shared Memory (HOLD, HOLDA) Overview of SBSRAM SDRAM Optimization C6000 Family EMIF Comparison


T TO

‘C6201 Bus Fanout

H/W MaxType Top Speed* Wait Size/Fan Glueless

ASYNC 100 MHz Yes 16 M/ Yes/No

SBSRAM 200 MHz No 3 MB Yes

SDRAM 100 MHz No 48 MB Yes

Bus pin drivers rated for 30pf loading Devices are designed for 45pf loads, but testing

equipment cannot guarantee it Most memory devices present 5pf loads Total fanout is six memory devices While this slide is slightly old, the issue remains. Again,

IBIS modeling is an excellent way to deal with this issue.


T TO

System with All Memory Types

‘C6201 SBSRAM

SDRAM

Flash

SRAM

FPGA

CBT’s and WidebusTransceivers work great

CE0

CE2

CE3


T TO


Performance ConsiderationsFanout / System Shared Memory (HOLD, HOLDA) Overview of SBSRAM SDRAM Optimization C6000 Family EMIF Comparison


T TO

Shared Memory

SharedMemory

‘C6201OtherP

How can 2 PShare the samememory?

Using 3-state buffers.

One of the P or another device arbitrates.

Arbiter

What is the drawback of using a buffer here?

Costs you extra:

Speed, Power, Reliability, Money, etc.

Shared Memory

SharedMemory

‘C6201OtherP

Arbiter

Here’s TI’s solution …

Built in buffers!!

HOLD

Shared Memory

SharedMemory

‘C6201OtherP

ArbiterHOLD

When ‘C6x drives HOLDA active:

• EMIF signals tri-stated• CPU continues to

execute as long as no off-chip access is needed

HOLDA


T TO

HOLD Status Bits (GBLCTL)

HOLD and HOLDA status Disable HOLD feature (NOHOLD = 1)

HOLD HOLDA NOHOLD rsv CLK1EN CLK2EN rsv

R, +x R, +x RW, +x R, +11 RW, +1 RW, +1 R, +000

9 8 7 6 5 4 3 2 0

BUSREQ ARDY

R, +0 RW, +0 RW, +1 RW, +1 R, +0 R, +x

31 15 14 13 12 11 10

rsv rsv± rsv±rsv±

C6711 EMIF GBLCTL


T TO


Performance ConsiderationsFanout / SystemShared Memory (HOLD, HOLDA) Overview of SBSRAM SDRAM Optimization C6000 Family EMIF Comparison


T TO

Synchronous Burst SRAM (SBSRAM)

Access 1

Access 2

Access 3

A1A2A3/D1A4/D2A5/D3A6/D4 D5 D6

Access 4

Asynchronous Synchronous

A1D1A2D2A3D3A4D4

Pipelined memory accesses


T TO

Access 1

Access 2

Access 3

A1A2A3/D1A4/D2A5/D3A6/D4 D5 D6

Access 4

Asynchronous Synchronous

A1D1A2D2A3D3A4D4

Synchronous Burst SRAM (SBSRAM) SBSRAM's pipelines memory accesses With Burst mode a processor only needs to generate an

address every four sequential accesses Not required by C6000 DSP's as they're fast enough '0x devices don't use (have) this feature '1x devices include the burst feature for power savings

(only one address pin needs toggling for four sequential accesses)

A1-- /D1- /D2A5/D3- /D4 D5 D6

Burst


T TO

SBSRAM - Hooking it Up...

'C6201

EA[N+2:2]ED[31:0]

SSWESSOE

SSADSSSCLK

CEnBE[3:0]

SBSRAM A[N:0]D[31:0]WEOEADV, ADSPADSCCLKCSBE[3:0]

VCC


T TO

SBSRAM Timing

SSADS

CE

Data is available 2 cycles after address appears Data can be accessed at the rate of 1 per cycle

1 2 3 4 5 6 7 8 9

SSOE

EA/BE EA1/BEx EA2 EA3

ED D1 D2 D3


T TO


Performance ConsiderationsFanout / SystemShared Memory (HOLD, HOLDA)Overview of SBSRAM SDRAM Optimization C6000 Family EMIF Comparison


T TO

SDRAM Extension Register

TCLRD

2RD

09 4 3 1

TRASTWR

6 5

THZP

8 7

RD2DEAC

11 10

RD2WR

14 12

DQM

15

TRRD

R2W

1617

TRRDWR2DEAC

19 1820WR2RDRESERVED

31 21

Most SDRAMs will work without programming this register. This is the case for the C6711 DSK.

Program the SDRAM Extension (SDOPT) register to optimize SDRAM performance.

Please refer to the SDRAM applications note (at the TI website) for further details on programming this register.


T TO


Performance ConsiderationsFanout / SystemShared Memory (HOLD, HOLDA)Overview of SBSRAMSDRAM Optimization C6000 Family EMIF Comparison


T TO

EMIF Variations Devices 'x01 'x02/3/4/5 'x11 '6712 '64x (A) '64x (B)

Scheme '0x '1x '1x

Bus Width 32 32 32 16 64 16

Size (MB) 52 52 512 256 1024 256

Sync

Clocking

CPU clk

½ CPU clk½ CPU clk

Independent ECLKIN

( 100MHz)

Independent ECLKIN¼ CPU clk1/6 CPU clk

CE1 Types Async Only Sync & Async Sync & Async

Sync Mem Allowed

in System

Both SDRAM & SBSRAM

Either SDRAM or SBSRAM

Both

SDRAM and SBSRAMAll

Pipelined SBSRAM

Flow thru SBSRAM

ZBT SRAM

Std Sync FIFO

FWFT FIFO

ti


External Memory Interface (EMIF) Chapter 13 C6000 Integration Workshop Copyright © 2005 Texas...

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Transcript of External Memory Interface (EMIF) Chapter 13 C6000 Integration Workshop Copyright © 2005 Texas...