Exploring a CPLD/FPGA-based Triggering System for LCLS
description
Transcript of Exploring a CPLD/FPGA-based Triggering System for LCLS
![Page 1: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/1.jpg)
Exploring a CPLD/FPGA-based Triggering System for LCLS
Matthew T. BrownOffice of Science, Science Undergraduate Laboratory Internship Program
Advisor: Ron Akre
![Page 2: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/2.jpg)
CPLD/FPGA Basics
Gates Macrocells LUTs JTAG Programmer Xilinx ISE
![Page 3: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/3.jpg)
Xilinx Cool Runner XPLA XCR3064XL
![Page 4: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/4.jpg)
Xilinx Spartan 3 XC3S200PQ208-5
![Page 5: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/5.jpg)
The Task at Hand
360Hz fiducial signal Set delays Triggering requirements
– Delay– Pulse length– Jitter
![Page 6: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/6.jpg)
How It’s Done
24-bit counter Comparators Flip flops Design entry
– Schematic – Text (VHDL code written for 8 channels)
![Page 7: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/7.jpg)
Simple Timing Diagram
![Page 8: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/8.jpg)
Schematic Example
![Page 9: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/9.jpg)
CPLD Results
Not good enough!
![Page 10: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/10.jpg)
FPGA Results
![Page 11: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/11.jpg)
FPGA Results Strike Back
Jitter measured to be below 2 picoseconds
![Page 12: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/12.jpg)
Return of the FPGA Results
Onboard Arcturus Coldfire Processor
Four DCMs on the chip allow for sub-clock cycle phase adjusting for the triggers
![Page 13: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/13.jpg)
Conclusion and Possible Future Work
CPLD = No
FPGA = Yes
Need to:– Build a board with all 8 channels on it– Complete the computer-FPGA interface
![Page 14: Exploring a CPLD/FPGA-based Triggering System for LCLS](https://reader035.fdocuments.in/reader035/viewer/2022062323/56815255550346895dc088d1/html5/thumbnails/14.jpg)
Acknowledgements
Thanks to Ron Akre, Jeff Olsen, Bo Hong, and Anatoly Krasnykh for help on this project.
Thanks to Steve Rock, Susan Schultz, and Farah Rahbar for managing us kids and the SULI program at SLAC.
Questions?
Sources:– http://supercomputing.fnal.gov/slac_logo.jpg– http://images.amazon.com/images/P/6305428387.01.LZZZZZZZ.jpg– http://therawfeed.com/pix/this_is_sparta.jpg