CPLD FPGA33
-
Upload
swetha-vanam -
Category
Documents
-
view
243 -
download
0
Transcript of CPLD FPGA33
-
7/28/2019 CPLD FPGA33
1/32
Technology evolution
-
7/28/2019 CPLD FPGA33
2/32
Transistor-Era
In 1947 on Dec 23
rd
Physicists William Shockley, WalterBrattain, and John Bardeen, working at Bell
Laboratories in US. Invented the first transistor using
Ge.
In 1950 the first transistor BJT was introduced
Ten years before the bipolar transistor was invented, the
principles of operation were patented for another type
of transistor called MOSFET
-
7/28/2019 CPLD FPGA33
3/32
In 1962 Steven Hofstein and Fredric
Heiman at the RCA Labs,in princeton,
New Jersey invented a MOSFET
They are cheaper , smaller, and low power
consumption but low speed
-
7/28/2019 CPLD FPGA33
4/32
Integrated Circuit (IC)
The first transistors were provided as discrete
components that were individually packaged in a small
metal cans. But people started to think that it wouildd be
a good idea to fabricate entire circuit on a single pieceof semiconductor.
A British RADAR expert GWA Dummer presented his
paper in 1952. But in 1958 that Jack KIlby working for
Texas Instruments (TI) fabricated first IC a Phase-shift
oscillator.
-
7/28/2019 CPLD FPGA33
5/32
Around the same time that kilby was
working, two of the founders of the
Fairchild semiconductors the swissphysicist (Jean Hoerni) and the american
physicist(Robert Noyce) inventented the
underlying optical litographic techniques
that are now used to create transistor ,
insulating layers and interconnections.
TI introduced simple 54xx and 74xx ICsduring mid-1960s by TTL logic families
By RCA CMOS based 4000 series.
-
7/28/2019 CPLD FPGA33
6/32
Next generation of ICs SRAMs,
DRAMs, and Processors
1960s and 1970s Digital Era.
In 1970 Intel announced the first IC 1024 bitDRAM (1103)
And Fairchaild announced 256 bit SRAM(4100)
In 1971 Intel indroced the worlds first
Microprocessor -4004(around2300transistors and 60K operations persecond)
-
7/28/2019 CPLD FPGA33
7/32
Programmable Logic
What is meant my programming?
The specific function of an IC for a given application is
determined by the selective breaking of some the
interconnections while leaving the others intact (unbroken).
PLD =Programmable Logic Device
PLD is an IC which contains a large number of
interconnected gates , flip-flops and Registers.
-
7/28/2019 CPLD FPGA33
8/32
commercially available high-capacity
Field-Programmable Devices (FPDs)
The three main categories of FPDs are delineated:
1) Simple PLDs (SPLDs),
2) Complex PLDs (CPLDs) and
3) Field-Programmable Gate Arrays (FPGAs)
-
7/28/2019 CPLD FPGA33
9/32
Advantages
Iow density
Low production cost
Lesser power requirement Easy programming
-
7/28/2019 CPLD FPGA33
10/32
SPLDs and CPLDs
PLD=SPLD
-
7/28/2019 CPLD FPGA33
11/32
ROMs
ROM s are simply memory devices
PROM,EPROM,EEPROM
ROM s are simply memory devices
PROM,EPROM,EEPROM
-
7/28/2019 CPLD FPGA33
12/32
ROM (PROM)
A PROM is a combinational circuit which can
be used to generate a desired logic function .
It has M address (representation of input)
lines and N data (output) lines
It has hardwired (fixed) AND array and
Programmable OR array.
-
7/28/2019 CPLD FPGA33
13/32
The M inputs are generated from the
decoder logic.
D
E
C
O
DE
R
n*2n
.
.
.
.
.
.
.
.
P--Address
Bits
M--Address lines(M=2p)
N--Data (output) Lines
-
7/28/2019 CPLD FPGA33
14/32
Structure of PROM
-
7/28/2019 CPLD FPGA33
15/32
Exanple
-
7/28/2019 CPLD FPGA33
16/32
-
7/28/2019 CPLD FPGA33
17/32
Example--1
Y0=A
Y1=CBA
Y2=CBA
In this example the output y0 has only one variable as
output function then we need to find out the Boolean
function to get A output. The output y0
can be realized by
minimizing the minters (1,3,5,7) , so we have to intact
(connect) the fuse for the four minterm values.
-
7/28/2019 CPLD FPGA33
18/32
Example--2
F1= m(1,5,7,8)
F2= m(0,2,5,8,12,15,17,18)
F3= m(4,5,7,15,18,21,30)
So we need 5 bit address lines and 3 output lines. But
there is 32*8 ROM only, so remaining 5 output lines
are open (unused)
-
7/28/2019 CPLD FPGA33
19/32
PROM generates every possible AND productterm , so it is useful in cases where it is required
that every input combination should be available.
When the input variables are large PROM
becomes impractical.
-
7/28/2019 CPLD FPGA33
20/32
Advan&Dis Afvantages of PROM
Less cost
No simplification is required
Flexibility in design
Dis advantages
The complete circuit is not used
More power requirement
Not suitable when number of inputs arelarge.
-
7/28/2019 CPLD FPGA33
21/32
PLA
-
7/28/2019 CPLD FPGA33
22/32
Example of PLA
-
7/28/2019 CPLD FPGA33
23/32
Drawback of PLA
Signals take long time to pass through the
Programmable links. So PLAs are slower
than PROMs.
-
7/28/2019 CPLD FPGA33
24/32
PAL
-
7/28/2019 CPLD FPGA33
25/32
PAL Example
Advantage is that they are faster because only
one of their arrays are programmable
But Disadvantage is that it allows only limitednumber of and gates are ORed
-
7/28/2019 CPLD FPGA33
26/32
CPLDs
In 1984 When newly formed Altera
introduced a CPLD based on a
combination of CMOS and EPROM
technologies. For little power consumption.
-
7/28/2019 CPLD FPGA33
27/32
CPLD architecture
-
7/28/2019 CPLD FPGA33
28/32
CPLD architecture
CPLD F ti l bl k
-
7/28/2019 CPLD FPGA33
29/32
CPLD Functional block
-
7/28/2019 CPLD FPGA33
30/32
CPLD I/O block
-
7/28/2019 CPLD FPGA33
31/32
Architecture issues of CPLD
The Programming technology
The functional block capability
The I/O capability
-
7/28/2019 CPLD FPGA33
32/32
CPLD Examples
Altera MAX 7000and 9000
AMDs(Advanced Micro Devices)
CLPDs(Match 1 to 5)
Atmel ATF and ATV familkies
Lattice family
Cypress faly Xilix family