Short Course On Phase-Locked Loops and Their Applications

Day 4, PM Lecture

Examples of Leveraging Digital Techniques in PLLs

Michael PerrottAugust 14, 2008

Copyright © 2008 by Michael H. PerrottAll rights reserved.

2M.H. Perrott

Outline

Example of high performance digital frequency synthesizer- Goal: wide bandwidth (500 kHz) and low phase noise- Techniques to achieve low implementation complexity

Example of high performance mixed-signal clock and data recovery- Goal: low jitter and full integration with compact area- Techniques to achieve low implementation complexity

3M.H. Perrott

Going Digital …

Digital loop filter: compact area, insensitive to leakageChallenges: - Time-to-Digital Converter (TDC)- Digitally-Controlled Oscillator (DCO)

Staszewski et. al.,TCAS II, Nov 2003

out(t)ref(t) Analog

Loop FilterPhase

Detect

VCO

Time

-to-

Digital

out(t)ref(t) Digital

Loop Filter

DCO

Divider

Divider

4M.H. Perrott

Assumptions: - delay = 20ps- carrier freq.

= 3.6GHz - reference freq.

= 50MHz- PLL BW

= 50kHz- 3rd order ΔΣ

VCO noise dominates performance everywhere …Don’t need very high TDC resolutionΔ−Σ fractional-N quantization noise is not an issue

Examine Noise Performance: Narrow-Bandwidth Case

Total Noise

5M.H. Perrott

Examine Noise Performance: Wide-Bandwidth Case

Noise dominated by TDC at low frequenciesNoise dominated by ΔΣ fractional-N noise at high frequencies

Assumptions: - delay = 20ps - carrier freq.

= 3.6GHz - reference freq.

= 50MHz- PLL BW

= 500kHz- 3rd order ΔΣ

Total Noise

6M.H. Perrott

To Meet High Performance Applications like GSM….

Need 6-ps TDC resolution and 20dB cancellation of Δ−Σfractional-N noise to achieve 500kHz bandwidth

Assumptions: - delay = 6ps- carrier freq.

= 3.6GHz - reference freq.

= 50MHz- PLL BW

= 500kHz- 3rd order ΔΣ

(20dB lower)

Total Noise

7M.H. Perrott

Proposed Digital Wide BW Synthesizer

Gated-ring-oscillator (GRO) TDC achieves low in-band noiseAll-digital quantization noise cancellation achieves low out-of-band noiseDesign goals: - 3.6-GHz carrier, 500-kHz bandwidth- <-100dBc/Hz in-band, <-150 dBc/Hz at 20 MHz offset

8M.H. Perrott

Key Enablers: GRO and ΔΣ Frac-N Noise Cancellation

GRO offers low noise at low frequency offsetsΔΣ fractional-N noise cancellation offers low noise at high frequency offsets

9M.H. Perrott

Proposed Multi-Path GRO TDC

Average delay per stage is reduced from 35ps to 6ps- Noise shaping further improves effective resolution

Hsu, Straayer, PerrottISSCC 2008

10M.H. Perrott

Reduction of Fractional-N Quantization Noise

PFD LoopFilter

N/N+1

Ref Out

M-bit 1-bit

Div

ΔΣ

Modulator

Fout

Noise

FrequencySelection

FrequencySelection

OutputSpectrum

QuantizationNoise Spectrum

PLL dynamicsΔΣ

Increasing PLL bandwidth increases impact of ΔΣfractional-N noise- Cancellation offers a way to counter this effect

11M.H. Perrott

Previous Analog Quantization Noise Cancellation

Phase error due to ΔΣ is predicted by accumulating ΔΣ quantization errorGain matching between PFD and D/A must be precise

Matching in analog domain limits performance

12M.H. Perrott

Proposed All-digital Quantization Noise Cancellation

Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely eliminated

Hsu, Straayer, PerrottISSCC 2008

13M.H. Perrott

Details of Proposed Quantization Noise Cancellation

Correlator out is accumulated and filtered to achieve scale factor- Settling time chosen to be around

10 usSee analog version of this technique in Swaminathan et.al., ISSCC 2007

14M.H. Perrott

Overall Synthesizer Architecture

Note: Detailed behavioral simulation model available at http://www.cppsim.com

15M.H. Perrott

Dual-Port LC VCO

Frequency tuning:- Use a small 1X varactor to minimize noise sensitivity- Use another 16X varactor to provide moderate range- Use a four-bit capacitor array to achieve 3.3-4.1 GHz range

16M.H. Perrott

VCO Varactor

Accumulation-mode varactor used for both coarse and fine frequency tuning- Coarse varactor is 16 times the size of fine varactor- Provides good ratio of capacitance versus voltage

variation with limited supply voltage

n+ n+

N-well

gate

+_

P-sub

17M.H. Perrott

Switched Structure for Coarse Cap Tuning

Ma0 provides low differential resistance for caps- Ma3 and Ma4 provide low bias voltage to minimize Ma0

channel resistance when Ma0 is turned on Minimizes impact on Q of tank

Ma2 provides high bias when Ma0 is turned off- Keeps voltage at n1 and n2 defined and prevents turn-

on of Ma0

S.T. Lee et.al.,JSSC, Dec 2004

18M.H. Perrott

Digitally-Controlled Oscillator with Passive DAC

Goals of 10-bit DAC- Monotonic- Minimal active circuitry and no transistor bias currents- Full-supply output range

1X varactor minimizes noise sensitivity16X varactor provides moderate rangeA four-bit capacitor array covers 3.3-4.1GHz

19M.H. Perrott

Operation of 10-bit Passive DAC (Step 1)

5-bit resistor ladder; 5-bit switch-capacitor arrayStep 1: Capacitors Charged- Resistor ladder forms VL = M/32•VDD and VH = (M+1)/32•VDD,

where M ranges from 0 to 31- N unit capacitors charged to VH, and (32-N) unit capacitors

charged to VL

20M.H. Perrott

Operation of 10-bit Passive DAC (Step 2)

Step 2: Disconnect Capacitors from Resistors, Then Connect Together- Achieves DAC output with first-order filtering- Bandwidth = 32• Cu/(2π•Cload)•50MHz

Determined by capacitor ratioEasily changed by using different Cload

21M.H. Perrott

Now Let’s Examine Divider …

Issues: - GRO range must span entire reference period during

initial lock-in

22M.H. Perrott

Proposed Divider Structure

Resample reference with 4x division frequency- Lowers GRO range to one fourth of the reference period

Divide value =N0+N1+N2+N3

23M.H. Perrott

Proposed Divider Structure (cont’d)

Place ΔΣ dithered edge away from GRO edge- Prevents extra jitter due to divide-value dependent delay

24M.H. Perrott

Asynchronous Divider Structure

Vaucher et. al., “A Family of Low-Power Truly Modular Programmable Dividers …”, JSSC, July 2000

IN OUT

modinmodout

2/3

CON

IN OUT

modinmodout

2/3

CON

IN OUT

modinmodout

2/3

CON Vdd

CON0 CON1 CON2

IN OUT

INAB

OUT

8 + CON0*20 + CON1*21 + CON2*22

A B

25M.H. Perrott

Implementation of 2/3 Sections in Modular Approach

Same as discussed on day 2 of this class

LATCHD Q

Qclk

IN

LATCHD Q

Qclk

LATCHDQ

Q clk

LATCHDQ

Q clk

OUT

modin

modout

2/3 Circuits

CON*

CON

ControlQualifierCircuits

26M.H. Perrott

Implementation of 2/3 Section

Combines logic gates into TSPC latches - Requires only 1 ma at 3.6 GHz operation in 0.13u CMOS!

fout

MODin

CON MODout

fin

N-LatchP-Latch

Flip-Flop

CON*

27M.H. Perrott

Dual-Path Loop Filter

Step 1: resetStep 2: frequency acquisition- Vc(t) varies- Vf(t) is held at midpoint

Step 3: steady-state lock conditions- Vc(t) is frozen to take quantization noise away- ΔΣ quantization noise cancellation is enabled

28M.H. Perrott

Fine-Path Loop Filter

Equivalent to an analog lead-lag filter- Set zero (62.5kHz) and first pole (1.1MHz) digitally- Set second pole (3.1MHz) by capacitor ratio

First-order ΔΣ reduces in-band quantization noise

29M.H. Perrott

Same Technique Poses Problems for Coarse-Tune

DAC thermal noise impacts performance due to the higher coarse VCO gain- Can we somehow lower

the DAC bandwidth?

30M.H. Perrott

Fix: Leverage the Divider as a Signal Path

Bypass to divider for feed-forward path allows coarse DAC bandwidth to be dramatically reduced!

31M.H. Perrott

Linearized Model of PLL Under Fine-Tune Operation

Standard lead-lag filter topology but implemented in digital domain- Consists of accumulator plus feedforward path

e[k]T

2π

TDCGain

1

Δtdel

Φref[k]

H(z)

LoopFilter

2πKv

s

1

T

T

1

Nnom

DT-CT

CT-DT

Φdiv[k]

Φout(t)

z=ej2πfT s=j2πf

V

2B

DACGain

K1

1

1-z-1

1

ΔΣ

1-α

1-αz-1K2 Gain

Accumulator

Gain

first-orderIIR

VCO

divider

32M.H. Perrott

Linearized Model of PLL Under Coarse-Tune Operation

Routing of signal path into Sigma-Delta controlling the divider yields a feedforward path- Adds to accumulator path as both signals pass back

through the divider- Allows reduction of coarse DAC bandwidth

Noise impact of coarse DAC on VCO is substantially lowered

e[k]T

2π

TDCGain

1

Δtdel

Φref[k]2πKvc

s

1

T

T

1

Nnom

DT-CT

CT-DT

Φdiv[k]

Φout(t)

s=j2πf

V

2B

DACGain

1

1-z-1

Accum. VCO

1

644

Kc 1-z-1

z-12π

Divider

1-α

1-αz-1

first-orderIIR

33M.H. Perrott

VCO Buffer Implementation

Consists of inverters with self-biased first stage- AC coupling from VCO output into buffer- Achieves low noise (as will be seen in far-out phase

noise in measured results)

1st-stage buf.

1st-stage buf.

2nd-stage buf. To Pad

(Driving 50ohm load

from instrument)

To Divider

34M.H. Perrott

Die Photo

0.13-μm CMOSActive area: 0.95 mm2

Chip area: 1.96 mm2

VDD: 1.5VCurrent: - 26mA (Core)- 7mA (VCO output

buffer at 1.1V)

GRO-TDC:- 2.3mA- 157X252 um2

35M.H. Perrott

Power Distribution of Prototype IC

Notice GRO and digital quantization noise cancellation have only minor impact on power (and area)

21.0mW (46%)

7.7mW (17%)

Digital

GRO-TDC

Ref. Buffer

DACDivider

VCO Pad Buffer

VCO 6.8mW (15%)

3.4mW (7%)

3.0mW

2.8mW

(7%)

(6%)

1.4mW (3%)

Total Power: 46.1mW

36M.H. Perrott

Measured Phase Noise at 3.67GHz

Suppresses quantization noise by more than 15 dBAchieves 204 fs(0.27 degree) integrated noise (jitter)Reference spur: -65dBc

37M.H. Perrott

103

104

105

106

107

−180

−160

−140

−120

−100

−80

−60

−40dB

c/H

z

foffset

VCO NoiseFinepath ΣΔ Quantization NoiseFine−tune DAC ThermalCoarse−tune DAC ThermalDivider Noise (1% left)GRO NoiseRef NoiseClose−loop Noise

Calculation of Phase Noise Components

See wideband digital synthesizer tutorial available at http://www.cppsim.com

38M.H. Perrott

-75

-70

-65

-60

-55

-50

3.62 3.63 3.64 3.65 3.66 3.67frequency (GHz)

Spur

(dB

c)

Measured Worst Spurs over Fifty Channels

16.2us

Tested from 3.620 GHz to 3.670 GHz at intervals of 1 MHz- Worst spurs observed close to integer-N boundary

(multiples of 50 MHz)-42dBc worst spur observed at 400kHz offset from boundary

Integer boundary(50MHz•73)

39M.H. Perrott

Conclusions

Digital Phase-Locked Loops look extremely promising for future applications- Very amenable to future CMOS processes- Excellent performance can be achieved

A low-noise, wide-bandwidth digital ΔΣ fractional-N frequency synthesizer is achieved with- High performance noise-shaping GRO TDC- Quantization noise cancellation in digital domain

Key result: < 250 fs integrated noise with 500 kHz bandwidth

Innovation of future digital PLLs will involve joint circuit/algorithm development

Mixed Signal CDR Example

41M.H. Perrott

Clock and Data Recovery Circuits for SONET

Function: recover clock from input NRZ data stream- Want to support multi-rates: 2.5 Gb/s, GbE, 622 Mb/s, 155 Mb/s

Structure: phase-locked loop with an appropriate phase detectorFocus: analog, digital, or hybrid (i.e., mixed-signal) implementation?

OpticalTransmitter

Optical fiber Optical toElectrical

Conversion

InData

Clk

Clock andData

Recovery

clk(t)

retimed data(t)

data(t) Analog

Loop FilterPhase

Detect

VCO

42M.H. Perrott

Key Jitter Performance Metrics for SONET

Jitter generation: amount of jitter produced by PLL- Achieved by designing low noise PLL

Jitter tolerance: amount of input jitter tolerated by PLL- Achieved through appropriate design of phase detector

Jitter transfer: required filtering of input jitter- Achieved by properly designing transfer function of PLL- Key challenge: need < 0.1 dB peaking in transfer function

clk(t)

retimeddata(t)

data(t) Analog

Loop FilterPhase

Detect

VCO

43M.H. Perrott

The Woes of an Analog PLL Implementation

Goal: integrated loop filterIssue: required cap value too large (100 uA charge pump):- 2.5 Gb/s (OC-48): 4 nF- 155 Mb/s (OC-3): 64 nF

clk(t)

retimeddata(t)

data(t) Analog

Loop FilterPhase

Detect

VCO

Icp

VoutCharge

Pump

Cint

freq

Jitter Peaking

1

44M.H. Perrott

Consider A Digital CDR …

Digital loop filter allows:- Easy integration of loop filter- Easy configurability for multi-rate operation

clk(t)

retimeddata(t)

data(t) Digital

VCO

Digital

Loop Filter

Phase

-to-

Digital

clk(t)

retimeddata(t)

data(t) Analog

Loop FilterPhase

Detect

VCO

45M.H. Perrott

Digital VCO Implementation

Other researchers have demonstrated a “digital” LC VCO using a switched capacitor bankIssue: better suited for 0.09u rather than 0.25u CMOS

Staszewski et. al., TCAS-II, Nov 2003& ISSCC, Feb 2004

clk(t)data(t)

Digital

VCO

Digital

Loop Filter

Phase

-to-

Digital

Va

rac

tor

Va

rac

tor

DigitalDigital

retimeddata(t)

46M.H. Perrott

Hybrid VCO Implementation

Advantages- Low phase noise, easy implementation in 0.25u CMOS

Hegazi et. al. JSSC, Dec 2001

clk(t)data(t)

Hybrid

VCO

Digital

Loop Filter

Phase

-to-

Digital

Va

rac

tor

Va

rac

tor

Digital

Analog

Digital

Analog

Digital cap

settings

D/A

Frequency

Acquisition

retimeddata(t)

47M.H. Perrott

Bang-Bang Structure as Digital Phase Detector?

Advantages: purely digital implementation with low complexity and low clock loadingIssue: leads to nonlinear CDR behavior

clk(t)data(t)

Hybrid

VCO

Digital

Loop Filter

Phase

-to-

Digital

retimeddata(t)

digital caps

D/A

D Q

D Q

D Q

D Q

retimeddata(t)

phase

error(t)

clk(t)

clk(t)

data(t)

Latch

Reg

48M.H. Perrott

A Closer Look at the Bang-Bang Detector

Phase error output consists of pulses of fixed area that are either positive or negative- Nonlinear phase detection!

Issue: PLL dynamics become nonlinear- Difficult to meet SONET Jitter Transfer Specification- Prone to limit cycle issues

retimed data(t)

clk(t)

clk(t)

data(t)D Q D Q

D Q D Q

e(t) data(t)

clk(t)

e(t)

Latch

Reg

49M.H. Perrott

A Flash Phase-to-Digital Converter?

Chain several bang-bang detectors through delays- Allows multi-level phase detection with digital structure- Similar to time-to-digital converters of other researchers

Staszewski et. al., TCAS-II, Nov 2003 & ISSCC, Feb 2004Issues:- High power consumption (multi-GHz operation required)- High clock loading (complicates VCO buffer design)- Prone to limit cycle issues

clk(t)e(t)

data(t)

clk(t)

e(t)BB PD

D E

Delay

BB PD

D E

BB PD

D E

Delay Delaydata(t)

50M.H. Perrott

An Analog Phase Detector?

Hogge detector popular in analog CDR designsAdvantages- Low complexity, power consumption, and clock loading- Leads to linear PLL dynamics

Issue- We need a digital output!

retimeddata(t)D QD Q

phase

error(t)

clk(t)

data(t)

LatchReg

data(t)

clk(t)

phase

error(t)

51M.H. Perrott

Proposed Phase-to-Digital Converter

Combine Hogge Detector with a high speed A/DIssues: - Want high resolution (i.e., to achieve high linearity) - Want low power, low clock loading, and compact area

A/D

IN

OUT

Hogge Detector

retimeddata(t)D QD Q

phase

error(t)

clk(t)

data(t)

LatchReg

digital

phase

error(t)

clk2(t)Input

CLK

Output

CLK

52M.H. Perrott

Proposed A/D Approach

A first order continuous-time Sigma-Delta A/D- Achieves high resolution, low power, low clock loading,

compact areaHow could this work??- Can easily clock at GHz speeds (i.e., high oversampling)- Hogge output provides random dithering source for free

retimeddata(t)D QD Q

clk(t)

data(t)

LatchReg

D Q

Amp

- Isd

Cint

2

Ipd

digital

phase

error(t)

clk2(t)

Continuous-Time

First Order Σ−ΔHogge Detector

53M.H. Perrott

Phase-to-Digital Converter Implementation Details

Issue 1: Hogge detector is prone to phase offsets- Caused by unequal delays for XOR input signals- Degrades jitter tolerance performance

retimeddata(t)D QD Q

clk(t)

data(t)

LatchReg

Ipd

data(t)

clk(t)

phase

error(t)

phase

error(t)

phaseoffset

Start with Hogge Detector/Charge Pump implementation

54M.H. Perrott

Improvement of Phase Offset of Hogge Detector

Extra latch improves matching of loads of Reg and LatchExtra buffer ideally matches clk-to-Q delay of Reg

retimeddata(t)D QD Q

clk(t)

data(t)

LatchReg

Ipd

D Q

Latch

Buffer

data(t)

clk(t)

phase

error(t)

phase

error(t)

55M.H. Perrott

Challenge of 2.5 Gb/s Operation in 0.25u CMOS

XOR outputs have pulse widths < 200 ps at 2.5 Gb/s- Complicates efforts to achieve reasonable linearity and

phase detector range

retimeddata(t)D QD Q

clk(t)

data(t)

LatchReg

Ipd

D Q

Latch

Buffer

data(t)

clk(t)

phase

error(t)

< 200 ps

phase

error(t)

56M.H. Perrott

A Combined XOR/Charge Pump Topology

Limits short pulse width signals to low impedance nodes- Fast pulses occur at source nodes of devices- Note: XOR outputs feed into “low impedance” capacitor

Combined implementation saves power and area

retimeddata(t)D QD Q

clk(t)

data(t)

LatchReg

D Q

Latch

Buffer

A

B A B

A

Ipd

Iout Iout

57M.H. Perrott

Bias Network with Simple Common-Mode Feedback

Common-mode feedback sets voltage according to voltage of top PMOS devices- Size PMOS devices appropriately for desired voltage

Achieves high impedance with compact design

retimeddata(t)D QD Q

clk(t)

data(t)

LatchReg

D Q

Latch

Buffer

IbiasIbias

Vbias

58M.H. Perrott

First Order, CT, Sigma-Delta A/D Topology

Simple design allows high speed clockingMetastability behavior improved with:- Inclusion of Amp- Slight reduction of clock frequency (i.e., 1.25 GHz)

retimeddata(t)

D QD Q

clk(t)

data(t)

LatchReg

D Q

Latch

Buffer

IbiasIbias

D Q

D Q

Ids

Amp

CintCint

2

clk2(t)

ph_err(t)

ph_err(t)

Vbias

59M.H. Perrott

Digital Loop Filter and D/A Implementation

Goal: digital implementation of analog lead/lag filterIssue: requires D/A with >> 1 MHz bandwidth, high resolution- An easier D/A implementation is preferred …

clk(t)data(t)

Hybrid

VCO

Digital

Loop Filter

Phase

-to-

Digital

retimeddata(t)

digital caps

D/A

IinVout

H(z) D/A

60M.H. Perrott

Proposed Hybrid Loop Filter Approach

Lead/Lag filter can be decomposed into two paths- Feedforward path (high bandwidth, easy in analog domain)- Integrating path (low bandwidth, hard in analog domain)

Digital domain provides a compact implementation

Iff

Iint

Vout

clk(t)data(t)

Hybrid

VCO

Hybrid

Loop Filter

Phase

-to-

Digital

retimeddata(t)

digital caps

D/A

Hint(z) D/A

Iff

Vout

61M.H. Perrott

Overall Hybrid Loop Filter Structure

Accumulator acts as digital integratorSigma-Delta D/A allows high resolution with easy implementationDecimator lowers operating speed of accumulator and D/A

Σ−Δ

D/ADecimator

Iff

clk(t)data(t)

Hybrid

VCO

Hybrid

Loop Filter

Phase

-to-

Digital

retimeddata(t)

digital caps

D/A

1 - z-1

Kint

62M.H. Perrott

Walk Through of Decimator Implementation

Consider simply running accumulator at full rate- Would need to run at GHz speeds in 0.25u CMOS

High power!Key observations- Accumulator output has higher resolution than needed by

VCO input- We do not need the LSB portion of the accumulator output

IN

OUT

clk2

ph_err-1

1

Phaseto

Digital

Σ−Δ

D/A

UnusedLSBInfo

VCOInput

clk

data

1 - z-1

Kint

ACCUM

63M.H. Perrott

Split Accumulator into LSB and MSB Sections

Key observations:- We only need one line of communication between LSB

and MSB sections (i.e., carry signals)- We only need to generate the carry out signal of the LSB

section- We can replace the LSB section with a decimator

structure and still preserve all relevant information

Cout

IN OUT

clk2

ph_err-1

1

Phaseto

Digital

UnusedLSBInfo

clk

data

ACCUM

Σ−Δ

D/AVCOInput

OUT

clk2

ACCUM

Up Down

64M.H. Perrott

First Pass at Decimator Implementation

We can implement the LSB accumulator with a ripple counter- Issue: ripple counter counts transitions- Solution: use appropriate translators to convert

between voltage levels and transitionsNext step: we have achieved an efficient LSB accumulator, but not a lower operating frequency

INOUT

Level to

Transition0

1

clk22 2 2

Ripple

Counter

INOUT

Transition

to Levelph_err

D Q

clk2

IN

OUT

D Qclk2

IN

OUT

Up

Σ−Δ

DACOUT

clk2

ACCUM

Down

VCO

Input

65M.H. Perrott

Final Decimator Architecture

Re-clock divide-by-2 stages of ripple counter at progressively lower clock frequencies- Aligns ripple counter transitions to lower frequency

clock boundariesMSB Accumulator now runs at 1/16 of the original frequency in the above example

D Q2

2

Σ−Δ

D/AVCOInput

OUT

clk16

ACCUM

IN OUT

Level to

Transition

clk2

INOUT

Transition

to Levelph_err

clk16

Decimated

Ripple Counter

De

cim

.

De

cim

.

De

cim

.

Up Down

66M.H. Perrott

Overall CDR Architecture

We have achieved:- A low power, compact, highly linear phase-to-digital structure- A low power, compact, highly configurable hybrid loop filter- Compatible with existing hybrid VCO structures achieving

excellent phase noise in 0.25u CMOS

Data In(2.5 Gb/s)

Clk16(156 MHz)

Clk2

(1.25 GHz)

Digital Integration Path

If

HoggeDet.

Σ−Δ

Vref

1

-1

RL

VCO

Analog FeedforwardPath

digitalcap

settings

A

buffer

2

Σ−Δ

D/A

Phase-to-Digital Converter

Ii

Clk(2.5 GHz)

Dec Accum

67M.H. Perrott

Die Photo

Supply Voltage- 2.5 V or 3.3 V

Typical current- 170 mA (2.5 Gb/s)

Supported data rates- 2.7 Gb/s (FEC)- 2.5 Gb/s (OC-48)- Gigabit Ethernet- 622 Mb/s (OC-12)- 155 Mb/s (OC-3)

Minimum input- 10 mV (differential)

Package size- 5mm X 5mm

68M.H. Perrott

Measured Jitter Tolerance and Transfer at 2.5 Gb/s

SONET performance specifications met at all data rates:

Jitter transfer (typ.)- Peaking < 0.03 dB

Jitter tolerance (min)- > 0.3 UIpp (> 1 MHz)

Jitter generation- 3 mUI rms (typ.)- 25 mUI pp (typ.)

Measured Jitter Tolerance and Transfer at 2.5Gb/s

0.1

1

10

100

100 1000 10000 100000 1000000 10000000 1E+08

Frequency - Hz

Jit

ter

To

lera

nce -

UI

-25

-20

-15

-10

-5

0

5

Jit

ter

Tra

nsfe

r -

dB

Jitter Tolerance Tolerance Mask

Jitter Transfer Transfer Mask

69M.H. Perrott

Measured Eye Diagrams at 2.5 Gb/s

Best Case Conditions- Input data: 2 Vp-p diff.- Pattern: PRBS 27-1- Temperature: 25° C- Jitter: 1.2 ps RMS

Worst Case Conditions- Input data: 10 mVppd- Pattern: PRBS 231-1- Temperature: 100° C- Jitter: 1.4 ps RMS

What about the digital cap settings?

--- Digital frequency acquisition example ---

71M.H. Perrott

Referenceless Frequency Acquisition

Utilize a “Forbidden Zone” to infer frequency lock- Use this information to determine digital cap settings

0o180o

270o

90o

0o180o

270o

90o

0o180o

270o

90o

Bit Error

0o 180o 0o

clk

data_in

0o 180o 0o

clk

data_in

0o 180o 0o

clk

data_in

jitter jitter edge sweep

Locked, Small Jitter Locked, Large Jitter Frequency Offset

ForbiddenZone

72M.H. Perrott

A Bit Error Detector Based on Forbidden Zone

Key idea: sample input data at two different times- Change ber_detect value if the two results are different

Implementation: achieve delayed clock with less than one buffer delay by using interpolative register

ber_resetber_detectD Q

Reg

D Q

Interp Reg

D Q

Lat

clkp

D Q D Q

clk

data_in

Reg Latch

ber_event

buffer

0o180o

270o

90o

0o 180o 0o

clk

data_in

jitter

Locked, Small Jitter

ForbiddenZone

73M.H. Perrott

Interpolative Latch

Effective latch time occurs between rising edges of input clocks (i.e., clk and clkp)- Adjustment of Ibias1/Ibias2 allows adjustment of latch time

Choose Ibias1 = Ibias2 in this application

clkp

dd

clkp

clkp

clk

Ibias1

Ibias

clkclk

out

out

Ibias2

RLRL

clkpclkp clkclk

Replica Bias

74M.H. Perrott

Combined Hogge Detector and Bit Error Detector

Sensing of bit errors adds minimal overhead to Hogge Det.- Note: Diff-to-Sngl and Sngl-to-Diff converters interface to

lower speed signals (ber_reset and ber_detect)

ber_resetber_detect

da

ta_

ho

g

be

rsig

D Q

Reg

D Q

Interp Reg

D Q

Lat

Diff-to-Sngl

Sngl-to-Diff

Bit ErrorDetector

(simplified)clkp

D Q D Q

clk

data_in data_out

ph_error

Reg

D Q D Q

Latch LatchLatch

Hogge Detector

ber_event

buffer

buffer

75M.H. Perrott

Sensing Bit Errors

For robust operation, only detect whether at least onebit error occurs within period of 2.5 MHz clock- BER Counter increases by one if the above occurs

ber_resetber_detect

da

ta_

ho

g

be

rsig

D Q

Reg

D Q

Interp Reg

D Q

Lat

Diff-to-Sngl

Sngl-to-Diff

Bit ErrorDetector

(simplified)clkp

D Q D Q

clk

data_in

ber_event

ber_reset

ber_detect

ber_event

BER counter

buffer

2.5MHz

1

76M.H. Perrott

Overall System with Referenceless Frequency Acq.

Digital cap settings are updated as shown when bit error counts exceed a threshold value

If

Ii

HoggeDet.

&BE Det.

Σ−Δ

Accum

data_in

Σ−ΔDec.

Vref

1

-1

RL

VCO

2.5 GHz

Analog Feedforward Path

Digital Integration Path

Referenceless FrequencyAcquisition Algorithm

clk_dig

digital_cap_setber_detect

ber_reset

center_accum

loss_of_lock

1024

digital capsettings

2.5 MHz

ber

buffer

2

clkpclk

Current CapSetting

Cap Settings duringFrequency Acquisition

Time

clk2 clk16

77M.H. Perrott

State Diagram for Referenceless Frequency Acq.

Fast initial check of cap setting- Allows speedy

visitation of all cap settings

- Assumes a wrong cap setting will usually yield a high BER count

Progressively slower checks of cap setting- Protects against

false selection of a cap setting

State 1Step Digital Caps

State 2

Evaluate over 16 Cycles(center_accum = 1)

State 3

Evaluate over 48 Cycles(center_accum = 0)

State 4

Evaluate over 512 Cycles

State 5

Evaluate over 512 CyclesSave VCO cap settings

reset

ber_count < 16

ber_count < 43

ber_count < 501

ber_count < 501

Fast evaluationbut sensitive tolong string of

transitionless bits

Robust against4000

transitionless bitsand BER < 1e-3

Robust against8000

transitionless bitsand BER < 2e-3

lol = 0

lol = 1

6.6 us

(336 cap settings)

209.7 us

209.7 us

19.6 us

78M.H. Perrott

Example: No Jitter, High Transition Density

BER counter goes to zero when correct digital cap setting is achieved

VCO Input

Feedforward Output

Accumulator Output (Integration Path)

BER Counter

Digital Cap Settings (Least Significant Caps)

0 UI Jitter, 1/2 Transition Density0.5

-0.50.5

-0.5

5000

020

05

00 0.2 0.4 0.6 0.8 1 1.2 1.4

Simulation Sample Number (X1000)

79M.H. Perrott

Measured Referenceless Frequency Acquisition

Change data input from 2.5 Gbit/s to 2.4 Gbit/s- In this case, frequency acquisition completes in < 2 ms

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

Time (mS)

VC

O F

req

uen

cy (

GH

z)

Measured Referenceless Frequency Acquisition

80M.H. Perrott

Example: High Jitter, Low Transition Density

BER Counter continues to have non-zero values even after correct digital cap setting is achieved- This information can be used to estimate BER of CDR

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VCO Input

Feedforward Output

Accumulator Output (Integration Path)

BER Counter

Digital Cap Settings (Least Significant Caps)

5 UI Jitter at 100 kHz, 1/6 Transition Density0.5

-0.50.2

-0.2

5000

-5000400

05

0

Simulation Sample Number (X1000)

81M.H. Perrott

Measured BER Estimation versus Actual BER

Above measured results occur across:- Worst case split lot corners- Temp: -40 to 85 degrees C, Voltage supply: 1.62 to 3.63 V

0

100

200

300

400

500

600

700

800

900

1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03

Actual BER

BE

RA

NA

(m

V)

Measured BER Estimate Vs Actual BER

82M.H. Perrott

Conclusion

Mixed-signal techniques allow high performance to be achieved with low power and compact area- Phase-to-digital converter: combined Hogge PD and First

Order Sigma-Delta A/D- Hybrid Loop Filter- All-digital frequency acquisition with minimal overhead

Measured results confirm high performance- All SONET specifications met with 1.2 ps typical rms jitter- Referenceless frequency detection with BER monitor

Mixed-signal design philosophy:Leverage both analog and digital circuits such that

their relative strengths are fully utilized