E-ELT-HIRES possible design and capabilities E. Oliva (INAF-Firenze) B. Delabre (ESO)
ESO AO Detector Controller for the E-ELT
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ESO AO Detector Controller for the E-ELT Javier Reyes, Mark Downing European Southern Observatory, ESO (http://www.eso.org) Jorge Romero University of Málaga (http://www.uma.es) Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy 10 October 2013 1 ESO AO Controller for E- ELT
description
ESO AO Detector Controller for the E-ELT. Javier Reyes , Mark Downing European Southern Observatory, ESO (http://www.eso.org) Jorge Romero University of Málaga (http://www.uma.es). Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy. The LGSD detector - PowerPoint PPT Presentation
Transcript of ESO AO Detector Controller for the E-ELT
ESO AO Detector Controller for the E-ELT
Javier Reyes, Mark DowningEuropean Southern Observatory, ESO (http://www.eso.org)
Jorge RomeroUniversity of Málaga (http://www.uma.es)
Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy10 October 2013 1ESO AO Controller for E-ELT
10 October 2013 2ESO AO Controller for E-ELT
Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy
44x42 Subapertures(NGSD)
44x42 Subapertures(NGSD)
44x42 Subapertures(NGSD)
44x42 Subapertures(NGSD)
ADCs ADCs
ADCs ADCsLVDS Serializer LVDS Serializer
LVDS Serializer LVDS Serializer
Y-a
dd
ress
ing
Y-a
dd
ress
ing
Y-a
dd
ress
ing
Y-a
dd
ress
ing
Sca
nn
ing
Sca
nn
ing
22 LVDS Outputs
22 LVDS Outputs
22 LVDS Outputs
22 LVDS Outputs
44 LVDS Outputs
44 LVDS Outputs
The LGSD detector• Large size detector: 55x45mm• 1760 x 1680 pixels• 88 x 84 SA• 20×20 pixel sub-apertures• Massive parallel architecture• 70,400 Analog-to-Digital structures• 1.4ms, 700 fps nominally
The NGSD detector• NGSD is a quarter cut out of the LGSD• 44 x42 SA• 17600 ADCs • The operation of the two imagers is the same
Top view of the NGSD package
10 October 2013 3ESO AO Controller for E-ELT
Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Sub-aperture
20x20 pixels
Row enable
Row enable
Row enable
Row enable
Gai
n D
eco
der
SA Gain
SA Gain
SA Gain
SA Gain
Y-a
ddr
essi
ng
400 ADCs9-bit
(10-bit optional)
400 ADCs9-bit
(10-bit optional)
LRC40calculator
Parallel to Serial
Sub-apertureRow #1
Sub-apertureRow #2
Sub-apertureRow #3
Sub-apertureRow #41
Sub-apertureRow #42
Sub-apertureRow #40
Logi
cFraming Control
Tming Control
Ramp
LVDS OUTPUT
Two columns of sub-apertures
800 ADCsper LVDS
Output
NGSD Pixel Output Port• Data conversion and serialization is built-in in the imagers• 22 high-speed LVDS output lines• Each LVDS output sends the data from two columns of sub-apertures
FPGA NGSD
SPI configuration
SPI configuration read-back
LVDS Master Sync
LVDS Pixel Data
LVDS Slave Sync
Pixel Control
LVDS Master Clock
Gray Counter Control
ADC Control
ADC Readout Control
LVDSDelay Line
AnalogPowerSupply
22
AnalogBias
Generation
10GbETransceiver
10GbETransceiver
10GbETransceiver
10GbETransceiver
MBS SPI DAC
MBSLinearity Test Biases
External Ramp
Ramp Control
DigitalPowerSupply
10GbETransceiver
Data Link to RTC
Control PC Interface
LVDS Slave Clock LVDS Slave Clock
External Ramp
DataReceiverFront-end
SequencerFront-end
DACExternal Ramp
Generator
DAC
Mixed Boundary Scan Bus (MBS)
Delay Control
Data Link to RTC
Data Link to RTC
Data Link to RTC
LED Control
Temperature Sensor
Moisture Sensor
Pressure Sensor
Peltier Current Sensor
Camera Synchronization
Peltier Controller
PCCommunication
Front-end
RTCCommunication
Front-end
External Ramp
NGSD Controller Architecture• Advanced FPGA• Minimal analog circuitry around it, basically DACs for bias generation• 10GbE fiber links
• Control PC• Real-Time-Computer
10 October 2013 4ESO AO Controller for E-ELT
Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy
Col
d fin
ger
open
ing
NG
SD d
etec
tor
Power supply filters
Power supply filters
Flex
PC
B
Analog power regulators
Dig
ital p
ower
regu
lato
rs
Power supply connector
Pow
er fi
lters
Signal monitors
10GbE RTCLLCU link
10GbE RTCLLCU link
10GbE RTCLLCU link
10GbE RTCLLCU link
Clock synthesis
Bias DACs
Bias DACsLDOs
FPGAConfiguration EPROM
FPGA
NG
SD
detector
Power supply filters
Power supply filters
Cold finger
opening
Flex PC
B
FPGA
Filters
Filters
Filters
FMC high-speedExpansion connector
Power supply
connector Signal monitors
Fiber transceivers
filters
Ramp generation
DAC
XCO
NGSD Prototype Controller• Xilinx Virtex-6 VLX240T FPGA• Xilinx Virtex-7 XC7VX690T• No sequencer on-chip so almost all critical clocks driven by the
FPGA• Use of Gigabit Ethernet IP core
Some Other Features• Integrated Peltier controller• Temperature, Humidity and Pressure
sensors• Over-voltage and Over-Temperature
protection• Detector power-up sequencing• Synchronization to other cameras
LVDS Pixel Link #1
SequencerSequencerFrequency
Doubler
Delay Line(Xilinx
ODELAY)
Buffer
FPGATapped
Delay Line
ExternalRamp Control200MHz
FIFOPixel
Sorting
Gray Code toBynary
SPI Control
Buffer
TXFIFO
10GbECore
ADC Ramp Control
DAC(External to FPGA)
10GbETransceiver
FiberTransceiver
PC IFFront-end
ClockSynthesis
LVDS Pixel Link #2FPGATapped
Delay LineFIFO
Pixel Sorting
Gray Code toBynary
LVDS Pixel Link #22FPGATapped
Delay LineFIFO
Pixel Sorting
Gray Code toBynary
LVDS Pixel Link #3
Combiner
LED Control
Temperature Sensor
Moisture Sensor
Pressure Sensor
Peltier Current Sensor
Peltier Controller
Camera Synchronization
LVDS Pixel Link #21
