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Equalization of Integrated Optical Photodiodes using an
Infinite Impulse Response Decision Feedback Equalizer
by
Hemesh Yasotharan
A thesis submitted in conformity with the requirementsfor the degree of Master’s of Applied Science
Graduate Department of Electrical and Computer EngineeringUniversity of Toronto
Copyright c© 2011 by Hemesh Yasotharan
Equalization of Integrated Optical Photodiodes using anInfinite Impulse Response Decision Feedback Equalizer
Hemesh Yasotharan
Master’s of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2011
Abstract
This thesis examines the challenges in creating a fully integrated optical receiver. Due to
the nature of silicon, 850nm light exhibits a poor impulse response when directed at an
on-die photodiode. Using a modified decision feedback equalizer with an infinite impulse
response filter in the feedback path allows to eliminate the long tail of post-cursor ISI that
is generated by the photodiode. Due to silicide depositions over the photodiodes, making
them opaque, the receiver was tested using an electrical cable with similar frequency roll-
off as that of a photodiode. A data rate of 3.7 Gbps was achieved and only limited by
the amount of input reflections at the transimpedance amplifier. The receiver occupies
an area of 0.23 mm2 and consumes 51.3mW.
ii
Acknowledgements
I would like to sincerely thank my supervisor, Professor Tony Chan Carusone. His men-
torship, support and enthusiasm has kept me motivated and made this thesis possible.
Thank you to Professor David Johns, Professor Glenn Gulak, and Professor Joyce
Poon for serving on my thesis examination committee.
Thanks to the Natural Sciences and Engineering Research Council of Canada (NSERC)
for providing grants. Also, thanks go out to CMC, for providing access to various CMOS
technology nodes and to Jaro Pristupa for providing CAD support.
I would also like to thank my friends and fellow graduate students, particularly in
BA5000, for their valuable knowledge and expertise. To Rocky for his help, guidance,
and discussions. To Dustin, Kentaro and Mike for their guidance. And to Alain, Andy,
Safeen and Shayan for their camaraderie.
Finally, thanks go to my parents for their love and support. I would not be where I
am today, if not for them.
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Contents
List of Figures vii
List of Tables x
List of Abbreviations xi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Silicon Photodetectors 6
2.1 Light Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Photodetector types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Junction Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Avalanche Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.3 Phototransistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.4 Spatially Modulated Light (SML) Detectors . . . . . . . . . . . . 10
2.2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Photodetector Characterization . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Theoretical Models . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Measured Photodetectors . . . . . . . . . . . . . . . . . . . . . . 15
iv
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 System Design 22
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Equalization Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Analog Equalization . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.2 Decision Feedback Equalization . . . . . . . . . . . . . . . . . . . 23
3.3 DFE Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Standard DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Infinite Impulse Response DFE . . . . . . . . . . . . . . . . . . . 26
3.4 System Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Circuit Design 33
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1 Transimpedance Amplifier . . . . . . . . . . . . . . . . . . . . . . 34
4.2.2 AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.3 Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.4 Injection Locked Oscillator . . . . . . . . . . . . . . . . . . . . . . 45
4.2.5 Infinite Impulse Response Decision Feedback Equalizer . . . . . . 50
4.2.6 Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.7 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5 Measurements 60
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.2 Circuit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.2.1 Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
v
5.2.2 Full Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.1 Optical Measurements . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.2 Electrical Measurements . . . . . . . . . . . . . . . . . . . . . . . 65
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6 Conclusion 77
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
References 81
vi
List of Figures
1.1 Optical Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Probability density function . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 CMOS photodiodes cross-section . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Diode I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 CMOS phototransistor cross-section . . . . . . . . . . . . . . . . . . . . . 10
2.5 Spatially Modulate Light detector cross-section . . . . . . . . . . . . . . 12
2.6 Intrinsic frequency response of photodiode . . . . . . . . . . . . . . . . . 15
2.7 Simulated Photodiode Impulse Response . . . . . . . . . . . . . . . . . . 16
2.8 Simulated Photodiode Eye Diagram . . . . . . . . . . . . . . . . . . . . . 17
2.9 Measured response of n+/p-sub diode . . . . . . . . . . . . . . . . . . . . 18
2.10 Measured response of npn phototransistor . . . . . . . . . . . . . . . . . 19
2.11 65nm CMOS Measurement Receiver . . . . . . . . . . . . . . . . . . . . . 20
2.12 Photodetector Testbench Die Photo . . . . . . . . . . . . . . . . . . . . . 21
3.1 Analog Equalized Impulse Response . . . . . . . . . . . . . . . . . . . . . 24
3.2 Low Pass Pulse Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 3 Tap DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Maximum achievable data rate (MADR) . . . . . . . . . . . . . . . . . . 27
3.5 Summation of exponential functions . . . . . . . . . . . . . . . . . . . . . 29
3.6 Example IIR DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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3.7 System Level DFE Simulations . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Optical Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 Shunt-feedback TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 TIA schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 TIA AC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.5 AC Coupling Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6 AC Coupling AC Response . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7 VGA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.8 Gain Cell Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.9 Input Gain Cell Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.10 Variable Gain Cell Schematic . . . . . . . . . . . . . . . . . . . . . . . . 46
4.11 VGA Bode Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.12 Clock Buffer Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.13 ILO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14 Delay Cell Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.15 90◦ Clock Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.16 VCO Tuning Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.17 ILO Transient Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.18 DFE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.19 Latch Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.20 Mux Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.21 Summer Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.22 RC Tap Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.23 DFE Simulated Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 56
4.24 Output Buffer Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.25 Output Buffer AC Response . . . . . . . . . . . . . . . . . . . . . . . . . 58
viii
5.1 Die Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 Optical Receiver Die Photo . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3 PCB Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.4 Optical Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5 Silicide Cross-section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.6 Electrical Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.7 ILO Transient Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.8 ILO Phase Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.9 2.5GHz Output Jitter Histogram . . . . . . . . . . . . . . . . . . . . . . 67
5.10 ILO RMS Jitter Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.11 ILO Duty Cycle Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.12 Coaxial Cable Channel Response . . . . . . . . . . . . . . . . . . . . . . 69
5.13 TIA Input Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.14 Electrical Input Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.15 Simulation Input Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.16 Input Reflection Simulation Results . . . . . . . . . . . . . . . . . . . . . 71
5.17 Lossless Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.18 Bathtub plot - 2.7Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.19 Bathtub plot - 3.6Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.20 Bathtub plot - 3.7Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.21 Bathtub plot - 3.8Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.22 3.7 Gb/s Equalized Eye Diagram . . . . . . . . . . . . . . . . . . . . . . 76
ix
List of Tables
1.1 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Measured 65nm CMOS Photodetectors . . . . . . . . . . . . . . . . . . . 17
3.1 IIR Filter and Gain Values . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 TIA Simulation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 DFE Parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3 Simulated Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1 Measured Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1 Table of Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
x
List of Abbreviations
BER Bit Error Rate
BJT Bipolar Junction Transistor
CDR Clock and Data Recovery
CML Current Mode Logic
CMOS Complementary Metal-Oxide Semiconductor
DAC Digital to Analog Converter
DCD Duty Cycle Distortion
DFE Decision Feedback Equalizer
ESD Electrostatic Discharge
IIR Infinite Impulse Response
ILO Injection-Locked Oscillator
ISI Inter-Symbol Interference
MADR Maximum Achievable Data Rate
PCB Printed Circuit Board
PDF Probability Density Function
PM Phase Margin
PRBS Pseudo Random Binary Sequence
QFN Quad Flat No Leads
RGC Regulated Gain Cascode
RMS Root Mean Square
xi
SCR Space Charge Region
SML Spatially Modulated Light
SOI Silicon On Insulator
TIA Transimpedance Amplifier
UI Unit Interval
VCSEL Vertical-Cavity Surface Emitting Laser
VCO Voltage-Controlled Oscillator
VGA Variable Gain Amplifier
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Chapter 1
Introduction
1.1 Motivation
There has been a slow migration of optical links from long-haul communications to short-
reach systems. Optical cables form the backbone of connections between continents and
across countries and have begun to find use in local area networks only a few kilometers
long. Server farms, and computer clusters typically use optical cabling on the order of
several meters [1]. It is predicted that the volume of active optical cables will reach 70
million by 2013 [1].
Optical links offer many advantages over their electrical counterparts. They are not
affected by crosstalk or other electrical conductor effects that degrade performance, like
the skin effect. For example, electrical links have to be shielded to minimize the effects of
crosstalk. This leads to thicker and more stiff cable, that can present hindrances in dense
configurations such as in datacenters. Optical cables on the other hand, are immune
to effects like crosstalk. Optical fibers are lightweight and recent advances have made
them more flexible with inexpensive connectors that enable the cable to support higher
bandwidths than traditional copper lines.
Currently a typical optical receiver is comprised of three parts as can be seen in
1
Chapter 1. Introduction 2
Figure 1.1 [1]. A discrete photodiode, SiGe BiCMOS trans-impedance amplifier (TIA),
and a CMOS die which has the clock and data recovery module and any data processing
block that is needed. This is obviously an expensive solution, but it allows for the
photodetector to be fabricated in a technology that is ideal for optical detection and
provides high responsivity and bandwidth. Another solution, is to bundle the TIA and
digital backend together. However, this still results in multiple dies, the photodetector
and the receiver. The cost for such a receiver can be reduced by combining all the
components onto one CMOS die.
Figure 1.1: (a) A typical optical receive path solution. (b) A fully-integrated CMOS opticalreceiver.
Short distance optical communications typically use vertical-cavity surface-emitting
lasers (VCSELs) on the transmitter side. These lasers usually have an output wavelength
of 850nm which has an average penetration depth of 18 μm in CMOS silicon. This deep
penetration results in a response that limits the data-rate a simple TIA-LA receiver can
achieve. Equalization has to be implemented if speeds greater than a gigabit per second
are desired.
Chapter 1. Introduction 3
1.2 State of the Art
The carriers generated deep in the silicon substrate slowly diffuse until they reach the
depletion region formed by a reverse-biased PN junction. This limits the data rate
of a standard receiver to several hundreds Mbps [2]. Using a process with a lightly
doped epitaxial layer allows for a wider depletion region and thus better responsivities
and photodiode capacitances. With standard supply voltages, responsivities around 0.3
A/W and capacitances on the order of 1pF have been reported. [3, 4]. Responsivity and
capacitance can be improved by using a higher reverse-bias voltage [5, 6]. This places the
diode in avalanche mode. An avalanche photodiode is extremely sensitive to light, but
prone to failures if there are any variations in either the voltage or process that causes it
to enter breakdown. The number of fingers and presence of fringing capacitances, effects
the performance of the photodiodes, thus good layout technique is crucial [4].
One way to improve the inherent speed of photodiodes is to reduce the slow diffusion
current formed from light absorption in silicon. A deep n-well can be used for this
purpose [7]. In addition the n-well/p-substrate junction can be used to shield current
from the p+/n-well photodiode [8, 9]. Another method is to use a Silicon on Insulator
(SOI) process which utilises a buried oxide layer to create better diode junctions and
shield photocurrent [10, 11, 12]. The trade-off of shielding the diffusion current is that
the DC responsivity of the photodiode drops to less than 0.1 A/W, requiring more gain
stages and power at the receiver.
Photoreceivers in BiCMOS [13] tend to perform better due to the opportunity to cre-
ate faster photodiodes. The thin base layer and lightly doped epitaxial layer forming the
collector allow for the formation of P-I-N diodes which have a fast response comprised
solely of drift current. In addition, the TIA can be designed with high gain and band-
width. This provides a good front-end for optical receivers. However, BiCMOS does not
scale down as aggressively as standard CMOS and thus lacks the ability to incorporate
fast digital blocks. This leads to a multi-chip solution which is undesirable.
Chapter 1. Introduction 4
Table 1.1: Comparison of various high performance optical receivers.
[3] [19] [18] [17]
Technology 0.18 μm 0.18 μm 0.13 μm 0.13 μmArea N/A 0.72 mm2 1.77 mm2 0.1 mm 2
Supply Voltage 1.8V 3.3/1.8 V 1.2 V 1.5 VPower Dissipation(Excluding OutputBuffer)
34 mW 168 mW 74 mW 47 mW
Data Rate 3 Gbps 5 Gbps 4.5 Gbps 8.5 GbpsBit Error Rate 10−11 10−12 10−12 10−12
Gain N/A 119 dBΩ 105dBΩ 120 dBΩ
Sensitivity-19 dBm -9.5 dBm (2.5 Gbps) -3.4 dBm -3.2 dBm
-4.5 dBm (4.25 Gbps)-3 dBm (5 Gbps)
In purely standard CMOS technology, a solution is to eliminate the slow diffusion
carriers by subtracting them from the received signal. This is done by using a spatially
modulated light (SML) detector, which consists of a series of covered and exposed pho-
todiodes that can be used to remove the the slow carriers [14, 15, 16, 17, 18, 19]. To
achieve speeds greater than a gigabit per second linear equalizers have been included in
the receive path. However, SML detectors suffer from low responsivity due to the high
amount of light rejection. In [3], a high-order linear equalizer was used to boost the
response of just a bulk photodiode. Some works use a regulated cascode input to present
a low impedance to the photodiode, but this suffers from adding additional noise to the
input of the transimpedance amplifier [17]. Table 1.1 highlights the various solutions and
their performance.
1.3 Outline
The rest of the thesis is outlined as follows. Chapter 2 provides a background on in-
tegrated photodiodes and their principles of operation. It highlights the response from
various different types of photodetectors and presents some measured results of photo-
Chapter 1. Introduction 5
diodes in 65nm CMOS. Chapter 3 contains a discussion on the receiver as a whole and
focuses on the type of equalization used and presents the principles of operation. Chapter
4 focuses on the transistor level implementation of the circuit and presents schematics
and simulation results of the various circuit blocks of the optical receiver. Chapter 5
presents the measurement results and characterization of the DFE. Chapter 6 provides
conclusions and a discussion on future avenues of research.
Chapter 2
Silicon Photodetectors
2.1 Light Detection
Light is comprised of discrete quantized packets of energy called photons. The amount
of energy in a photon is given by the following formula:
Eph =hc
λ(2.1)
where h is Planck’s constant and has a value of 6.626 · 10−34 J·s, c is the speed of light in
a vacuum, which is 3 ·108 m/s and λ is the wavelength of light. The process of converting
optical power into an electric signal is facilitated through reverse-biased diodes, hereafter
called photodiodes. When a photon of sufficient energy hits the semiconductor, it excites
an electron causing the formation of a free electron and a hole, commonly called an
electron-hole pair. The excess charge carriers in the semiconductor will begin to diffuse,
some towards the depletion region of the diode. Once this happens, it generates a net
movement of charge as the electron or hole gets swept to either the n+ or p+ region of the
diode and thus creates an electrical signal. There are several models of photodetectors
which will be explained in the following sections.
6
Chapter 2. Silicon Photodetectors 7
2.2 Photodetector types
2.2.1 Junction Photodiodes
These photodiodes are simple PN diodes. The problem with diodes in CMOS silicon is
the relatively small depth of the depletion region. The absorption of light in silicon is
dictated by the Beer-Lambert law, namely, the penetration depth of photons in silicon
follows an exponential probability density function (PDF) with the mean penetration
depth, do [1]. Thus, the PDF for the distance, x, a photon travels in silicon before being
absorbed is:
pd(x) =e−x/do
do(2.2)
The value of do for λ = 850nm in the non-CMOS semiconductors, GaAs, InP, Ge is
between 0.1 to 1μm. However, for silicon, the mean penetration depth is 18μm [1]. Figure
2.1 shows the probability density function of absorption of 850nm light in silicon. When
light is incident on silicon there is an initial fast response as the electron-hole pairs formed
in the depletion region are immediately converted to current. However the majority of the
light is absorbed below the depletion region and the excess photo-generated carriers slowly
diffuse through the substrate eventually entering the depletion region and causing current
to be generated. In other words, one pulse of light has signal energy in subsequent unit
intervals (UIs) causing a considerable amount of Inter-Symbol Interference (ISI). This
will be explained in greater detail in Chapter 3. The bandwidth of such a photodiode
has been measured to be around 2.4MHz in 0.18 μm CMOS [4, 20, 21, 22]. Figure 2.2 [1]
(a) and (b) show two examples of junction photodiodes in CMOS. The junction diode is
formed at the boundary of the n-region and the p-substrate. The p-type region is tied
to a lower voltage than the n-type region in order to form a reverse bias junction. The
junction width, W is given by the following formula:
W =
√2εSiq
NA +ND
NAND
(Vbi − VR) (2.3)
Chapter 2. Silicon Photodetectors 8
0 20 40 60 800
0.02
0.04
0.06
Depth from Surface (um)
Abs
orpt
ion
PD
F (
um−
1 )
Figure 2.1: Probability density function of the absorption of λ = 850nm light in silicon (do= 18 μm).
where NA is the doping concentration in the p-type material, ND is the doping in the
n-type material, εSi is the the permittivity of silicon, q is the charge of an electron, Vbi is
the built-in potential voltage, and VR is the reverse-bias voltage.
(a) (b)
Figure 2.2: Cross-section of CMOS photodiodes in standard CMOS: (a) n+/p-substratejunction; (b) n-well/p-substrate junction. The depletion region is indicated by the shadedregion.
Chapter 2. Silicon Photodetectors 9
2.2.2 Avalanche Photodiodes
An avalanche photodiode is a regular junction diode, described above, that is operated
in the breakdown region. Figure 2.3 shows the ideal I-V characteristics of a pn junction
diode. Normally, a photodiode is operated in the reverse bias range; an avalanche diode
is operated near the breakdown region. As the graph indicates, for a large reverse bias
voltage, the diode sources a high level of current [5, 6].
Figure 2.3: Current-Voltage characteristics of a diode.
When a photon is absorbed in the depletion region it creates an electron-hole pair.
This pair in an avalanche photodiode can then move in the depletion region and create
more electron hole-pairs, so there is some amplification of the signal. This means that
avalanche photodiodes have good responsivity, however, they also have low bandwidth
as the diffusing electron-hole pairs can wind up in the depletion regions and initiate the
current multiplication over numerous UI. Moreover, operating close to the breakdown
region is not desirable as there is a possibility that any fluctuations in voltage might
cause large DC current and overheating, resulting in permanent damage to the diode.
2.2.3 Phototransistors
A phototransistor consists of a photodiode with internal transistor-action gain. It is
generally made with a bipolar junction transistor (BJT) with the base open to light.
Chapter 2. Silicon Photodetectors 10
(a) (b)
Figure 2.4: Cross-section of a CMOS npn structure using a deep n-well. (a) The n+/p-type region can be used as a junction photodiode, with the deep n-well shielding the diode fromdiffusing substrate carries. (b) The device could alternatively be used as an npn phototransistor,where the base is not electrically contacted, and photocurrent is amplified by the BJT.
When light reaches the base-collector junction it generates a current that is amplified
by the current gain, β, of the transistor. This allows for higher responsivity but lowered
bandwidth due to a faster roll-off in the bode plot because of the addition of a transistor
in the receiver path. An npn-transistor example is shown in Figure 2.4 (b) [1], which
utilizes a deep n-well to realize the npn structure. The p-type base is not connected
electrically and a positive bias voltage is applied between the collector and emitter. Any
carriers generated deep in the substrate would not be collected using this phototransistor.
If no deep n-well is present, a pnp BJT can be formed. Due to the slow intrinsic speed
of a phototransistor, it is not an ideal photodetector for high-speed signaling.
2.2.4 Spatially Modulated Light (SML) Detectors
A modification of a junction photodiode is to alternate strips of exposed photodiodes
with covered photodiodes [4], as shown in Figure 2.5. Both the covered and uncovered
Chapter 2. Silicon Photodetectors 11
photodiodes are given the same reverse-bias voltage, and thus will have the same diode
characteristics. All the exposed photodiodes are connected in parallel as are all the cov-
ered photodiodes. When light hits the detector, the uncovered photodiodes immediately
generate drift current from absorbed photons in the depletion region. Drift current would
not be generated in the covered photodiodes as it would block the incoming light. As
noted above, photons are also absorbed deep in the substrate. When they diffuse through
the substrate, they will come in contact with both the covered and uncovered photodi-
odes. Thus, the uncovered photodiodes generate drift and diffusion current, while the
covered photodiode only generates diffusion current. Subtracting the two currents leaves
just the faster drift current [4] [1]. This is a good method for increasing the bandwidth
as it eliminates the slow diffusion current which contributes to post cursor inter-symbol
interference (ISI). The drawback is that half of the photodiode area is covered thereby
reducing the sensitivity of the photodetector. In addition, much of the photocurrent
generated in the substrate is being ignored by subtraction, which leads to a reduced re-
sponsivity. Reported responsivity’s for SML photodetectors are 0.05 A/W [19] and 0.03
A/W [4]. However, because of the elimination of the diffusion current, bandwidth can
be as high as 1 GHz [20]. Increasing the periodicity of the alternating strips, lx and
ly in Figure 2.5, will make the cancellation of the diffusion current more precise [1]. A
checkerboard pattern can be used as in [6] where 10 Gb/s operation was reported with a
reverse bias voltage of 14 V.
2.2.5 Summary
An overview of the various types of photodetectors used in CMOS was presented. Avalanche
photodiodes were used in [6] but risk overheating and thus are not pursued here. Al-
though a phototransistor has good responsivity, the relatively fast roll-off and low band-
width makes it ill-suited to high speed detection. SML detectors have been used in
[19, 15, 16, 17, 18] and although they have a fast response, the input sensitivities have
Chapter 2. Silicon Photodetectors 12
Figure 2.5: Cross-section of a CMOS SML photodetector. The depletion region is indicatedby the shaded region.
been poor, at around -3 dBm. Thus, a junction transistor was chosen because of its
higher responsivity and low frequency roll-off of -5 dB/decade. Compared to an SML
detector, a junction photodiode should introduce a 3 dB improvement because half of the
optical power is not rejected. Circuit techniques can be used to equalize the low band-
width of a junction diode. Therefore, it provides a good balance between responsivity
and bandwidth.
2.3 Photodetector Characterization
2.3.1 Theoretical Models
The total amount of current generated from the nwell/P-substrate junction is comprised
of the drift current in the depletion region and the diffusion current in the n-well and
p-substrate, as given in the following equation:
Jtotal = Jdrift + Jnwell,diff + Jp−sub,diff (2.4)
In order to calculate the current response, each individual component must be ana-
Chapter 2. Silicon Photodetectors 13
lyzed and summed together. The drift current is the current generated from the space
charge region (SCR) and is assumed to be frequency independent. It is given by the
following equation [20]:
Jdrift(jw) = Φ0(jw)qαLSCRAI
AT
(2.5)
Φ0(jw) =p
hc/λ(2.6)
where Φ0 is the incident optical flux, p the incident optical power, α the absorption
constant of light in silicon for a particular wavelength, LSCR the width of the depletion
region, AI the area below the immediate diffusion or well contact, and AT the total
detector area.
The diffusion in the n-well is calculated based on the minority carrier profile as an
initial condition for solving the diffusion equations. Assuming a substrate of infinite
depth, which is the worst case, the current density profile at the lower edge of the space
charge region is a function of frequency as follows [20]:
Jp−sub,diff = Φ0(jw)qαLne−αlz
1√1 + jwτn + αLn
(2.7)
Ln =√
Dnτn (2.8)
where Ln is the diffusion length of the minority carrier electrons in the p-region, Dn the
diffusion coefficient, τn the carrier lifetime, and lz the distance between the surface and
the bottom of the space charge region.
The diffusion in the n-well is based on the minority carrier profile in the n-well, which
is the hole profile. The equation is based on a carrier generation function g(t), that is the
product of two Fourier series, one is a square wave in the x-direction (with an index n),
the other is a square wave in the y direction (with an index m). The total contributed
current can be expressed as the sum of the contributions of each indice, m and n [20].
Chapter 2. Silicon Photodetectors 14
The equation is shown below:
Jnwell,diff (jw) = Φ0(jw)qL2p
l
32
π2
(1− e−αlz)
lz
∞∑n=1
∞∑m=1
2lzly
(1
2n−1
)2+ ly
2lz
(1
2m−1
)2(
(2n−1)πLp
2lz
)2
+(
(2m−1)πLp
ly
)2
+ 1 + jwτp
(2.9)
Lp =√
Dpτp (2.10)
where Lp is the diffusion length of the minority carrier holes in the n-well, Dp the diffusion
coefficient, τp the carrier lifetime, ly the width of the n-well, and l the periodicity of the
structure.
It should be noted that temperature would have an effect on the carrier mobility and
thus the value of Lp and Ln. However, it can be seen in both equation 2.7 and equation
2.9 that the effect of Ln and Lp is negligible, due to being in both the numerator and
denominator. The greatest contributing factor to the current density is the depth and
height of the depletion region.
Figure 2.6 shows the calculated frequency response of a photodiode based on the
equations above. Note that the bandwidth of the response is around 2 MHz. The exact
value can be calculated by manipulating the equations above and assuming that the
dominant factor affecting current is the p-substrate diffusion. The equation is as follows:
f3dB =(4−
√7) (αLn + 1)2
2πτn(2.11)
Using this equation, gives a 3dB frequency of 2.42 MHz for 0.18 μm CMOS assuming
a minority carrier lifetime of 2.5 × 10−3s and a diffusion coefficient of 38.8 cm2/s as in
[20]. The other item of note in Figure 2.6 is that the roll-off of the photodiode response
is around -5 dB/decade over a couple of decades. From the frequency response, the
photodetector’s impulse response can be found. Figure 2.7 shows the associated response
for a 5 Gb/s (200 ps wide) pulse. Each square box on the plot represents a 1 UI-spaced
sample. The pulse response has over 50 UIs of signal power and creates a significant
Chapter 2. Silicon Photodetectors 15
102
104
106
108
1010
−25
−20
−15
−10
−5
0
5
Frequency [Hz]
AC
Res
pons
e [d
B]
Figure 2.6: Intrinsic frequency response of an n-well/p-substrate junction photodiode in stan-dard 0.18 μm CMOS.
amount of ISI. Figure 2.8 shows a simulated eye diagram at 5 Gb/s with the channel set
as the photodiode response and a pole at 3 GHz intended to simulate the response of a
TIA. The ISI introduced by the photodiode causes the output eye to become completely
closed. This presents a challenge that must be overcome in order to create an optical
receiver working at 5 Gb/s.
2.3.2 Measured Photodetectors
A chip was fabricated with different photodiode structures in the ST 65nm technology
node. The chip consisted of various photodetectors with a simple linear receiver shown
in Figure 2.11 (a). The associated transistor level schematic can be seen in Figure
2.11 (b). It consisted of a TIA, an amplifier and a 50Ω buffer. The design was made
for simplicity and is not optimized for low power. A die photo of the completed chip
is shown in Figure 2.12. Two types of photodiodes were tested. A simple n+ p-sub
photodiode as shown in Figure 2.2 (a) and a phototransistor shown in Figure 2.4. Both
photodetectors were 60 μm x 60 μm. All measurements were made with a 1.3 V
Chapter 2. Silicon Photodetectors 16
0 0.5 1 1.5 2 2.5 3−0.2
0
0.2
0.4
0.6
0.8
1
1.2
Time [ns]
Nor
mal
ized
Impu
lse
Res
pons
e
Figure 2.7: Simulated Impulse Response of a 5 Gb/s pulse through a CMOS photodiode basedon equations in section 2.3.1. Each square box represents one UI. There is a long tail due toslow roll-off and low bandwidth. This causes significant ISI.
supply which resulted in a reverse bias voltage of 670mV on the diodes. In order to
measure the photodiode accurately, an electrical test of the amplifier was performed to
de-embed the photodetector measurements. A DC transimpedance of 1 kΩ and a 3dB
bandwidth of 2 GHz was measured. This bandwidth far exceeds the expected bandwidth
of the photodetectors, and thus a flat response was assumed when plotting the frequency
response.
The measurement results from the n+/p-substrate photodetector is shown in Figure
2.9. A DC responsivity of 0.03 A/W, a 3-dB bandwidth of 2.5MHz and a roll off of -5
dB/decade were observed. The low responsivity, compared to expected value of at least
0.1 A/W based on the previous equations, can be attributed to silicide placed on the
n+ region which has a low optical transmission coefficient and will be explained in more
detail in Chapter 5. Measurements of the npn phototransistor (n+/p-tub/deep n-well) in
Chapter 2. Silicon Photodetectors 17
−1 −0.5 0 0.5 1−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
UI
Inpu
t Eye
Dia
gram
(V
)
Figure 2.8: Simulated Eye Diagram at 5 Gb/s of a PRBS 231−1 signal through a photodiode.
Table 2.1: Summary of 65nm CMOS photodetector measurements.
Photodetector Responsivity [A/W] 3-dB Bandwidth[MHz] Roll off
n+/p-substratephotodiode
0.03 2.5 -5 dB/dec
n+/p-tub/deep n-well phototransis-tor
0.34 0.15 -9 dB/dec
65nm CMOS is shown in Figure 2.10. It has a high DC responsivity of 0.34 A/W which
is comparable with state-of-the-art CMOS photodetectors. However, it features a 3dB
bandwidth of only 150kHz and a roll off of 9 dB/decade. Table 2.1 provides a summary of
the measurement results. These results qualitatively agree with the background presented
earlier in the chapter.
Chapter 2. Silicon Photodetectors 18
Figure 2.9: Characterization of the response of a n+/p-substrate photodiode in 65nm CMOS(least square fit).
2.4 Summary
This chapter has presented an overview of CMOS photodiode operation. The process by
which an incident photon gets converted to a current was explained. The different types
photodetectors were outlined and the advantages and disadvantages of each were stated.
An in-depth analysis into junction diodes was presented, characterizing its response. An
array of photodetectors were fabricated in 65nm ST CMOS to measure their response.
The measured results qualitatively agree with the theoretical models. Thus, in order to
achieve good input sensitivity, a junction photodiode must be used. The disadvantage
is the small bandwidth and low roll-off causes significant ISI over a long post-cursor
interval. This provides an interesting challenge in circuit design and a possible solution
will be described in the upcoming chapters.
Chapter 2. Silicon Photodetectors 19
Figure 2.10: Characterization of the response of an n+/p-tub/n-well npn phototransistor in65nm CMOS.
Chapter 2. Silicon Photodetectors 20
Vout
Photodetector
TIA
Amplifiers
Output Buffer
50Ω
50ΩAc
(a)
100 x 1 um / 0.06 um
Vb2 100 x 1 um / 0.06 um
Vb1100 x 1 um / 0.06 um
Vi
250
13mA 4mA
120 x 1 um / 0.06 um
VDD
Vb3
120 x 1 um / 0.12 um
Ω
Vb4
31mA
210 x 1 um / 0.06 um
120 x 1 um / 0.06 um
50Ω
Vo
8mA
180 x 1 um / 0.09 um
160 x 1 um / 0.06 um
11mA
(b)
Figure 2.11: 65nm CMOS photodetector measurement circuitry: (a) block diagram; (b)schematic.
Chapter 2. Silicon Photodetectors 21
Figure 2.12: CMOS photodetector array testbench in a standard 65m ST CMOS process.
Chapter 3
System Design
3.1 Introduction
The low bandwidth and long roll-off of the response of an optical photodiode necessitates
the use of equalization to achieve high speed communications. This chapter will provide
an overview of two forms of equalization: linear equalization that relies of frequency
boosting and digital feedback equalization. The various pros and cons of each will be
investigated and the design of the proposed equalization scheme will be discussed.
3.2 Equalization Architectures
3.2.1 Analog Equalization
The frequency response of a photodiode generally has a very low bandwidth of around
2 to 4 MHz as explained previously. In addition, it rolls off at around -5 dB per decade
[4, 20, 3]. An analog equalizer modifies the system’s frequency response by adding peaking
so as to extend the bandwidth. This peaking is achieved through the adding of poles and
zeros. By careful placing of zeros and poles, one can form a variety of different responses.
Adding this complex response into the receiver chain causes the overall bandwidth of the
22
Chapter 3. System Design 23
system to be extended and thus enables the transmission of higher data rates.
In [3], the photodiode’s -5dB per decade response was compensated for by a +5
dB per decade response to get a relatively flat overall response in order to equalize a
photoreceiver to 3 Gb/s. Using an analog equalizer to perform channel correction would
lead to a multi pole-zero system, which is not only complex, but as is common with analog
equalizers, would increase the noise power. Figure 3.1 shows the impulse response both
before equalization and after an analog equalizer with three zeros of a bulk photodetector
operating at 5 Gb/s is used. It was plotted using the equations outlined in Chapter 2
and with Dn = 38.8 cm2/s, τn = 2.5 ms, μn = 1500 cm2/V/s, Dp = 10 cm2/s, and
τp = 0.4 ms as in [20]. Taking the sum of the ISI at each UI for both the equalized
photodiode and unequalized photodiodes provides a metric for comparison. In 10 ns,
the photodiode has a combined post-cursor ISI of 107 while the equalized photodiode
has a combined post-cursor ISI of 59. The amount of ISI is still significant but is greatly
reduced compared to just a plain photodiode. This allows for a data rate in the low Gb/s
range. It was determined that because of the poor bandwidth and unorthodox roll-off, an
analog equalizer would not be best solution because greater complexity would be needed
to increase the data rate to 5 Gb/s.
3.2.2 Decision Feedback Equalization
Traditionally, decision feedback equalizers (DFE) have been used in systems where post-
cursor ISI is a problem. The benefit of using a DFE is that it does not amplify noise power.
However, it does eliminate the signal power in the post-cursor taps. Another disadvantage
with a DFE is that it requires a clock signal that is aligned with the incoming data. A
DFE operates by making a guess as to the current bit and then feeding a delayed, scaled
version of the signal to cancel out the ISI that was in that bit from interfering with the
incoming data [23, 24]. Generally, the more taps a DFE has the more post-cursor ISI it
is able to eliminate and as a result higher data rates can be transmitted over the channel.
Chapter 3. System Design 24
0 0.5 1 1.5 2 2.5 3−0.2
0
0.2
0.4
0.6
0.8
1
1.2
Time [ns]
Nor
mal
ized
Impu
lse
Res
pons
e Unequalized PhotodiodeEqualized Photodiode
Figure 3.1: Simulation of the impulse response at 5 Gb/s both without equalization and witha linear equalizer with three zeros.
As an example, look at Figure 3.2 for the response of a 5 Gb/s impulse in a simple low
pass filter with one pole and a 3-dB bandwidth of 1.25 GHz. Each square box on the
plot denotes a 1 UI-spaced sample. Thus the three square boxes after the peak indicate
that the channel has 3 taps of post cursor ISI. A simple 3 tap DFE shown in Figure 3.3
can eliminate this ISI and result in ISI-free transmission.
Looking back at Figure 2.7, it can be seen that most of distortions in the pulse
response are post-cursor ISI. Since a DFE is able to handle post-cursor ISI nicely, it was
chosen as the equalization that would be used.
3.3 DFE Analysis
3.3.1 Standard DFE
Equalization of an optical receiver with a CMOS integrated photodetector is impractical
using an ordinary DFE due to the long post-cursor ISI tail that is present. To illustrate
Chapter 3. System Design 25
0 0.5 1 1.5 2 2.5 3−0.2
0
0.2
0.4
0.6
0.8
1
1.2
Time [ns]
Nor
mal
ized
Impu
lse
Res
pons
e
Figure 3.2: Simulated pulse response of a low pass channel that contains 3 UIs of post-cursorISI.
Retimed Data
ISI−FreeNode
T1
T3
T2
FF FF FF
clk
Data
Figure 3.3: Block diagram of a full rate DFE with 3 feedback taps.
Chapter 3. System Design 26
this, the maximum avchievable data rate (MADR) is plotted in Figure 3.4 versus the
number of DFE taps. These graphs were made by taking the channels (both with just a
photodiode in Figure 3.4 (a) and with a photodiode and a linear equalizer in Figure 3.4
(b)) and attaching a DFE to them. The algorithm used was as follows: A linear equalizer
with three zeros was chosen so that the overall frequency response was maximally flat.
For a given data rate, a zero-forcing algorithm was used to pick tap settings such that
the amount of ISI present at a particular UI is zero. Then, for a given clock phase, a
27− 1 pattern was run twice through the system and the number of errors were counted.
The clock phase was then incremented by 0.1UI and the sequence was rerun, counting
errors with the same tap weights. This was repeated until the entire clock phase had
been swept. If error-free operation was achieved over a timing window of 0.7UI, the data
rate was increased 1. This repeats until the error-free timing window was 0.6UI or less.
The highest data rate with a 0.7UI timing margin is considered the MADR. Then the
number of taps is increased by 1 and the whole simulation is repeated.
With an analog equalizer before the DFE, data rates of 5-10 Gb/s are achievable with a
DFE having 4-8 taps, a relatively complex and power-hungry receiver architecture. With
just a photodiode, more than 10 taps would be needed just to reach 250Mbps. Thus, a
standard DFE is not the best means by which to equalize a photodiode.
3.3.2 Infinite Impulse Response DFE
The key to equalizing the photodiode response in silicon is to eliminate the long tail
of post-cursor ISI formed by the diffusion of carriers in the substrate. Many taps are
required to do this, so the power consumption needed is not practical. However in
[25], a DFE was proposed which uses an Infinite Impulse Response (IIR) filter in order
to mimic the exponential tail of a wireline channel. In [25], the first tap was normal
1This simulation only accounts for 0.3UI peak-to-peak of deterministic jitter. Some of the remaining0.7UI will be accounted for by random jitter, however this work targets inexpensive short-reach opticalcommunications and random jitter and channel impairments are presumed to be small.
Chapter 3. System Design 27
0 2 4 6 8 100
0.05
0.1
0.15
0.2
0.25
Number of Taps
MA
DR
[Gbp
s]
(a)
0 2 4 6 8 100
2
4
6
8
10
12
Number of Taps
MA
DR
[Gbp
s]
(b)
Figure 3.4: (a) MADR for a n-well/p-substrate photodiode followed by a DFE. (b) MADRfor a n-well/p-substrate photodiode followed by an analog equalizer and DFE. The photodiodewas modeled using the equations introduced in Chapter 2.
and their second tap incorporated a continuous-time RC low-pass filter. This creates
an exponential response modeled by e−t
RC . It was also shown in [25] that the channel
response from 20mm Si carrier channels are well modeled by a decaying exponential pulse
response for 2UI or more after the arrival of the pulse peak.
Chapter 3. System Design 28
Unfortunately the pulse response from the photodiode response does not fit a simple
exponential tail. In order to emulate a photodiode response several exponentials are
needed. Figure 3.5 shows that with three exponential functions, a more complex expo-
nential function can be generated. Thus to cancel out the response from a photodiode,
a low amplitude slow roll-off is needed along with higher amplitude fast responses. As
can be seen in the figure, a very low-frequency RC pole is needed to cancel the pulse
response’s long tail. The other two poles are used to simulate the immediate post-cursor
ISI. The most critical pole is the long tail pole, as any mismatch in this roll-off would
affect numerous subsequent bits.
In summary, reconstructed data fed through the filter undergoes a similar pulse re-
sponse as the actual integrated photodiode channel except delayed by 1 UI. This allows
for a subtraction to be performed to cancel out all the ISI generated by the channel. An
example of how such a DFE might look can be seen in Figure 3.6.
The advantage that this offers is that once the filter is fixed for a channel, it is
independent of data rate. In a traditional DFE, when the data rate changes, the pulse
response changes and hence the value of the DFE taps must also change. In the proposed
system, the IIR filter in the DFE models the channel. When the data rate increases, the
pulse response from the photodiode changes, but this change is matched by the output
of the IIR filter. This allows for one configuration setting to be used across all data rates
without having to readjust any of the DFE coefficients or pole values. In addition, only
one flip-flop is needed as opposed to several if a standard DFE was used. This offers
a huge reduction in the power needed to equalize all the post-cursor ISI found when
employing a n-well/p-substrate photodiode.
Chapter 3. System Design 29
0 0.5 1 1.5 2 2.5 3
x 10−9
0
0.1
0.2
0.3
0.4
0.5
X
Y
(a)
0 0.5 1 1.5 2 2.5 3
x 10−9
0
0.2
0.4
0.6
0.8
X
Y
(b)
Figure 3.5: A complex exponential function can be approximated by a summation of simpleexponentials (a). In this figure, the line with no markers (b) is the sum of the three exponentialshown in (a).
3.4 System Simulation
The system was developed in Matlab to ensure that it was theoretically sound. A channel
was constructed using the equations in Chapter 2. A Matlab fitting algorithm (ratio-
nalfit()) was then applied to get a pole zero approximation of the channel from the
calculated frequency response. This was then made into a transfer function and added
into the Simulink simulation. A clock source was used to drive both the PRBS generator
and the decision feedback equalizer. The output of the PRBS generator went through
Chapter 3. System Design 30
Retimed Data
ISI−FreeNode
T1
clk
Data FF
Figure 3.6: An example of what a possible Infinite Impulse Response DFE would look like.
the channel, which had the estimated dominant pole of the analog front-end included in
its model but no analog linear equalizer. The output of the channel was then fed to a
half-rate implementation of the IIR DFE [26], the output of which was then mux-ed back
together and fed to a BERT. In Matlab, with a good approximation of the channel in
the IIR filter, successful error free operation was possible at any data rate. Figure 3.7(a)
shows the simulated input eye at 5 Gbps, 231− 1 PRBS, to the DFE using the equations
detailed in the previous chapter. Figure 3.7(b) shows the eye diagram at the node after
the summer and before the latch. This node is referred to as the ISI-Free node as shown
in Figure 3.6. As can be seen, the ISI is eliminated and a clean eye can then be latched
to form the retimed data.
It was found that in order to equalize a standard nwell/p-substrate photodetector, as
calculated in Chapter 2, three poles were needed. A pole at 16 MHz with a gain of 0.45
was needed to simulate the long tails common in photodiode pulse responses. Two other
poles at 458 MHz and 468 MHz with gains of 0.07 and 0.17 respectively, were used to
form the initial drop off after the peak. Table 3.1 summarizes these values. Together,
the 3 poles form an approximation of the pulse response and can be used as the IIR filter
Chapter 3. System Design 31
−1 −0.5 0 0.5 1−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
UI
Inpu
t Eye
Dia
gram
(V
)
(a)
−1 −0.5 0 0.5 1−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
UI
ISI−
Fre
e E
ye D
iagr
am (
V)
(b)
Figure 3.7: Eye Diagram of (a) input signal to the DFE at 5 Gb/s and (b) signal after thesummer in the DFE at 5 Gb/s for a PRBS 231 − 1.
Chapter 3. System Design 32
Table 3.1: Values of the pole locations and gain of the IIR filter.
Pole location Gain
Pole 1 16 MHz 0.45Pole 2 458 MHz 0.07Pole 3 468 MHz 0.17
in the DFE to equalize a monolithic integrated CMOS photodiode.
3.5 Summary
This chapter has presented a discussion on two general types of equalization schemes
that can be used to improve the data rate of optical receivers. At data rates around
5 Gb/s, analog equalization is complex and introduces significant noise enhancement.
Since all the ISI from an integrated photodiode is post-cursor ISI, it is natural to consider
decision feedback equalization. Due to the overwhelming number of post-cursor ISI terms
present, a standard DFE would prove too power hungry. An infinite impulse response
DFE was proposed whose filter combines several exponential impulse responses to match
the channel’s impulse response. This DFE can equalize many post-cursor ISI terms with
one digital delay (flip-flop). An additional benefit is that once the coefficients and pole
values are set, the taps do not need to be readjusted when the data rate is changed.
Simulations show that this is a viable equalization scheme for optical receivers.
Chapter 4
Circuit Design
4.1 Introduction
This chapter presents the design of an optical receiver which performs channel equaliza-
tion through the use of an Infinite Impulse Response (IIR) Decision Feedback Equalizer
(DFE) as described in the previous chapter. The technology node used for the design
was IBM 0.13 μm CMOS with eight metal layers and an ft,max of 90 GHz.
The half-rate DFE contains three poles in the IIR filter and has a total of 6 parameters,
three for the pole location and three for the gain through each branch in the filter. The
receiver was designed to support an input sensitivity of -10dBm, operate at 5Gb/s and
consume 50mW of power. This compares favourably with the prior art, particularly with
respect to sensitivity.
4.2 Receiver Architecture
A block diagram of the proposed receiver is shown in Figure 4.1. The receiver is composed
of a covered and exposed photodiode to provide a balanced load for the differential Trans-
33
Chapter 4. Circuit Design 34
Impedance Amplifier (TIA) that follows1. AC coupling is used to eliminate the differences
in DC common mode that arise between the two differential signals due to the single-
ended input excitation. A Variable Gain Amplifier (VGA) follows to ensure that the input
signal power to the DFE is constant regardless of the amount of optical power incident
to the system. An IIR half-rate DFE then follows the VGA with the clock provided by
an injection-locked oscillator (ILO). The phase of the clock is manually tuned off-chip by
varying the ILO’s resonant frequency [27]. For testing, an output buffer matched to 50
Ω was used to drive the signal off-chip.
Figure 4.1: Proposed optical receiver block diagram.
4.2.1 Transimpedance Amplifier
The TIA is one of the most important blocks in the receive path. The input signal to it
is in the order of tens of micro-amperes, making the TIA performance a critical factor
in the overall system design. The trade-offs between transimpedance gain, bandwidth,
noise and stability will be discussed.
1This is not a spatially-modulated structure. The entire fiber cross-section is aligned with the exposedphotodiode. The covered photodiode provides only a matched input capacitance to the differential-inputTIA.
Chapter 4. Circuit Design 35
Transimpedance Gain
In a shunt-shunt feedback TIA, the transimpedance gain is determined by the resistor
that is in the feedback path. Having a large gain is beneficial because it reduces the
amount of input referred current noise. In addition a large gain would ease the noise
specifications of any subsequent blocks in the receive path.
Transimpedance Bandwidth
The transimpedance bandwidth is dominated by the large input pole formed by the
photodiode capacitance and feedback resistor. Thus there is a trade-off between the
bandwidth and gain of the TIA. A small bandwidth would reduce the eye-opening and
create ISI. Whereas a large bandwidth will increase the integrated noise and reduce the
input sensitivity of the receiver. A value of 0.6· Datarate was chosen. For a data rate of
5 Gb/s, a TIA bandwidth of 3 GHz was targeted.
Noise
As touched upon above, an important specification is the amount of input-referred current
noise present. The noise contributed by the TIA decreases with a larger feedback resistor
based on the following equation:
In,in =Vn,out
RT
(4.1)
Thus, increasing the value of the feedback resistor will allow for better input sensitivity.
Stability
Like any system in feedback, the stability of the loop must be ensured. If the phase
margin is too low, there could be significant overshoot in the time domain response.
However, too much phase margin would result in a long settling time. In this work, a
phase margin of 60 degrees is targeted.
Chapter 4. Circuit Design 36
Design
A shunt-feedback TIA was used as the front-end in the optical receiver as opposed to a
regulated gain cascode (RGC) [17]. An RGC stage can provide a low input resistance
and, hence, a higher frequency input pole together with the big capacitance normally
found in a photodiode. However since RGC topologies include a transistor in series with
the photodiode, they increase input noise. This decrease in sensitivity is undesirable and
hence an RGC TIA was not used.
Figure 4.2 shows the basic topology of a shunt feedback TIA where Iin models the
current generated by the photodiode, Cin is the sum of capacitances of the photodiode
(dominant) and the input of the core amplifier. If the core amplifier were ideal, then all
(s)cA
RF
Cin
Iinvo
Figure 4.2: Basic shunt-feedback Trans-impedance amplifier.
the current generated by the photodiode would flow through the resistor RF , creating a
voltage signal at vo. Since the core amplifier is not ideal, the trans-impedance gain, RT ,
is given by [28]:
RT ≈ RFAo
1 + Ao
(4.2)
Assuming that the gain, AC , is larger than unity the bandwidth of the TIA can be written
as follows:
BW3dB =1 + Ao
2πRFCin
(4.3)
Chapter 4. Circuit Design 37
Thus the bandwidth is determined by the dominant pole multiplied by one plus the core
amplifier gain. Another way of looking at this, is to calculate the input resistance of the
closed-loop system. Feedback reduces the input resistance by a factor of one plus the
gain. Thus the input resistance is given by:
Rin =RF
1 + Ao
(4.4)
It’s clearly beneficial to have a core amplifier with high gain to improve the bandwidth
of the TIA. However the phase margin of the system restricts the maximum gain. The
core amplifier A(s), can have multiple stages in order to increase the DC gain as in [18].
Looking at Figure 4.2, the loop gain of the TIA can be expressed as:
LG = A(s)1
1 + sRFCin
(4.5)
The system’s dominant pole is the input pole of RF and Cin which contributes 90◦ to
the phase. Thus, the phase margin of the system is 90 degrees minus the contributions
of the internal poles of the amplifier.
PM = 90◦ −N∑i=1
tan−1
(ωt
ωpi
)(4.6)
where assuming Ao � 1 and ωpi � ωdominant,
ωt ≈ Ao
RFCin
(4.7)
In order to remain stable, the dominant pole must either be lowered or the internal poles
of the core amplifier must be increased. Increasing the internal poles requires a drop in
the gain of each amplifier stage. In order to keep the bandwidth of the TIA constant,
the number of stages and hence the gain can be increased. This increases the power
consumption and reduces the amount of phase margin. Lowering the dominant pole is
achieved through increasing the feedback resistor. This reduces the amount of input rms
current noise and increases the transimpedance gain, but lowers the bandwidth of the
TIA. These numerous tradeoffs have to be juggled in TIA design.
Chapter 4. Circuit Design 38
Based on [4], the expected responsivity of a 0.13μm photodiode is 0.3 A/W. As
mentioned above, the targeted input sensitivity of the receiver is -10 dBm. Therefore,
the expected current generated by the photodiode is 30 μA at most. The schematic of
the core amplifier is shown in Figure 4.3. The transistors sizes are specified as Nf x
Wf . Nf denotes the the number of finger and Wf , the finger width. The length of the
transistors, L, is specified in the schematic. The feedback resistors surrounding the core
amplifier is 300 Ω.
RF = 300Ω (4.8)
3.87 mA 3.87 mA
200 Ω
200
Vinp
Vinn
VoutpVoutn
VDD
VDD
35 x 2 um 35 x 2 um
40 x 2 um
40 x 2 um 40 x 2 um
40 x 2 um
L=0.12 um
Ω
Figure 4.3: Schematic of the Trans-impedance amplifier
The core amplifier consists of two cascaded differential common source amplifiers. The
bandwidth of the core amplifier is increased through the use of negative-Miller capacitance
between the two differential pairs [29]. Instead of a traditional capacitor to serve as the
negative-Miller capacitance. An NMOS transistor that is sized the same as the input
Chapter 4. Circuit Design 39
pair of the second stage was used. The gate and source of the transistor was shorted
so the negative-Miller capacitance is the Cgd of this transistor, which should track any
variations in the Cgd of the input pair.
An initial estimation given by Cadence for the capacitance of the photodiode with
0.6V of reverse bias voltage was approximately 1.7 pF. In order to be conservative, a
capacitance of 2 pF was assumed. Due to this large capacitance the feedback resistors
had to be lowered in order to push the input and dominant pole out to achieve a target
TIA bandwidth of 3 GHz. Simulations of this circuit will be presented below.
Simulation Results
106
107
108
109
1010
1011
0
10
20
30
40
50
60
Frequency [Hz]
Tra
nsim
peda
nce
Gai
n [d
B O
hm]
Figure 4.4: AC response of the Trans-impedance amplifier
Figure 4.4 shows the AC response of the Transimpedance amplifier. Since the feedback
resistor is 300Ω, the transimpedance gain was expected to be 49.5 dBΩ. The actual gain
is 49.4dBΩ, due to the finite gain in the core amplifier. The response is flat through the
pass band and the bandwidth of the TIA was simulated to be 2.9 GHz. This is close to the
design goal of 3 GHz. Since the system involves feedback, an important characterization
Chapter 4. Circuit Design 40
Table 4.1: Summary of the simulation results of the transimpedance amplifier.
Specification Value
Gain 49.37 dBΩBandwidth 2.9 GHz
Phase Margin 68.8◦
Input Referred Current Noise 2.8 μArmsInput Resistance 9 Ω
Power 9.3 mW
metric is the phase margin which tests stability. The loop was broken and the phase
margin of the loop gain was simulated to be equal to 69◦. The input resistance of
the TIA was 9 Ω and the input referred current noise was 2.8 μA. A summary of the
simulation results for the TIA is shown in Table 4.1.
This TIA has more noise than that in [18](4-stage core amplifier) and [19](same
topology). The aforementioned TIAs were designed for a spatially modulated photodi-
ode which has about half the capacitance of a bulk photodiode as used in this work.
In addition this work aimed to be low power which restricted the amount of DC gain
available. Thus, according to equation 4.3, in order to keep the 3-dB bandwidth similar
to the other works to allow for 5 Gbps data, the feedback resistor had to be reduced.
The reduction if RF increases the amount of noise present in the TIA. The size of the
feedback resistor in this work is 16 times smaller than that in both [18] and [19].
4.2.2 AC Coupling
An AC coupling block is placed after the TIA. This block is necessary due to the nature
of the output signal from the TIA. The TIA is differential and one end is connected to a
photodiode which will be sending pulses of current. Because the photodiode is either on
or off, the output of the positive terminal in the TIA is either at V1 or V2. However, the
other input to the TIA is a dummy photodiode that is covered by metal. This photodiode
will never be on and thus at the negative output terminal of the TIA, the voltage is always
Chapter 4. Circuit Design 41
at V1. Thus there is a difference in the common modes of the two terminals. AC coupling
serves to force the common mode voltage of both terminals to be the same.
The schematic of the AC coupling channel is shown in Figure 4.5. The values of RAC
and CAC were chosen so that for a 231 − 1 PRBS signal at 5 Gb/s, the lower frequency
content is passed.
2.4 pF
bV
2.5 MΩACC
RAC
Vin Vout
bV
Figure 4.5: Schematic of the AC coupling network.
Simulation Results
Figure 4.6 shows the Bode response of both the TIA and AC coupling network. The
pass-band is between 26.5 kHz and 2.9 GHz.
4.2.3 Variable Gain Amplifier
The purpose of the Variable Gain Amplifier (VGA) is to ensure that regardless of the
amount of signal power incident on the photodiode, the peak-to-peak signal power enter-
ing the DFE is constant. Thus if the input optical power changes, for example, a shift
in alignment between the fiber and photodiode, the DFE tap weights do not have to be
modified. The VGA also allows for a wide range of input power (-10dBm to -3 dBm) to
be received without a change in the DFE, making testing easier.
Chapter 4. Circuit Design 42
103
104
105
106
107
108
109
1010
1011
0
10
20
30
40
50
60
Frequency [Hz]
Tra
nsim
peda
nce
Gai
n [d
B O
hm]
Figure 4.6: AC response of the AC coupling network along with the TIA.
Specifications
The feedback resistor, RF , on the TIA is 300Ω. Since the DC responsivity of the photo-
diode was estimated to be 0.3 A/W, at -3 dBm and -10 dBm input, the voltage signal
from the output would be between 45 mV and 9 mV, respectively. The input voltage
swing to the DFE was set to be 600 mV, therefore a gain between 22.5 dB and 36.5 dB
is needed.
In addition, the bandwidth of the VGA must not affect the maximum data rate of
the system, thus a bandwidth of more than 3 GHz is preferable. Due to the large gain in
the VGA, any small input voltage offset would get amplified and result in a large offset
at the output of the VGA. Therefore offset cancellation must be used to ensure that the
voltage at the output is balanced with as small of an offset as possible.
Chapter 4. Circuit Design 43
Design
The VGA is comprised of 3 fixed gain stages and a final variable gain stage. There is an
offset cancellation loop that encompasses all 4 stages. Figure 4.7 shows the block diagram
of the variable gain amplifier. The offset cancellation network utilized a low-pass filter to
sense any DC offsets. The first gain cell has two inputs. One of the inputs amplifies the
Coc
Vin Vout
VocpVocn
Roc
AE
AL
Figure 4.7: Block diagram of the variable gain amplifier.
signal through the VGA. The other input amplifies the error signal and performs error
correction. The cut-off frequency of the offset cancellation loop is given as follows:
fc =ALAE + 1
2πROCCOC
(4.9)
Thus, fc must be low to reduce wander and data-dependent jitter. Due to the large gain
of both the VGA and error amplifier, the low pass filter in the offset cancellation loop
has to be large. A value of 6 MΩ and 25 pF was chosen for ROC and COC , respectively.
Figure 4.8 shows the implementation for the gain cell in the VGA network. The gain
cell comprises of a Cherry Hooper amplifier with active feedback.
Chapter 4. Circuit Design 44
417 uA
Ω1000
Ω2300
VDD
VDD
Vin
Vout
5 x 2 um
2 x 1 um
4 x 2 um
L = 0.12 um
1 x 1 um
5 x 1 um
3 x 3 um
89 uA
473 uA
Figure 4.8: Schematic of the gain cell in the VGA. The gain cell is a Cherry Hooper Amplifier.
The amplifier has a transfer function can be expressed as a standard 2 pole system
with the following values for Av, ζ, and ω2n [30].
Av =gm1gm5RD1RD2
1 + gm5gm3RD1RD2
(4.10)
ζ =1
2
RD1CL1 +RD2CL2√RD1RD2CL1CL2 (1 + gm3gm5RD1RD2)
(4.11)
ω2n =
1 + gm3gm5RD1RD2
RD1RD2CL1CL2
(4.12)
CL1 and CL2 represents the load capacitance at the internal and output nodes. Based on
these equations, gm1 needs to be large for a large gain and gm5 should be big for a wider
bandwidth.
The input cell and variable gain cell are shown in Figures 4.9 and 4.10 respectively.
In Figure 4.10, source degeneration is used in the first differential pair to achieve the
Chapter 4. Circuit Design 45
474 uA
VDD
VDD
5 x 2 um / 0.12 um
2 x 1 um / 0.12 um
3 x 3 um / 0.12 um
1 x 1 um / 0.12 um
5 x 1 um / 0.12 um
Vin
Vout
5 x 2 um / 0.12 um
Vocp
Vocn
3 x 3 um / 0.12 um
5 x 2 um / 0.12 um
82 uA
408 uA
485 uA
Ω1000
Ω2300
Figure 4.9: Schematic of the input gain cell in the VGA. The gain cell is a Cherry Hooperamplifier with an additional input to cancel any offsets.
variability in gain. An analog voltage controls the triode region of the MOS transistor
and thus the source resistor seen by the input pair. Common mode feedback is employed
on the last stage to ensure that the common mode value of the node connected to the
DFE is near 0.7V. The common mode circuitry employed a gain of 1 and the common
mode of the output was fed to PMOS transistors in the circuit.
Simulation Results
Figure 4.11 shows the range of gains achieved by variable gain amplifier. The VGA has
a small signal gain in the range of 23.9 dB and 35 dB, with a bandwidth of 4 GHz for
the highest gain setting and 7.4 GHz for the lowest gain setting.
4.2.4 Injection Locked Oscillator
A DFE requires a clock aligned to the data for the latches to sample in the middle of
the eye. Implementation of a Clock and Data Recovery (CDR) block would increase the
complexity of the system and is beyond the scope of the project. Instead, a clock was fed
Chapter 4. Circuit Design 46
324 uA
Ω1880
VDD Vout
Vin
Vctrl
VDD
L = 0.12 um
5 x 2 um
4 x 1 um
3 x 1 um
5 x 1 um
10 x 2 um
2 x 1 um
3 x 1 um
5 x 2 um5 x 2 um
200 uA200 uA
206 uA
240kΩ
Figure 4.10: Schematic of the variable gain cell in the VGA. The gain cell is a Cherry Hooperamplifier with source degeneration in the first branch to control the gain. A weak common-modefeedback is used to keep a common-mode voltage of 0.7 V.
into the system and the phase of the clock could be manually adjusted to align with the
incoming data. The Injection Locked Oscillator (ILO) comprises of a Voltage Controlled
Oscillator (VCO), analog demux and clock buffers with Duty Cycle Distortion (DCD)
correction.
Specifications
The ILO should be able to provide a phase shift of at least 180◦ to allow for the clock
to match the phase of the data. In addition, the duty cycle of the output to the latches
in the DFE should be at 50% at all clock phases. This ensures that the data is sampled
in the center of the the eye. Any deviations from this could cause less than optimal
performance.
Chapter 4. Circuit Design 47
103
104
105
106
107
108
109
1010
1011
20
25
30
35
40
45
Frequency [Hz]
AC
Res
pons
[dB
]
vctrl=0Vvctrl=300mVvctrl=400mVvctrl=500mVvctrl=1.2V
Figure 4.11: Bode plot of the variable gain amplifier showing the range of gain offered.
Buffer Design
Figure 4.12 shows one stage of the clock buffer. It comprises of a pair of CMOS inverters.
Each subsequent stage will be sized larger by a factor of 3. This allows for the buffers
to drive all the circuitry in the DFE. There exists a pair of weak CMOS inverters in
between the two differential lines that serves to eliminate any errors in duty cycle that
may be present [31].
VCO Design
A ring ILO was chosen because it provides access to various clock phases as well as having
a relatively small area and the ability to linearly tune clock phase over a wide range. A
block diagram for the ILO is shown in Figure 4.13. The delay stages, shown in Figure
4.14 have an NMOS and PMOS switch near ground and power respectively. The first
Chapter 4. Circuit Design 48
VoutVin
Figure 4.12: Schematic of one stage of the clock buffers.
stage uses it as a switch to turn on or off the stage to form either a delay line or a ring
oscillator. The other three stages have the same switches but are always in the ON state.
This was done to ensure that all stages are identical, which is important for a 50% duty
cycle. Having a delay line allows testing the chip at frequencies too slow for the ILO to
lock to.
en
clk
InjPt
Vosc
Vout
Figure 4.13: Block level diagram of the injection locked oscillator.
There are two injections points, one at the zero degree phase point and the other
at the 45 degree phase point. 90 degrees was not chosen as an injection point because
for certain settings the output of the ILO would not be clean. See Figure 4.15 for a
Chapter 4. Circuit Design 49
Vosc
10 x 2 um
2 x 1.2 um 2 x 1.2 um
2 x 1 um
187 uA
VDD
en
20 x 2 um / 0.12 um
L = 0.12 um
en
Vin
Vout
Figure 4.14: Schematic of one stage of the delay stages in the VCO.
simulation of the voltages at different phase points in the ILO with injection at the 90
degree point. The output node of the VCO has several distortions near the middle of the
waveform which causes the subsequent CMOS buffers to output the incorrect frequency
from the injected clock. However, a 180 degree phase shift is attainable with the 0 and
45 degree injection sites without causing any errors in the output and thus was used.
The targeted datarate of the DFE was 5 Gb/s. Since the DFE architecture used was
a half rate one, the VCO was sized such that the tuning range would be between 4 and
2 GHz.
Chapter 4. Circuit Design 50
Figure 4.15: Node Voltages of the stages in the VCO at an injection point of 90◦ when thephase shift is close to 180◦. The Injection point is at the 90 degree node in the VCO, andthe output of the VCO would be the 90 degree phase shift from the injection point, thus thethird plot. This output waveform has several ripples around the mid point which causes thesubsequent buffers to output the incorrect frequency.
Simulation Results
Figure 4.16 shows the tuning characteristics for the VCO in the ILO. The VCO is able
to oscillate between 4 and 1.5 GHz. Figure 4.17 shows that the ILO is able to attain a
phase shift of more than 180 degrees.
4.2.5 Infinite Impulse Response Decision Feedback Equalizer
The operation and theory behind the IIR-DFE was explained in the earlier chapter. A
detailed block diagram of the system is shown in Figure 4.18. The incoming data stream
goes through a summer where the Inter-Symbol Interference (ISI) is canceled. The output
of the summer goes through a pre-amplifier before splitting up into two latches. One latch
is clocked when the clock is positive and the other on the negative clock. The data is
then muxed together and fed into IIR filter and the result goes back into the summer to
cancel the ISI. The output of the latches also go into another mux and the full-rate data
Chapter 4. Circuit Design 51
0 0.2 0.4 0.6 0.8 1 1.2 1.41
1.5
2
2.5
3
3.5
4
Control Voltage [V]
Fre
quen
cy [G
Hz]
Figure 4.16: Tuning Characteristic of the ILO showing the self-oscillation frequency (withoutinjection) versus control voltage
then proceeds off-chip.
Current Mode Logic Blocks
A Current Mode Logic (CML) latch was used and the schematic is shown in Figure 4.19.
CML blocks steer current into different branches in order to realize their function. The
CML latch tracks the data when current is steered into the first branch when the clock
is high. When the clock goes low, current is steered down the second branch which uses
positive feedback to latch. The delay of the latch is controlled by the resistors at the
transistor drains and the input capacitive load of the next stage. The latch was designed
for an input sensitivity of 10 mV.
Figure 4.20 shows the schematic of a CML mux. It is designed similar to that of the
latch except instead of latching when the clock is low, it allows the second input to move
to the output. Thus, depending on the clock value, either the first input or second input
is seen on the output node. The mux is controlled so that only when the data is latched
and thus valid, does it appear on the output.
Figure 4.21 illustrates the schematic of the summing node. The main branch is similar
Chapter 4. Circuit Design 52
4.2 4.4 4.6 4.8 5−1.5
−1
−0.5
0
0.5
1
1.5
Time [ns]
Vol
tage
Lev
el [V
]
Figure 4.17: Transient output of the ILO illustrating that it’s possible to achieve a 180 degreephase shift at 2.5 GHz.
to that of latches and muxes and just tracks the input. The branches on the right of
the main subtract a scaled current from the current generated by the input on the main
branch. Thus subtraction is performed through current removal.
RC Taps
The RC taps were based on a constant resistor value of 400Ω to enable a certain common-
mode value. The capacitor values were then swept until error-free operation was possible.
This ideal capacitance was then replaced with varactors or a bank of capacitors, to provide
tunability. Two of the RC taps use varactors to acheive capacitances tunable between
800fF and 2.5pF. These RC taps were used to create the steep drop-off. The third tap
responsible for the long tail approximation is comprised of a capacitor bank. A 15 pF
capacitor is permanently attached, along with 4 swithces that can attach capacitors of
10 pF, 5 pF, 2.5pF, and the varactor used in the other RC taps. Thus this tap has
capacitance variation from 15 pF to 35pF. These taps form the poles that are used in
Chapter 4. Circuit Design 53
clk
Vout
clk
clk
PreampVin clk
Figure 4.18: Block diagram of the digital feedback equalizer. Note that clk refers to a half-rateclock. Thus for a 5 Gbps signal, clk = 2.5GHz.
the IIR filter. The schematic of one of the RC taps is shown in Figure 4.22.
Simulation Results
To simulate the DFE block, PRBS31 data was run through the optical channel model
and an estimated channel comprised of the analog frontend. The resulting waveforms
then served as input to the DFE. The data rate was 5 Gb/s and the input eye diagram
is shown in Figure 4.23 (a). As can be seen the eye is completely closed. Table 4.2 shows
the values of all the parameters in the DFE to equalize the eye. The eye diagram of
the associated ISI-free node after the summer is shown in Figure 4.23 (b). The open eye
indicates that the DFE works at 5 Gb/s for a PRBS31 signal. The delay in the critical
Chapter 4. Circuit Design 54
2.5 mA
200Ω
VDD
clk
20 x 1.25 um / 0.12 um 20 x 1.25 um / 0.12 um
20 x 2 um / 0.12 um
40 x 2 um / 0.12 um
+
Vin
+Vout_
_
Figure 4.19: Schematic of the CML latch.
2.5 mA
200Ω
VDD
clk
20 x 1.25 um / 0.12 um 20 x 1.25 um / 0.12 um
20 x 2 um / 0.12 um
40 x 2 um / 0.12 um
Vin1
Vin2
_+
+Vout
_
_
+
Figure 4.20: Schematic of the CML mux.
Chapter 4. Circuit Design 55
itune3
Vinp Vinn
Vout
Vrc1p Vrc1n Vrc2p Vrc2n Vrc3p Vrc3n
VDD
Ω100
8 x 2 um
20 x 2 um
8 x 2 um
20 x 2 um
8 x 2 um
10 x 2 um
8 x 2 um
10 x 2 um1.15 mA1.15 mA
L = 0.12 um
itune1 itune2
200 Ω
Figure 4.21: Schematic of the DFE Summer.
2 mA
400 Ω
100ΩVb
Vin
Vout
VDD
10 x 2 um / 0.12 um
10 x 2 um / 0.12 um
Figure 4.22: Schematic of the RC tap.
path of the DFE is 142 ps. The quality of the ISI-free eye can be improved by refining
the value of the coefficients of the IIR filter.
Chapter 4. Circuit Design 56
Table 4.2: Values of the capacitances and gain of the IIR filter.
Specification Value
C1 25 pFC2 875 fFC3 850 fFT1 500 mVT2 450 mVT3 425 mV
(a) (b)
Figure 4.23: Eye diagram of the (a) input signal to the DFE at 5 Gb/s and (b) ISI-free node(node after the summer) in the DFE at 5 Gb/s for a PRBS 231 − 1. The eye-opening in (b) is100 mV. The simulation was run for 10,000 UI.
4.2.6 Output Buffer
The output buffer has a 50 Ω on chip termination in order to allow maximum power
transfer between the chip and measurement devices, which have an input impedance of
50 Ω. This reduces the reflections when attached to measurement devices and allows for
measurement of the system. In an actual system, an output buffer would not be present.
The bandwidth of the output buffer should be large enough so that it does not affect the
receiver. A 100 fF pad capacitance was assumed and a bandwidth of more than 5 GHz
was targeted.
Chapter 4. Circuit Design 57
Design
The type of output buffer used is commonly called an ft doubler and is used to reduce the
effective input capacitance as in [32] and the schematic is presented in Figure 4.24. The
low resistances at the drains of the transistors mean that much more current needs to
flow through the resistors to bias everything in saturation and allow for adequate output
voltage swing.
5.7 mA
Ω75 Ω75
24 x 2 um / 0.12 um24 x 2 um / 0.12 um
100 x 1.25 um / 0.12 um 100 x 1.25 um / 0.12 um
VDD
Vcm
Vin
Vout
5.7 mA
Figure 4.24: Schematic of the output buffer.
Simulation Results
The Bode plot of the output buffer is shown in Figure 4.25. The output buffer had an
output bandwidth of 4.7 GHz. A differential pair with the same loading would have a
bandwidth of 4.0 GHz.
With a load resistance of 75 Ω, the S22 with a 50 Ω load is below -4 dB up to 10 GHz
and is -12 dB at the Nyquist rate of 2.5 GHz. The output buffer consumes 16 mW of
power.
Chapter 4. Circuit Design 58
106
107
108
109
1010
1011
−25
−20
−15
−10
−5
0
5
Frequency [Hz]
AC
Res
pons
e [d
B]
Figure 4.25: AC Response of the output buffer.
Table 4.3: Simulated power consumption of the various blocks in the optical receiver.
Block Power
ILO and Buffers 7.4 mWAnalog Frontend 13.8 mW
DFE 17.3 mWOutput Buffer 13.7 mW
System Power (excluding Output Buffers) 38.5 mW
Total Power 52.2 mW
4.2.7 Power Consumption
Table 4.3 shows the power break down for the various blocks in the system.
4.3 Summary
This chapter presented an overview of the various blocks inside the optical receiver.
Schematics were presented for each of these blocks in the receiver. The main blocks
discussed were the transimpedance amplifier, variable gain amplifier, decision feedback
Chapter 4. Circuit Design 59
equalizer, injection locked oscillator, and output buffer. Circuit simulations were also
shown to demonstrate the feasibility of the system and demonstrate that the receiver
is able to correctly equalize incoming optical data from an integrated photodetector.
Finally a power budget was presented detailing the power consumption of the various
sub-blocks in the receiver.
Chapter 5
Measurements
5.1 Introduction
This chapter outlines the measurement setup and results from the chip which was fabri-
cated in IBM 0.13μm CMOS with 8 metal layers. A quick description of the chip will be
presented before moving into the various circuits measured and their performance. The
chapter will conclude with a summary of the measurement results.
5.2 Circuit Layout
5.2.1 Photodiodes
The photodiode features 14 fingers of nwell strips. Each strip had a line of metal one
that contacted the n-plus doped regions of the nwell [22]. Fingering was done to reduce
the transit time it takes the signal to move through the doped region before reaching the
contacts to metal one. The structure is similar to that shown in Figure 2.2 (b). Active
region was placed across the entire surface of the nwell to reduce the series resistance
for the collected carriers. This unfortunately led to poor optical performance as will be
explained in the measurement section due to the deposition of silicide.
60
Chapter 5. Measurements 61
5.2.2 Full Die
The total area of the chip was 1.7mm by 1.7mm for an area of 2.9 mm2, as shown in
Figure 5.1. The chip shown in the figure has numerous breakouts of various sub blocks
Figure 5.1: Die photo of the chip.
to allow for debugging and testing. The full optical receiver including the photodiode is
525 μm by 430 μm for an area of 0.23 mm2, and is shown in Figure 5.2. The breakouts
included were that of just the DFE, the full backend, the injection locked oscillator, the
analog frontend with the photodiode, just the photodiode and a full electrical receiver
without the photodiode attached. The completed chip was packaged with Quad Flat No
Leads (QFN).
Chapter 5. Measurements 62
Figure 5.2: Die photo of the optical receiver.
5.3 Measurements
A Printed Circuit Board (PCB) was designed to properly test the chip, as in Figure
5.3. Voltage regulators generated the appropriate supply voltages for the chip. The bias
voltages were controlled through a computer which was connected through a USB cable
to a PIC micro controller on the PCB. Analog values were entered on the computer and
were converted to digital bits and sent to Digital to Analog Converters (DACs) on the
PCB, which generated the appropriate analog voltage. These voltages were then passed
through unity gain buffers before being fed to the chip.
Chapter 5. Measurements 63
Figure 5.3: Photo of the PCB board with the packaged chip shown. The top of the QFN wasremoved so that an optical fiber could be brought close to the integrated photodiodes locatedon the die.
5.3.1 Optical Measurements
Optical testing was performed in the Advanced Photonics Systems Laboratory at Queen’s
University. Optical probes were used along with a probe station to align a bare multi
mode fiber to the exposed photodiodes on the die. A block diagram of the test bench can
be seen in Figure 5.4. A 50 μm multi-mode fiber was used to couple the optical power
emitted from a 850-nm VCSEL source (HFE4192-582) to the on-chip photodetector. A
power meter (Noyes OPM4) was used to measure the emitted light from the VCSEL and
a multimeter was used to measure the output current from which the DC responsivity
can be calculated. With an input power of -1 dBm the output current recorded was
0.5 μA which indicates a DC responsivity of 0.0006 A/W. This number is much lower
than anticipated and would be below the noise floor of the TIA. The reason for this
Chapter 5. Measurements 64
disparity has to do with the deposition of silicide in sub-micron technology nodes [9]. A
cross-section of the various layers can be seen in Figure 5.5.
Divide by 2
PatternGenerator
BERT
Scope
Fiber
VCSEL
in out
clkin
DUT
full−rate clk
Clock
Figure 5.4: Diagram depicts how an optical test bench would operate. The source modulatesa VCSEL with transmits light through the fiber to the DUT. The clock provided by the signalsource is converted to a half-rate clock for the DUT and the full rate clock is used to triggerthe scope and BERT.
Figure 5.5: Cross-section showing the areas in which silicide is deposited, namely thesource/drain diffusion regions.
Silicide is a metal that is usually annealed on top of the source, drain and polysilicon
regions in order to reduce the resistivity in these regions. According to [33] the trans-
missivity of 18nm of Cobalt silicide (used in IBM’s process), can range from 5% to 10%.
Hence the photodiodes were rendered useless due to the minute amount of photons that
are able to penetrate the top of the silicon substrate. A full optical measurement could
thus not be performed. A re-spin of the design with the unsilicided photodiodes is being
submitted to CMC so that the full optical receiver can be tested.
Chapter 5. Measurements 65
5.3.2 Electrical Measurements
Since an optical test could not be done, an extensive electrical test was conducted to
ensure that the DFE worked. Figure 5.6 shows the test bench used to measure the DUT.
Divide by 2
75ΩChannel
PatternGenerator
BERT
Scope
in out
clkin
clkout
DUT
Scope
full−rate clk
Clock
Figure 5.6: A pattern generator generates both the PRBS signal and a full-rate clock. Thesignal goes through a channel before the DUT. The clock is converted to a half-rate clock tooperate the DFE. The full-rate clock is used to trigger the scope and BERT.
Injection Locked Oscillator
A decision feedback equalizer is dependent on a clock to operate properly. This was
achieved by an on-chip ILO, where the phase of an injected clock can be tuned by varying
a control voltage. Figure 5.6 illustrates the test bench used to perform characterization
of the injection locked oscillator. Figure 5.7(a) and (b) shows the peak to peak amplitude
at various phase settings for both 1.5 GHz and 3 GHz oscillation frequencies respectively.
The most important measure of any ILO is to ensure that a full 180 degree phase
change is possible. Figure 5.8 shows that for both 1.5 GHz and 2.5 GHz a phase range
of at least 180 degrees is possible when both injection points are used.
Chapter 5. Measurements 66
(a) (b)
Figure 5.7: Transient outputs of the ILO at various phases for (a) 1.5 GHz and (b) 3 GHz.It should be noted that the peak to peak amplitudes of the signal do not change over phase orfrequency.
300 400 500 600 700 800 9000
50
100
150
200
250
300
Control Voltage [V]
Out
put P
hase
[deg
rees
]
0 Injection Point45 Injection Point
(a)
0 100 200 300 4000
50
100
150
200
250
Control Voltage [V]
Out
put P
hase
[deg
rees
]
0 Injection Point45 Injection Point
(b)
Figure 5.8: Phase of the ILO at various control voltages for (a) 1.5 GHz and (b) 2.5 GHz. Ascan be seen, a full 180 degree phase shift is possible.
The jitter histogram of the output waveform at 2.5 GHz can be seen in Figure 5.9.
The rms jitter present is at most 2.5 ps.
Figure 5.10 shows the rms jitter across various phases at both 1.5 GHz and 2.5 GHz.
Likewise, Figure 5.11 shows the duty cycle at the same frequencies. Unfortunately, the
Chapter 5. Measurements 67
Figure 5.9: Jitter Histogram of the ILO with an output clock frequency of 2.5 GHz.
free-running frequency of the ILO could not be measured due to the buffers preceding
the ILO which force internal nodes of the VCO to either the power or ground rails and
thus prevent the ILO from oscillating when there is no input.
0 50 100 150 200 2502
2.2
2.4
2.6
Clock Phase [degrees]
Out
put R
MS
Jitt
er [p
s]
(a)
0 50 100 150 2001.8
2
2.2
2.4
2.6
Clock Phase [degrees]
Out
put R
MS
Jitt
er [p
s]
(b)
Figure 5.10: RMS jitter of the ILO at various control voltages for (a) 1.5 GHz and (b) 2.5GHz. The rms jitter does not exceed 2.5 ps over various frequencies and phases
Chapter 5. Measurements 68
0 50 100 150 200 25046
48
50
52
54
Clock Phase [degrees]
Dut
y C
ycle
[%]
(a)
0 50 100 150 20046
47
48
49
50
Clock Phase [degrees]
Dut
y C
ycle
[%]
(b)
Figure 5.11: Duty cycle of the ILO at various control voltages for (a) 1.5 GHz and (b) 2.5GHz. The duty cycle stays within a couple of percent of the optimal value, 50%.
DFE
Since there are no break-out of the front end without photodiodes, it was not possible
to test the front end separately. However, it can be inferred that the front end works.
An input signal of 60mV peak to peak had sufficient gain to ensure that the DFE works
appropriately. Furthermore, in simulations dropping the input voltage to below 50mV
peak to peak will introduce bit errors if there is no change to the DFE coefficients. This
result was reproduced with the actual chip. The results for the full system is presented
below. The channel used was a 10m, 75Ω Belkin coaxial cable. The S21 plot can be seen
in Figure 5.12.
This channel was chosen because the response can be seen to roll off at -5dB/decade
in the region of interest which is similar to an optical photodiode. Thus the DFE co-
efficients needed to properly equalize the channel are close to what were simulated for
the integrated photodiode channel. It was found in measurements, that the only change
needed to accomodate the coaxial cable channel was to turn off the filter responsible for
the long tail in the pulse response. This corresponds with having a channel bandwidth
close to 1 GHz as opposed to 4 MHz. The maximum data rate achievable was 3.7 Gb/s
with a wireline channel. The TIA was designed to have a low input impedance in order
Chapter 5. Measurements 69
106
107
108
109
1010
−25
−20
−15
−10
−5
0
5
Frequency [Hz]
AC
Res
pons
e [d
B]
Figure 5.12: S21 results for a 10m Belkin coaxial cable channel. The average roll-off is closeto -5 dB/decade between 200 MHz and 2 GHz and at 2.5GHz has a loss of -12.5dB.
ensure that the dominant pole formed by the input impedance and the capacitance of
the photodiode was as small as possible. Unfortunately, this means that the TIA was
not matched to 75 Ω and numerous reflections close the input eye. Figure 5.13 shows the
input to the TIA. A power splitter was used to measure the TIA input during operation
and get a sense of how the reflections affect the incoming signal. The setup for this can
be seen in Figure 5.14.
Simulations with the S-parameter block of the channel were also done to verify the
measurements, as shown in Figure 5.15. Figure 5.16 shows the transient response to a 4
Gbps (250ps wide) pulse at the input of the TIA after the channel and with reflections.
At around 4 Gb/s the pulse response has a slight staircase shape to it, which distorts the
impulse response such that it can’t be equalized by the DFE anymore. The DFE was
not given enough programmability to equalize an arbitrary response and thus for high
data rates, the DFE is not able to equalize the signal. Thus the input reflections limit
the datarate that can be correctly equalized.
Chapter 5. Measurements 70
Figure 5.13: Eye diagram at 3.6 Gbps showing the input that the TIA would see withreflections. It should be noticed that measuring the eye adds distortion, and thus the eyeshould serve as an approximation of what is actually present.
500fF
0o
PowerCombiner
50 Ω75Ω
Channel50Ω
DUT
1nH
100fF
cAPCB Trace
50Ω
Figure 5.14: Electrical test bench to determine what the input to the TIA is because of inputreflections.
Figure 5.17 (a) and (b) shows the output eye diagram of the DFE with equalization
turned off for a lossless channel at both 4 and 5 Gb/s, respectively. This is the output of a
latch so is not a good indication of how well the receiver performs. The key indicator that
should be used in characterizing DFEs are bathtub plots. These plots were generated by
Chapter 5. Measurements 71
cA75ΩChannel PCB Trace
50Ω50Ω 1nH
DUT
100fF500fF
Figure 5.15: Simulation test bench to emulate the system being measured and accuratelycapture the input reflection effect.
0 1 2 3 4 50
0.2
0.4
0.6
0.8
1
Time [ns]
Nor
mal
ized
Pul
se R
espo
nse
Figure 5.16: 4 Gbps impulse response showing the effects of reflections to the signal. It shouldbe noted that there is a staircase-like effect that causes the pulse response to move away fromwhat is expected.
varying the phase of the clock using the ILO and recording the Bit Error Rate (BER).
The purpose of the bathtub curve is to measure the horizontal eye opening of the ISI-free
node of the DFE (after the summer) as shown in Figure 4.18.
Figures 5.18, 5.19, 5.20, and 5.21 show bathtub plots with the equalization both on
and off with a PRBS of 27 − 1 for data rates 2.7 Gb/s, 3.6 Gb/s, 3.7 Gb/s and 3.8 Gb/s.
It can be observed that as the data rate increases, the horizontal eye width decreases.
In other words, as the data rate increases, the horizontal eye opening decreases. The
maximum achievable data rate with a Bit Error Rate (BER) of less than 10−12 was 3.7
Chapter 5. Measurements 72
(a) (b)
Figure 5.17: Retimed data from the DFE from lossless channels at (a) 4 Gb/s and (b) 5 Gb/s.
Table 5.1: Measured power consumption of the various blocks in the optical receiver at 5Gbps.
Block Power
ILO and Buffers 7.9 mWAnalog Frontend 11.2 mW
DFE 16.2 mWOutput Buffer 16.1 mW
System Power (excluding Output Buffers) 35.3 mW
Total Power 51.4 mW
Gb/s. Figure 5.22 shows the output eye at 3.7 Gbps: (a) is the output from the latch
with equalization turned off and (b) is with equalization on. Note that the same DFE
tap weights were used for the measurement at 2.7 Gb/s and 3.7 Gb/s; this is unlike a
conventional DFE where totally different tap weights would be required for these different
data rates.
The power distribution of the receiver is shown in Table 5.1. The total power con-
sumed including the output buffer is 57.8 mW. Excluding the output buffer, the power
consumed by the receiver is 35.3 mW.
Chapter 5. Measurements 73
−0.2 −0.1 0 0.1 0.2 0.310
−12
10−10
10−8
10−6
10−4
Normalized Clock UI
Bit
Err
or R
ate
DFE OnDFE Off
Figure 5.18: Bathtub plot of the receiver at 2.7Gb/s with equalization on and off.
5.4 Summary
This chapter presented measured results for the optical receiver. Due to silicide over the
photodiodes, an optical measurement could not be done. As a substitute, the receiver was
measured with a wireline channel that has a similar roll-off to what would be expected
from an optical photodiode, namely -5 dB/decade. The wireline channel however has
more bandwidth than that of an optical photodiode. As such, one filter pole in the IIR
DFE was turned off. The TIA in the frontend of the equalizer was designed to have a
low input resistance, therefore there were numerous reflections between the channel and
TIA which resulted in worsening the input eye to the system. The maximum data-rate
that could be equalized was 3.7 Gb/s, limited by the reflections in this particular channel
(not by circuit speed). The total power consumed by the receiver was 35.3 mW without
the output buffer and 52.3 mW with the output buffer.
Chapter 5. Measurements 74
−0.2 −0.1 0 0.1 0.2 0.310
−12
10−10
10−8
10−6
10−4
Normalized Clock UI
Bit
Err
or R
ate
DFE OnDFE Off
Figure 5.19: Bathtub plot of the receiver at 3.6Gb/s with equalization on and off.
−0.2 −0.1 0 0.1 0.2 0.310
−12
10−10
10−8
10−6
10−4
Normalized Clock UI
Bit
Err
or R
ate
DFE OnDFE Off
Figure 5.20: Bathtub plot of the receiver at 3.7Gb/s with equalization on and off.
Chapter 5. Measurements 75
−0.2 −0.1 0 0.1 0.2 0.310
−12
10−10
10−8
10−6
10−4
Normalized Clock UI
Bit
Err
or R
ate
DFE OnDFE Off
Figure 5.21: Bathtub plot of the receiver at 3.8Gb/s with equalization on and off.
Chapter 5. Measurements 76
(a)
(b)
Figure 5.22: Eye diagram of the (a) unequalized output at 3.7 Gb/s and (b) equalized outputat 3.7 Gb/s.
Chapter 6
Conclusion
6.1 Conclusion
The design of an IIR decision feedback equalizer has been investigated for compensation
of long pulse tails, such as those found in CMOS integrated optical chips. These long
tails are a result of the slow diffusion of minority carriers through the substrate into the
depletion region leading to one input pulse generating signal current over many UIs. The
DFE uses an analog filter to form an approximation of the pulse response introduced by
the optical photodiode. This approximation is then subtracted from the incoming signal
in order to recover the ISI-free data.
A chip was fabricated in IBM 0.13μm CMOS to validate the idea. The integrated
photodiodes on the die were opaque to light because of silicide covering the entire pho-
todetector, thus the DFE was not able to equalize the channel it was designed to work
with. A 10m long coaxial cable has similar roll-off to an integrated photodiode and was
used as the channel. Input reflections reduced the equalized data rate to 3.7 Gbps. A
frontend of 3 GHz was used to to provide a low noise, linear input stage. A propagation
delay of 142 ps was found through the critical path of the DFE based on simulation. The
receiver occupies an area of 0.23 mm2, operates from a 1.2V supplies and draws 29.4 mA
77
Chapter 6. Conclusion 78
of current excluding the output buffers.
Simulations show that equalization is able to be performed at data rates up to 5
Gb/s with -10 dBm input sensitivity, while consuming 35.3 mW of power. When optimal
tap weights and pole locations match the response generated by the photodiode, they
can remain locked for all data-rates as the IIR filter will change the pulse response
depending on the input data rate appropriately. Provided there are no variations in the
photodiodes on the semiconductor die, the equalization coefficients can remain constant.
A comparison of this work is shown in Table 6.1. It should be noted that because of the
blocked photodiode, the data rate and responsivity are simulated values.
In conclusion, integrated monolithic CMOS photodiodes are a poor channel. Increas-
ing input sensitivity and generating maximal photo-current, requires a photodiode whose
3-dB frequency is around 2 to 4 MHz with a roll-off of -5 dB/decade. This translates to
a pulse response with a long tail that restricts the maximum transmission datarate. An
equalizer was designed in IBM 0.13 μm CMOS that uses an IIR filter DFE with one tap
to approximate and eliminate this long tail.
6.2 Future Work
Due to the number of coefficients needed to equalize the channel, algorithms for making
the system adaptive should be investigated. The location and magnitude of the low
frequency pole is the most important since it controls the long exponential tail which is
responsible for the majority of ISI in the other UIs. One way to monitor the adaptation
of this long tail is to monitor the DC value of the equalized signal. If the DC level is
rising then there is too little equalization being applied to the signal and if the DC level
is dropping, then there is too much equalization being applied. Finding the optimal value
for the long tail eliminates the majority of UIs and reduces the search space for adapting
the other filter parameters.
Chapter 6. Conclusion 79
Table 6.1: Comparison of various high performance optical receivers.
[3] [19] [18] [17] This work
Technology 0.18 μm 0.18 μm 0.13 μm 0.13 μm 0.13 μm
Area N/A 0.72 mm2 1.77 mm2 0.1 mm2 0.23 mm2
Supply Voltage 1.8V 3.3/1.8 V 1.2 V 1.5 V 1.2 V
Power Dissipa-tion (ExcludingOutput Buffer)
34 mW 168 mW 74 mW 47 mW 35.3 mW
Data Rate 3 Gbps 5 Gbps 4.5 Gbps 8.5 Gbps 5 Gbps (simulated)
Bit Error Rate 10−11 10−12 10−12 10−12
10−12 (verified at3.7 Gbps for acoaxial channel)
Gain N/A 119 dBΩ 105dBΩ 120 dBΩ85 dBΩ (TIA +
VGA)
Sensitivity -19 dBm -3 dBm -3.4 dBm -3.2 dBm-10 dBm
(simulated)
Chapter 6. Conclusion 80
Data rates can also be extended by designing a differential photodiode to gather
both the positive and negative photocurrent and thereby increase the input sensitivity.
Migrating to more advanced technologies will enable faster DFEs and TIAs thus providing
the possibility of pushing the datarate to 10 Gb/s.
References
[1] Anthony Chan Carusone, Hemesh Yasotharan, and Tony Kao, “Progress and Trends
in Multi-Gbps Optical Receivers with CMOS Integrated Photodetectors”, Custom
Integrated Circuits Conference, pp. 1–8, 2010.
[2] C. Hermans, P. Leroux, and M. Steyaert, “Two high-speed optical front-ends with
integrated photodiodes in standard 0.18 μm CMOS”, European Solid-State Circuits
Conference, pp. 275–278, 2004.
[3] S. Radovanovic, A.-J. Annema, and B. Nauta, “A 3-Gb/s optical detector in stan-
dard CMOS for 850-nm optical communication”, Journal of Solid-State Circuits,
vol. 40, no. 8, pp. 1706–1717, Aug. 2005.
[4] Carolien Hermans and Michiel Steyaert, Broadband Opto-Electrical Receivers in
Standard CMOS, Springer, 2007.
[5] W Huang, Y Liu, and Y Hsin, “Bandwidth enhancement in Si photodiode by
eliminating slow diffusion photocarriers”, Electronics Letters, vol. 44, no. 1, pp. 3–4,
2008.
[6] Shih-hao Huang andWei-zen Chen, “A 10-Gbps CMOS Single Chip Optical Receiver
with 2-D Meshed Spatially-Modulated Light Detector”, Custom Integrated Circuits
Conference, pp. 129–132, 2009.
81
References 82
[7] Wei-Zen Chen and Shih-Hao Huang, “A 2.5 Gbps CMOS Fully Integrated Optical
Receicer with Lateral PIN Detector”, IEEE Custom Integrated Circuits Conference,
pp. 293–296, 2007.
[8] Peter J-w Lim, Andrew Y C Tzeng, Harry L Chuang, and A St Ongez, “A 3.3-
V Monolithic Photodetector/CMOS Preamplifier for 531 Mb/s Optical Data Link
Applications”, International Solid-State Circuits Conference, , no. 11, pp. 600–602,
1993.
[9] T.K. Woodward and A.V. Krishnamoorthy, “1-Gb/s integrated optical detectors
and receivers in commercial CMOS technologies”, Journal of Selected Topics in
Quantum Electronics, vol. 5, no. 2, pp. 146–156, 1999.
[10] R. Li, J.D. Schaub, S.M. Csutak, and J.C. Campbell, “A high-speed monolithic
silicon photoreceiver fabricated on SOI”, IEEE Photonics Technology Letters, vol.
12, no. 8, pp. 1046–1048, 2000.
[11] M. Ghioni, F. Zappa, V.P. Kesan, and J. Warnock, “A VLSI-compatible high-speed
silicon photodetector for optical data link applications”, IEEE Transactions on
Electron Devices, vol. 43, no. 7, pp. 1054–1060, July 1996.
[12] S M Csutak, J D Schaub, W E Wu, and J C Campbell, “High-speed monolithically
integrated silicon optical receiver fabricated in 130-nm CMOS technology”, IEEE
Photonics Technology Letters, vol. 14, no. 4, pp. 516–518, Apr. 2002.
[13] Robert Swoboda and Horst Zimmermann, “11Gb/s Monolithically Integrated Sil-
icon Optical Receiver for 850nm Wavelength”, International Solid-State Circuits
Conference, pp. 904–911, 2006.
[14] Tony Kao, “A 5-Gbps Optical Receiver with Monolithically Integrated Photodetec-
tor in 0.18um CMOS”, Master’s thesis, University of Toronto, 2009.
References 83
[15] Wei-zen Chen, Shih-hao Huang, Guo-wei Wu, Chuan-Chang Liu, Yang-Tung Huang,
Chin-Fong Chiu, Wen-Hsu Chang, and Ying-Zong Juang, “A 3.125 Gbps CMOS
fully integrated optical receiver with adaptive analog equalizer”, IEEE Asian Solid-
State Circuits Conference, pp. 396–399, Nov. 2007.
[16] Carolien Hermans and Michiel S J Steyaert, “A High-Speed 850-nm Optical Receiver
Front-End in 0.18um CMOS”, Journal of Solid-State Circuits, vol. 41, no. 7, pp.
1606–1614, 2006.
[17] Dongmyung Lee, Jungwon Han, Gunhee Han, and Sung Min Park, “An 8.5-Gb /
s Fully Integrated CMOS Optoelectronic Receiver using Slope-Detection Adaptive
Equalizer”, Journal of Solid-State Circuits, vol. 45, no. 12, pp. 1–13, 2010.
[18] Filip Tavernier and Michel S. J. Steyaert, “High-Speed Optical Receivers With
Integrated Photodiode in 130 nm CMOS”, Journal of Solid-State Circuits, vol. 44,
no. 10, pp. 2856–2867, Oct. 2009.
[19] Tony Shuo-chun Kao, Faisal A Musa, and Anthony Chan Carusone, “A 5-Gbit/s
CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and
Equalization”, IEEE Transactions on Circuits and Systems I, pp. 1–14, 2010.
[20] Jan Genoe, Coppee Danniel, Johan Stiens, Roger Vounckx, and M Kuijk, “Calcu-
lation of the Current Response of the Spatially Modulated Light CMOS Detector”,
IEEE Transactions on Electron Devices, , no. 9, pp. 1892–1902, 2001.
[21] S. Radovanovic, A.J. Annema, and B. Nauta, “Physical and electrical bandwidths
of integrated photodiodes in standard CMOS technology”, 2003 IEEE Conference
on Electron Devices and Solid-State Circuits, pp. 95–98, 2003.
[22] Sasa Radovanovic, Annejohan Annema, and Bram Nauta, “On optimal structure
and geometry of high-speed integrated photodiodes in a standard CMOS technol-
References 84
ogy”, The 5th Pacific Rim Conference on Lasers and Electro-Optics, vol. 48, no. 9,
pp. 87, 2003.
[23] John F Bulzacchelli, Alexander V Rylyakov, and Daniel J Friedman, “Power-
Efficient Decision-Feedback Equalizers for Multi-Gb/s CMOS Serial Links”, Radio
Frequency Integrated Circuits Symposium, pp. 507–510, 2007.
[24] Azita Emami-neyestanak, Aida Varzaghani, John F Bulzacchelli, Alexander
Rylyakov, Chih-kong Ken Yang, and Daniel J Friedman, “A 6.0-mW 10.0-Gb/s
Receiver with Switched-Capacitor Summation DFE”, Journal of Solid-State Cir-
cuits, vol. 42, no. 4, pp. 889–896, 2007.
[25] Byungsub Kim, Yong Liu, Timothy O Dickson, John F Bulzacchelli, and Daniel J
Friedman, “A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization
in 65-nm CMOS”, Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3526–3538,
2009.
[26] Timothy O. Dickson, John F. Bulzacchelli, and Daniel J. Friedman, “A 12-
Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-
Integrating Summers in 45-nm SOI CMOS Technology”, Journal of Solid-State
Circuits, vol. 44, no. 4, pp. 1298–1305, Apr. 2009.
[27] Masum Hossain and Anthony Chan Carusone, “8.2 A 6.8mW 7.4Gb/s Clock-
Forwarded Receiver with up to 300MHz Jitter Tracking in 65nm CMOS”, Interna-
tional Solid-State Circuits Conference, pp. 158–159, 2010.
[28] E Sackinger, Broadband Circuits for OPtical Fiber Communication, John Wiley and
Sons, 2005.
[29] Feng-tso Chien and Yi-jen Chan, “Bandwidth enhancement of transimpedance am-
plifier by a capacitive-peaking design”, IEEE Journal of Solid-State Circuits, vol.
34, no. 8, pp. 1167–1170, 1999.
References 85
[30] Sherif Galal and Behzad Razavi, “10-Gb/s Limiting Amplifier and Laser/Modulator
Driver in 0.18 um CMOS technology”, Journal of Solid-State Circuits, vol. 38, no.
12, pp. 2138–2146, 2003.
[31] B.W. Garlepp, K.S. Donnelly, P.S. Chau, J.L. Zerbe, C. Huang, C.V. Tran, C.L.
Portmann, D. Stark, T.H. Lee, and M.a. Horowitz, “A portable digital DLL for
high-speed CMOS interface circuits”, IEEE Journal of Solid-State Circuits, vol. 34,
no. 5, pp. 632–644, May 1999.
[32] Behzad Razavi, Design of Integrated Circuits for Optical Communication Systems,
McGraw-Hill, 2003.
[33] Hon-sum Wong, “Technology and device scaling considerations for CMOS imagers”,
IEEE Transactions on Electron Devices, vol. 43, no. 12, pp. 2131–2142, 1996.