EPC2033 – Enhancement Mode Power Transistor · eGaN® FET DATASHEET EPC2033 EPC – THE LEADER IN...

eGaN® FET DATASHEET EPC2033

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EPC2033 – Enhancement Mode Power Transistor

VDS , 150 VRDS(on) , 7 mΩID , 48 A

EPC2033 eGaN® FETs are supplied only inpassivated die form with solder bumps. Die Size: 4.6 mm x 2.6 mm

• High Frequency DC-DC Conversion• Motor Drive• Industrial Automation• Class-D Audio

EFFICIENT POWER CONVERSION

Maximum Ratings

PARAMETER VALUE UNITVDS Drain-to-Source Voltage (Continuous) 150 V

ID

Continuous (TA = 25°C, RθJA = 4°C/W) 48A

Pulsed (25°C, TPULSE = 300 µs) 260

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature -40 to 150°C

TSTG Storage Temperature -40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 0.45

°C/W RθJB Thermal Resistance, Junction-to-Board 3.9

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 45Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

All measurements were done with substrate connected to source.

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.7 mA 150 V

IDSS Drain-Source Leakage VGS = 0 V, VDS = 120 V 0.1 0.5 mA

IGSSGate-to-Source Forward Leakage VGS = 5 V 1 8 mA

Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.5 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 9 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 5 7 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V

G

D

SHAL

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.



0

50

100

150

200

250

0 1 2 3 4 5 6

I D-D

rain

Cur

rent

(A)

VDS - Drain-to-Source Voltage (V)

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V

250

200

150

100

50

00 1 2 3 4 5 6

I D –

Dra

in Cu

rrent

(A)

Figure 1: Typical Output Characteristics at 25°C

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

20

15

10

5

03.0 3.5 4.0 4.5 5.0

R DS(o

n) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ)

VGS – Gate-to-Source Voltage (V)

ID = 10 AID = 25 AID = 50 AID = 100 A

Figure 3: RDS(on) vs. VGS for Various Drain Currents

I D –

Dra

in Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

25˚C125˚C

VDS = 3 V

25˚C125˚C

VDS = 6 V

250

200

150

100

50

0

3.0 3.5 4.0 4.5 5.0

Figure 4: RDS(on) vs. VGS for Various Temperatures

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ)


25˚C125˚C

VDS = 3 V

25˚C125˚C

ID = 25 A

20

15

10

5

0

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance

VDS = 120 V, VGS = 0 V

1160 1400

pF

CRSS Reverse Transfer Capacitance 6

COSS Output Capacitance 480 720

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 120 V, VGS = 0 V

670

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 900

RG Gate Resistance 0.5 Ω

QG Total Gate Charge VDS = 120 V, VGS = 5 V, ID = 25 A 12 15

nC

QGS Gate-to-Source Charge

VDS = 120 V, ID = 25 A

3.8

QGD Gate-to-Drain Charge 3.2

QG(TH) Gate Charge at Threshold 2.8

QOSS Output Charge VDS = 120 V, VGS = 0 V 90 135

QRR Source-Drain Recovery Charge 0All measurements were done with substrate connected to source.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.



All measurements were done with substrate shortened to source. TJ= 25°C unless otherwise stated.

Capa

citan

ce (p

F)

1000

100

10

10 50 100 150

Figure 5b: Capacitance (Log Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 7: Reverse Drain-Source Characteristics150

100

50

0

25˚C125˚C

VDS = 3 V

25˚C125˚C

VGS = 0 V

Figure 9: Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.600 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 11 mAID = 8 mA

Capa

citan

ce (p

F)

0 50 100 150

Figure 5a: Capacitance (Linear Scale)


2000

1500

1000

500

0

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

Figure 6: Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

5

4

3

2

1

00 10 128642

QG – Gate Charge (nC)

ID = 25 AVDS = 120 V

Figure 8: Normalized On-State Resistance vs. Temperature

ID = 30 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.60 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 25 AVGS = 5 V



Figure 12: Transient Thermal Response Curves

0.1

1

10

100

0.1 1 10 100

I D – D

rain

Curre

nt (A

)

VDS - Drain-Source Voltage (V)

Limited by RDS(on)

Pulse Width 100 ms

10 ms 1 ms

100 µs

Figure 11: Safe Operating Area

TJ = Max Rated, TC = +25°C, Single Pulse

I G –

Gate

Curre

nt (m

A)


Figure 10: Gate Leakage Current

25˚C125˚C

40

30

20

10

00 1 2 3 4 5 6

tp, Rectangular Pulse Duration, seconds

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.050.02

Single Pulse

0.01

0.1

Duty Cycle:

Junction-to-Case

PDM

t1

t2

10-510-6 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

0.0001

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

tp, Rectangular Pulse Duration, seconds

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.1

0.020.05

Single Pulse

0.01

Duty Cycle:

Junction-to-Board

PDM

t1

t2

10-5 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

0.0001

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

10+1



2033 YYYY ZZZZ Die orientation dot

Gate Pad bump is under this corner

Part Number

Laser Marking

Part #Marking Line 1

Lot_Date CodeMarking Line 2

Lot_Date CodeMarking Line 3

EPC2033 2033 YYYY ZZZZ

DIE MARKINGS

2033YYYYZZZZ

TAPE AND REEL CONFIGURATION4 mm pitch, 12 mm wide tape on 7” reel

7” reel

a

d e f g

c

b

Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatesolder bump isunder thiscorner

Die is placed into pocketsolder bump side down(face side down)

Loaded Tape Feed Direction

Dimension (mm) target min EPC2033 (note 1)

max a 12.00 11.70 12.30 b 1.75 1.65 1.85

c (note 2) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (note 2) 2.00 1.95 2.05 g 1.5 1.5 1.6

DIE OUTLINESolder Bump View

Pads 1 and 2 are Gate;

Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain;

Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are

Source;

Pad 12 is Substrate*

*Substrate pin should be connected to Source

Side View

DIMMicrometers

MIN Nominal MAX

A 4570 4600 4630B 2570 2600 2630c 1000 1000 1000d 500 500 500e 285 300 315f 332 369 406

510 t

yp

Seating plane

79

0 typ

280+

/−28

B

A

cX4

e

e

155 10 20

d X4

f

1

166 11 212

177 12 22

188 13 233

199 14 244



RECOMMENDEDLAND PATTERN (units in µm)

Pads 1 and 2 are Gate;

Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain;

Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source;

Pad 12 is Substrate*

*Substrate pin should be connected to Source

Land pattern is solder mask definedSolder mask opening is 330 µmIt is recommended to have on-Cu trace PCB vias

2600

4600

1000X4

300

300

500

X4330

155 10 201

166 11 212

177 12 22

188 13 233

199 14 244

RECOMMENDEDSTENCIL DRAWING (units in µm)

RECOMMENDEDSTENCIL DRAWING (units in µm)

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

2600

4600

1000X4

300

300

500

X4

330

155 10 201

166 11 212

177 12 22

188 13 233

199 14 244

2600

4600

1000300

300

500

300

350

155 10 201

166 11 212

177 12 22

188 13 233

199 14 244

Option 1 : Intended for use with SAC305 Type 4 solder.

Option 2 : Intended for use with SAC305 Type 3 solder.

Information subject to change without notice.

Revised August, 2019

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

EPC2033 – Enhancement Mode Power Transistor · eGaN® FET DATASHEET EPC2033 EPC – THE LEADER IN...

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