IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013 1103

Enhanced Performance of P-FET Omega-Gate SoINanowire With Recessed-SiGe Source-Drain

Down to 13-nm Gate LengthSylvain Barraud, Remi Coquand, Jean-Michel Hartmann, Virginie Maffini-Alvaro,

Marie-Pierre Samson, Lucie Tosti, and Fabienne Allain

Abstract— Ultrashort gate length silicon-on-insulator nanowire(NW) transistors with embedded source/drain (S/D) SiGe stres-sors were fabricated. An enhancement of P-FET NW perfor-mance is achieved using in situ HCl + GeH4 etching and selectiveepitaxial growth of boron-doped Si0.7Ge0.3 for the formation ofrecessed S/D. For the first time, an ION current improvementof +100% along the 〈110〉 direction induced by SiGe S/Dis achieved in Omega-FET NWs down to 13-nm gate length.The current enhancement coming from uniaxial compressivestrain of recessed SiGe S/D stressors in narrow-channel transis-tors is well demonstrated (+100% versus +40% in wide planarFET).

Index Terms— Embedded SiGe source-drain, MOSFET,nanowire, omega-gate, silicon-on-insulator (SoI), uniaxial com-pressive strain.

I. INTRODUCTION

NANOWIRE (NW) transistors are now widely recognizedas one of the most promising solutions to go beyond con-

ventional planar bulk and fully depleted silicon-on-insulator(SoI) technologies. Whereas NW transistors with excellentimmunity to short-channel effects have already been fabricated[1]–[4], strain-induced enhancement in short-channel NW willbe crucial for the 10-nm technology node and below [5].We have recently shown that the uniaxial tensile strain (andthus the higher electron mobility) with an excellent elec-trostatic integrity inherent to N-FET NWs (scaled down to10-nm width) fabricated on strained-SoI substrates were idealfor high-performance logic applications [2]. Embedded SiGesource/drain (S/D) integration has been previously demon-strated on bulk [6]–[8] and fully depleted SoI [9]–[11]p-type MOSFETs. Few results have been, however, reportedon P-FET NW transistors [12]. In this letter, two competingschemes used as stressors are carefully benchmarked, raised

Manuscript received July 1, 2013; accepted July 18, 2013. Date of publi-cation August 6, 2013; date of current version August 21, 2013. This workwas supported by the frame of the ST/IBM/LETI joint program. The reviewof this letter was arranged by Editor L. Selmi.

S. Barraud, J.-M. Hartmann, V. Maffini-Alvaro, L. Tosti, and F. Allain, arewith the Commissariat à l’Energie Atomique et aux Energies Alternatives,LETI, Grenoble 38054, France (e-mail: sylvain.barraud@cea.fr).

R. Coquand is with the Commissariat à l’Energie Atomique et aux EnergiesAlternatives, LETI, Minatec campus, Grenoble 38054, France, and also withSTMicroelectronics, Crolles 38926, France.

M.-P. Samson is with STMicroelectronics, Crolles 38926, France.Color versions of one or more of the figures in this letter are available

online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2013.2274172

A’

AA’ sec�onHNW=12nm, WNW=11nm

(a) (b) (c)

LG=13nm

A

Fig. 1. (a) Energy dispersive X-ray analysis of HfSiON/TiN omega-shaped-gate NW MOSFETs. (b) Cross-sectional TEM images of Omega-gate NWMOSFETs with 11-nm width (WNW) and 12-nm height (HNW). (c) 13-nmgate length (LG ).

S/D using in situ B-doped Si0.7Ge0.3 and in situ HCl etchingwith selective epitaxial growth (SEG) of B-doped Si0.7Ge0.3for the formation of recessed S/D [13]. This first demonstrationof Omega-FET Si NW scaled down to LG = 13 nm showsan ION improvement up to +100% along the 〈110〉 directioncompared with its Si S/D counterpart. Finally, the compressivestrain effect on electrical performance of P-FET NW transis-tors are presented and discussed for different NW widths andSiGe:B film thicknesses.

II. DEVICE FABRICATION

The NW transistors were fabricated on 300-mm SoI sub-strates with a 145-nm buried oxide. The silicon layer ispatterned to create the NWs with a mesa isolation technique.A transmission electron microscopy (TEM) cross section of anOmega-gate transistor with LG = 13 nm and WNW = 11 nmis shown in Fig. 1. The Si thickness (NW height: HNW)under the HfSiON/TiN gate is 12 nm. HNW, WNW, and LG

reported in this letter result from ellipsometry measurements,scanning electron microscopy, and TEM images. After gateetching, a SiN layer (thickness 10 nm) was deposited andetched to form a first spacer on the sidewalls of the gate.18-nm-thick Si raised S/D was selectively grown at 750 °C,20 torr, for the Si reference transistors before the S/D exten-sion implantation and activation annealing. For SiGe S/D,two 650 °C schemes were used and benchmarked thereafter:1) a straightforward SEG of in situ boron-doped Si0.7Ge0.3:Braised S/D ([B] = 2 × 1020 cm−3) or 2) the in situHCl + GeH4 etching of a few nanometer of Si (estimated to

0741-3106 © 2013 IEEE

1104 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

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Fig. 2. ISAT versus VTSAT of P-FET multifin SoI NW. For WNW ∼ 25 nmand LG ∼ 25 nm, the combination of in situ HCl + GeH4 etching andSi0.7Ge0.3:B SEG (both at 650 °C, 20 torr) yields the best performances(open circles).

4 nm) followed by the SEG of Si0.7Ge0.3:B for the formationof recessed S/D. Then, a second spacer was formed beforeS/D implantations, activation spike anneal, and salicidation(NiPtSi).

III. RESULTS AND DISCUSSION

In this section, the interest of using recessed (r ) and raisedSi0.7Ge0.3:B S/D in 〈110〉 P-FET NWs is discussed.

The comparison of these integrations is done by plottingthe saturation current ISAT (extracted at VDS = VGS = 0.9 V)as a function of the threshold voltage (VTSAT) (Fig. 2). Thesaturated threshold voltage (VDS = 0.9 V) is extracted usingthe constant current method at 100 nA ×W/LG with W =2 × HNW + WNW. The relevance of using SiGe:B S/D comesfrom: 1) the carrier mobility enhancement induced by the uni-axial compressive strain in the channel and 2) the improvementof access resistance induced by the SiGe layer and the highboron doping levels. For long gate lengths, the compressivestrain effect diminishes in the channel and the impact of S/Dresistances becomes negligible. No ISAT improvement is thenachieved. For short gate lengths, SiGe:B S/D improves ISATcompared with Si S/D (Fig. 2). The combination of in situ HCletching with the SEG of B-doped Si0.7Ge0.3 further, however,improves electrical performance and slightly reduces VTSAT.The increase of uniaxial compressive strain in the channel iscoming from the use of recessed S/D SiGe stressors may bea promising option for SoI NW technology. The IOFF–ISATtradeoff of P-FET NW with recessed SiGe:B S/D and controlSi S/D is shown in Fig. 3(a).

The IOFF current is extracted at VGS = 0 V and VDS =0.9 V. An ISAT improvement of +100% induced by the SiGeS/D is observed. The saturation current enhancement is evenmore important when the gate length is reduced. Fig. 3(b)shows the total device resistance as a function of the gatelength. The extracted S/D extrinsic series resistances (RSD) forrecess SiGe and Si S/D are 300 and 530 � μm, respectively.The 44% RSD reduction is not enough to explain the saturationcurrent enhancement. The hole effective mobility of short-channel transistors being inversely proportional to the slope ofd Rtot/d LG , Fig. 3(b) shows an improvement of hole mobility

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Fig. 3. (a) ISAT–IOFF plot of P-FET single-fin NW with Si and recessedSiGe:B S/D. +100% ISAT improvement coming from strain is achieved.(b) Total device resistance as a function of the gate length (VGS = 1.2 V).

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WNW=19nmHNW=11nmDIBL=138mV/VSS=80mV/decIon=610µA/µmIoff=1.8nA/µm

LG=13nmNormalized with Weff=2HNW+WNW

Fig. 4. Transfer characteristics for a 13-nm gate length P-FET Omega-gateNW with recessed SiGe:B S/D.

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Fig. 5. ISAT current enhancement of P-FET multifin NW induced by recessedSiGe:B S/D. (+100% for narrow NW versus +40% for wide planar FET).Inset: ISAT current enhancement versus the SiGe:B thickness (no recess beforeepitaxy). As the thickness of SiGe:B raised S/D increases, the performanceof P-FET SoI NWs is enhanced from +50% to +70%.

due to the recessed SiGe S/D. This directly results from theuniaxial compressive strain in the channel.

The IDS(VGS) curves for an 13-nm gate length P-FET NWwith recessed SiGe:B S/D are shown in Fig. 4. A saturationcurrent ISAT = 610 μA/μm is achieved with a low IOFFcurrent (1.8 nA/μm). The NW width is also expected tohave a large impact on performance due to the change ofmobility in 〈110〉 NWs. Through reducing the NW width, alarge mobility improvement induced by a significant increaseof subband curvature and hole velocity is expected [14].The efficiency of recessed S/D SiGe:B stressors for narrow-channel transistor is well shown in Fig. 5. The results show

BARRAUD et al.: ENHANCED PERFORMANCE OF P-FET OMEGA-GATE SOI NANOWIRE 1105

a major improvement of the saturation current from +40%for wide planar transistors up to +100% for narrow NWtransistors. The high efficiency of uniaxial compressive strainin 〈110〉 NWs has been explained with an atomistic tight-binding approach [15]. Compressive strain strengthens thelight subbands of the highest valence subbands, pushing heavyholes subbands down. This leads to a higher average holevelocity and induces an improvement of the saturation current(×2) along the 〈110〉 direction. In Fig. 5 (inset), the saturationcurrent enhancement is shown as a function of the epitaxialSiGe:B film thickness. The saturation current is extracted at|VGS–VT | = 0.65 V and LG = 25 nm. The performance ofP-FET NW is enhanced as the SiGe:B S/D becomes thicker(from 13 to 20 nm), from +50% up to +70% due to anincrease of compressive strain [16], [17].

IV. CONCLUSION

The effectiveness of SiGe S/D has been evaluated byinvestigating the ION–IOFF tradeoff of short-channel Si P-FETNW transistors. Raised S/D using in situ B-doped Si0.7Ge0.3and in situ HCl + GeH4 etching followed by the SEG ofB-doped Si0.7Ge0.3 (recessed S/D) have been benchmarkedversus standard Si raised S/D. Recessed SiGe:B S/D improvedthe ISAT current even more than raised SiGe:B S/D. The sat-uration current improvement (compared with Si S/D) reached+100% for LG = 13 nm. A thick SiGe:B film is also favorableto enhance the uniaxial compressive strain in the channel from+50% (13 nm) to +70% (20 nm).

ACKNOWLEDGMENT

The authors would like to thank the LETI facilities fordevice processing and SOITEC for providing SoI substrates.

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