Encoders and Decoders

Encoding

• Suppose we have 8 input signals and only one amongst them is active at any point in time.– Clearly we can have 8 bits to represent this and have only 1 bit set. – But this would necessitate 8 wires going all the way to the part of the

circuit using this information.

• Can we be more efficient in the number of bits? And therefore save on the wiring?

• Binary logic allows us to use just 3 bits to signal which of the 8 input lines were active. – Log2 8 = 3

8 to 3 encoder TT

Priority is given to the most significant bit that is high.

Encoder Logic

Decoding

• Complimentary to encoding• Select one of k output lines to be high based

on the ln k bit input. • Fun challenge: Can you design a full adder

using a decoder?

Full Adder with a DecoderA

(Addend)

B (Augend)

Cin Sum Carry Out

0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1

Fs = Σ m (1,2,4,7)

Fco = Σ m (3,5,6,7)

3 to 8 Decoder

Enable signal – If its 1, it cuts off power to the IC – electrically disconnect without unplugging

Multiplexers (MUX)

• Motivation – cost/function is not linear– => 100 gates does not cost 10 times as much as 10

gates (in fact, far less – perhaps 1.1). – This motivates us to build larger circuits on a

single chip rather than raw gates on it (pin issues).– Often called MSI/LSI/VLSI.

• Encoders/Decoders are examples• So is a multiplexer

MUX

• Switches in one of the inputs to the output based on selector inputs.

4 to 1 Mux

i0

i1

i2

i3

s0 s1

F = S1’S0’i0+ S1’S0 i1+ S1 S0’i2+ S1 S0 i3

Application? Telephony!

FA with Mux?0 11 00 11 0

Ci

AB00

0111

10

0 1

K Map for Sum (S)

0 0

0 1

1 1

0 1

AB00

0111

10

0 1

K Mapfor Cout

• When AB=00, the SUM is just Ci, so connect Ci to i0. Similarly …

• Connect i1 to Ci’• Connect i2 to Ci’• Connect i3 to Ci

• When AB=00, the Cout always 0. • Connect i1 to Ci• Connect i2 to Ci• Connect i3 to 1

AB becomes our control signal to the Mux

FA With Mux

A

B

Cin

0

Challenge

• The chief challenge is to match the requirements to the capabilities of the devices that are out there. – Most muxes come as 2 Muxes to an IC from which

we can make a full adder.

• Almost ANYTHING with a 3 or 4 variable K Map can be done with either a 4 to 1 or 8 to 1 Mux.

Programmable Logic Arrays

Multi Purpose

• Imagine a circuit which could realize any truth table you want and perhaps even different truth tables at different times!

• Similar to microprocessors, PLAs are “reconfigurable” – Not as flexible as microprocessors – Programmability on a smaller, less complex scale.

• Another approach to constructing logic– Different from gate level design

• PROMs, EPROMs etc. are examples of PLAs.

Approach

• Think of a TT as a hashmap

• The key is the input • The contents of the

memory location indexed by the key is the output

000 ….

001 …

010 1000

011 1100

100 …

101 …

110 1101

111 1100

InputsOutputs

• So, what is reconfigurable about this?• The ability to change the

contents of the cells on the RHS of the TT

Persistence?

• Wont the contents of this memory get erased when the device is powered off?

• UVEPROM, Flash - examples of persistent memory.

• Electronically alterable or with UV Radiation.

Now for the logic

3 Inputs – X0 to X2

Realizing Minterms with ANDarray

The TT we want

x2 x1 x0z1 z0

0 0 00 0

0 0 11 0

0 1 00 0

0 1 11 0

1 0 01 1

1 0 10 0

1 1 00 0

1 1 10 1

Wiring the AND array for the 4 Minterms we want

Minterms:x0 x1’ x2’x0 x1 x2’x0’ x1’ x2x0 x1 x2

Now for the outputs

Z0 = Σ m(4, 7)Z1 = Σ m(1, 3, 4)

OR Array for the outputs

“Programming a PLA”

• What does it mean to program a PLA? • See the black dots? Those are connections

made between wires. In effect "programming" the wires means to make the connections within the PLA.

• Configurable might be a better word than programmable, but that's the name that stuck.

Size of a PLA?

• Given n variables, it would seem necessary to have 2n vertical wires (for the AND gates), one for each possible minterm.

• However, this grows VERY quickly. So, sometimes there aren't 2n vertical wires.

• m OR gates for m outputs

Sequential Logic

Two kinds of logic

• Combinational logic – implement boolean expressions

• Sequential Logic – Adds an element of “feedback” – The outputs not only depend on the present inputs

but on past behavior. – Needed for many situations – traffic controller

• We need to remember the state we are in before we transition to another state.

• If the light is green and 90 seconds have passed, change the light to Yellow.

Combinational Logic ++

CombinationalLogicBlock

Memory

Feedback Loop

Latches and Flip Flops, Clocks

Basic Building Blocks of Memory - Latches

A Basic NOR LatchIncorporates feedback – what does it do?

Start with S = 1 and R = 0Then Q’ = 0 and Q = 1

Now make S = 0 and R = 0then Q’ remains 0 and Q remains 1

Now make S = 0 and R = 1then Q becomes 0 and Q’ will

become 1

Again make S = 0 and R = 0 (with Q = 0 and Q’ = 1)then Q remains 0 and Q’ remains 1

(contrast this with case 2 above)

• Case 2 and 4 have identical inputs but have different outputs because of the memory derived from case 1 and 3 respectively.

• What happens if I make both S and R be 1?– Q and Q’ are both 0 which makes no sense.

• If I now make S= 0 and R= 0 I can get either:– Q = 0, Q’ = 1– Q = 1, Q’ = 0– Depending on which gate you analyze first or “fires” first.

• Hence the output of the latch when S = R = 0 AFTER S = R = 1 is unreliable and should not be used.

TT of the SR Latch

S R Q Q’

0 0 Memory State (As before)

0 1 0 1

1 0 1 0

1 1 Not Used state

Regardlessof previousState

S is the setting inputR is the Resetting input

S-R Latch with Nand

Note the inputs arecomplements of the inputs forthe NOR latch

What if we did not have the complemented inputs?

The TT changes accordingly:0,0 will be the “not used” state and 1,1 will be the memory state

Issues with the design

• The “not used” state is confusing.• Why should I give two inputs to store 1 bit???• When the input changes (because of whatever

reason) the outputs can change even though I may not want the change.– Variations in input signals. – I don’t really have control over the persistence of

memory. • Latches are therefore only the building blocks of

memory

Clocked Latches or Flip Flops

• Incorporates a control mechanism to ensure that only when the control is high are any latch inputs accepted.

Why are clocks really useful?

• It allows us to synchronize multiple parts of a circuit and smooth out the difference in performance of various stages.

• It allows us to sequence a set of operations.

• The latch’s state can be changed only when the clock is high.

• But remember there are gate delays!

• The trick is to have the inputs be ready just before the clock goes high so that the inputs are applied when the clock goes high and then you have the entire high part of the cycle as the delay tolerance of the circuit.

• What should be the frequency or clock period of the clock?– The smallest period is decided by how long the latch needs

to process the input.

Avoiding the 1-1 input state

S-RFlip Flop

D

Clock

Q

Q’

D (for Data) Flip flop – the simplest 1 bit storage element

Can we use the wasted (not used) state?

• We have added a stage of gates to the SR Flip Flop

• What happens when:• Clk=1, J=K=1?

• Assume initially:• Q=1, Q’=0• Output changes

to 0,1 from 1,0• How about when:

• Q=0, Q’=1• Output changes

to 1,0 from 0,1

So, when Clk=1, and J=K=1 the output races between 0 and 1 with a frequencythat depends on the gating speed. Now if only we could control this race!

Master Slave JK Flip Flop

Two Flip flops with:a) Complementary clocks and b) one feedback from output of the second stage to input of the first stage

What does this do?

A Toggling Flip Flop

What happens if we take a JK flip flop and tie the two inputs together?

• When the CLK = 0, its in Memory State and the input does not affect it

• When the CLK = 1 and T = 0 its ALSO a Memory State. • When the CLK = 1 and T = 1 , it will be in Toggle state, toggling

once every (rising edge or falling edge of the) clock cycle.

Registers

Memory

• A latch is a simple 1 bit storage element. • We can string a set of D latches together to make a

higher order storage element.

• The issue: To keep the data for a while, I must turn the clock off after storing the data

• But the clock in the computer is common and is of a much higher frequency than what persistent storage needs

Persistence Behavior• We need an independent

control to keep the data around.

• Desired behavior: Set when the data is available and then store in it.

• Needs an additional control input– Write Enable or Load

Clearing a register

• Similar to controlling when data gets loaded, we can also control when data gets cleared so that junk is not read unintentionally off the register.

• Think about how to do this…

Shift Registers• In the registers we have seen so far, inputs and outputs are

fed in and read in parallel • There may be situations involving serial I/O devices that

need a serial stream of bits to be stored and then read in parallel (and vice versa)

Modes of Operation

Serial O/P Parallel O/PSerial I/P SISO SIPO

Parallel I/P PISO PIPO

• Load and clear controls still exist as before. • Registers which offer all modes are called Universal

Shift Registers

State Machines

What are SMs?

• A set of states• A set of transitions

triggered by events

A more complex example – the TCP Protocol State Machine

Many examples

• Traffic light controller• Elevator controller• Airplane takeoff controller etc. etc. • In each state, the SM can produce an output. • We can also think of a SM as a clocked

sequential circuit. – A 2 bit counter – has 4 states (00, 01, 10, 11) and

cycles through these states with a clock pulse.

Representing a SM

Input X

CLK to triggerthe transition

Output Z

Current State (2 bits)

Memory(D FFs)

Counter as a state machine

• A counter cycles through a sequence – usually contiguous.

• However, lets do something different• Our counter:– 6 states – S0 – S5– Sequence: [1,4,3,5,2,6] cycling back to 1 after 6.– How many state variables?• 3 for 6 states.

States

A B C

S0 0 0 1

S1 1 0 0

S2 0 1 1

S3 1 0 1

S4 0 1 0

S5 1 1 0

S2

S0 S1

S3S4

S5

• 3 State Variables (A, B, C)• No external Inputs in this case

CLK to triggerthe transition

Current State & Output (3 bits)

D0

D1

D2

Q0Q1

Q2

Counter Combinationallogic

A, B, C

A+, B+, C+

How about the combinational logic?A B C A

+B+

C+

0 0 0 X X X0 0 1 1 0 00 1 0 1 1 00 1 1 1 0 11 0 0 0 1 11 0 1 0 1 01 1 0 0 0 11 1 1 X X X

X 01 01 X1 0

A

00

0111

10

0 1

K Map for A+

BC

A+ = A’

Similarly B+ = AB’ + A’C’ andC+ = AC’ + BC