Enabling MIPI Physical Layer Test - Keysight · LTE WiMAX Wireless Domain Digital ... • SQL data...

Enabling MIPI Physical Layer Test

July, 2008

High Speed Digital Test


High Speed Test and Characterization


July, 2008

The Explosion of Functions within Mobile Devices

Multiple RF functions– GPS– Bluetooth– WCDMA– GSM– WLAN– FM

Multiple Peripherals– Camera– Display– Audio in /out– Mobile TV – DVB-H – Other IOs

Request for more bandwidth

High speed serialization

Digitization of IQ

Power Management


July, 2008

Emergence of Standard Digital InterconnectsFrom Analog to Digital

Wireless Handset

RF IC

BB IC

AP

LTE

WiMAXWirelessDomain

DigitalDomain

Mobile Industry specific

standards

Standards inherited from the computer industry

MIPIDPHY DSI

MIPIDPHY CSI

DigRF

The Digital Interface• Is easier and cheaper to implement • Will consume less battery power• Provides higher bandwidth• Reduces the number of IC pins• Allows for easier “plug and play”

between devices

BUT

• Breaking the GBit barrier requiresdedicated jitter stress test – on clock and data separately

• Power safe requires wake up and therefore different signal extremes, low power and high speed


July, 2008

Agilent Solution Offering

Wide Band OscilloscopeBERT

Digital Protocol Layer Debug / Validation

Digital Physical LayerDebug / Validation

Wireless ProtocolLayer Validation

Wireless Physical Layer Validation

Dig

ital D

omai

nW

irele

ss D

omai

n

Dig RF testerProtocol Viewer

Pulse Function Arbitrary Noise Generator


July, 2008

The MIPI Evolution

Test & Debug Port

BB-IC debug ports Shared pins

Physical layers

DigRF v3

MIPI DPhy

MIPI MPhy

Protocol layers

DigRF v3

DSI Display

CSI Camera

Unipro Other

DigRF v4

Status

- Shipping today

- In development

- DPhy is in definition, almost final

- Physical layer solution volume Shipment Oct 08

- MPhy definition to start end of the year

- DPhy Solution also requires Logic Analyzer. Minor adaptations to configuration are possible because standard is not defined yet!


July, 2008

BB-IC RF-IC

Camera

MIPI D-Phy MIPI D-Phy CSI

MIPI D-Phy DSI

WiMAX

DigRF v3

2.5G3GPP

RXRX

TXTX

RXTX

TX

RX

How to Get Confidence on the Physical LayerCharacterizing the ParametersTX Tests:Data bus timing

Transition times

DC levels and AC swing

Low Power / High Speed mode switching

Jitter

RX Tests:Data bus timing

Min. pulsewidth

Sensitivity (min/max amplitude)

Jitter Tolerance on Clock and Data

Differential and common mode, termination switching

TimingSignal

IntegrityLevels


July, 2008


Low PowerSignaling

Low PowerSignaling

High SpeedSignal

Enabling MIPI D-PHY Physical Layer TestControl the transition

The ParBERT 81250A

- Generates the signal you need- Controls the sequences - Forces the bus through low to high speed transition and vice versa

- Glitch free change of timing parameters

MIPI D-PHY operates in two modes with dynamic transitions

Low Power Signal- Max 20 Mbit-Single ended

- CMOS

High Speed Signal- > 1 Gbit

-Differential-LVDS


July, 2008


Enabling Physical Layer Test – Bit Error TestingStress your device to its limits

RXBit

Error Ratio

Expected Data

Compare

Generator Solution

Data AnalyzerError Detector

DeviceUnderTest

Stress

RX Tests: Sensitivity and jitter tolerance on clock and data

- For several lanes at least 2 data and clock- Devices show immunity at combined jitter testing; data and clock

needs to be tested independently- For all kinds of jitter and stress test- Jitter injection from 81150A via delay line to the ParBERT 81250A


July, 2008July 3, 2008

N5990A Test Automation Software and MIPI Frame Generator

One button Rx and Txcompliance tests and characterization

• MIPI D-PHY Editor• Pre-canned test pattern• Calibrated test cases• Easy post processing• SQL data base interface• Interaction with legacy

code

Enabling MIPI D-PHY Physical Layer TestCharacterization at your fingertips

Next Level of Performance and Convenience through Test Automation


July, 2008


The Stimulus Test Setup• Full coverage of stimulus signal generation with flexible signal conditioning• Full Stress / Jitter tolerance testing• Modular configuration for 1, 2 or multiple lanes• Test Automation Software with MIPI Editor and pre-canned test pattern• Multi-application support by ParBERT platform (e.g. HDMI)• Depending on device design, full BER Analysis possible

Multi Application Tester 7 Gbit/s

81150A Noise / Jitter source

81250A ParBERT

N5990A Test Automation Software

E4438C Signal Generator / clock source

Economic High speed Tester3.35 Gbit/s

81150A Noise / Jitter source

81250A ParBERT

N5990A Test Automation Software


July, 2008


Agilent MIPI D-PHY Physical Layer Test

Agi

lent

812

50A

Par

BER

TA

gile

nt 8

1150

A N

oise

Sou

rce

Low PowerSignaling

Low PowerSignaling

High SpeedSignal

Generate the signal you need

Control and synchronize transitions between different modes and channels

Ease-of-use through test automation

N59

90A

Tes

t A

utom

atio

n S

oftw

are

High Speed From nominal to

stress test

Multiple Lanes with separate Clock

and Data

Transition between LP and HS

is critical


July, 2008

Appendix

Test Details


July, 2008

BB-IC RF-IC

Camera

Display

MIPI D-Phy

MIPI D-Phy CSI

MIPI D-Phy DSI

RXRX

TXTX

RXTX

TX

RX

MIPI M-Phy

Provide Access Point and Method by Design /

Standardization

Design For Testability


July, 2008July 3, 2008

Recommended ParBERT MIPI D-PHY Configurations

Configurations vary in max data rate and jitter injectioncapabilities:

3.35 GBit/s economic with 500 ps jitter injection capabilityThe maximum data rate of 3.35 GBit/s limits the usage of ParBERT

modules for other standards respectively applications

7 GBit/s multi-application setupWith 7GBit/s ParBERT modules the setup can support a wider range of

standards and applications


July, 2008July 3, 2008

Jitter Injection Capabilities of ParBERT Configurations

Economic Solution Multi-application solutionSeparate jitter on clock and

data lanesPossible –

setup suggests clean clock lane and jitter on data lanes only

Possible –setup suggests clean clock lane and

jitter on data lanes onlyJitter capabilities

500ps delay line 200ps delay line plus jittered ParBERT clock (see below)

Externally jittered ParBERT clock

Not possible Data rate dependent – example

at 1 GBit/s

Max supported jitter

Data

Clock

500ps

500ps (capability not used in setup)

Jittered Clock + 200ps

Jittered Clock + 200ps(capability not used in setup)

.4 4 40 MHz

UI

787

.15


July, 2008July 3, 2008

Noise Generation Capability of ParBERT Configurations

Same for economic and multiple application setups

Suggest to test either noise or jitter at one timeuse the same equipment for both and change setup(parallel test would require more accessories)

Perform noise test only on one lane at a timein a setup with mutliple data lanes this means to test all lanes

sequentially and change setup in-between(parallel test would require more accessories)


July, 2008July 3, 2008

Economic ParBERT 3.35 GBit/s System Configuration –Single Lane Shown

LP Signal GenerationTrigger Out Start In

Data Out

11667BPwr Splitter

D-PhyClock or Data Lane

HS Signal Generation

675MGenerator

675MGenerator 3.35G

Generator3.35G

Generator

675MGenerator

675MGenerator

internal channel add internal channel addData OutData OutData Out

15432B250ps

TransitionTime

Converter

+ -

15438A2ns

TransitionTim

eC

onverter

Scope Trigger

DelayControl In

1250-1159 Adapter

Lane 1

Lane 1

Lane 2

Lane 2

Jitter Generation(4 lanes shown)

all SMA cables15442-61601

81150A opt 002

1250-2015Adapter

81150A opt 002

Lane 3

Lane 3

Lane 4

Lane 4

81150A opt 002

8493C6dB

8493C6dB

11667BPwr Splitter

11636BPwr Divider

11636BPwr Divider

11636BP

wrD

ivider

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

15432B250ps

TransitionTime

Converter

11636BP

wrD

ivider

15438A2ns

TransitionTim

eC

onverter

1250-2015Adapter

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

NoiseGeneration

1250-1159 Adapter


July, 2008July 3, 2008

Economic ParBERT 3.35 GBit/s System Summary1 clock

1 data lane1 clock

2 data lanes1 clock

4 data lanes Comments

Signal Generation4x 675MBit/s generators 1x E4832A with 4x E4838A 2 3 5 LP signaling and HS offset2x 3.35GBit/s generators 1x E4861B with 2x E4862B 2 3 5 HS signaling250ps transition time converter 15432B 4 6 10 HS transition time2ns transition time converter 15438A 4 6 10 LP transition time, 3rd part productpower splitter 11667B 4 6 10 combine HS and LP signalsset of 4 SMA cables 15442-61601 3 5 (2 cables not used) 8 (2 cables not used) signal connect

Other ParBERT Itemsclock module E4808A 1 1 1 HS clockclock module E4805B 1 1 1 LP clockParBERT mainframe 81250A-149 1 1 1IEEE 1394 PC link to VXI 81250A-013 1 1 1ParBERT 81250 software license E4875A 1 1 1 softwareLaptop including PCMCIA IEEE 1394 card 81250A-015 1 1 1 PC to operate the setup power divider 11636B 1 1 1 split LP trigger out to HS and scope set of 4 SMA cables 15442-61601 1 (1 cable not used) 1 (1 cable not used) 1 (1 cable not used) trigger signals

Jitter Generation81150A with two channels 81150A, option 002 1 1 2 noise generatorBNC to SMA adapter 1250-2015 1 1 2 81150 output adapterSMA to SMA adapter 1250-1159 0 2 4 connect power dividerspower divider 11636B 1 3 6 split noise to ParBERT delay linesset of 4 SMA cables 15442-61601 1 (1 cable not used) 2 (3 cables not used) 3 (2 cables not used)

Noise Generation (one lane - use equipment for jitter generation)power divider 11636B 2 0 0 re-use power divider for jitter generation6dB attenuator 8493C 2 2 2SMA to SMA adapter 1250-1159 2 0 0 re-use adapter for jitter generationBNC to SMA adapter 1250-2015 0 0 0 re-use adapter for jitter generationset of 4 SMA cables 15442-61601 0 0 0 re-use cables for jitter generation

Other9GHz or better DSO 90000 Scope options t.b.d 1 1 1differential probe 1169A 2 2 2 timing and level measurement with DSOdifferential probe head 5380A 2 2 2 timing and level measurement with DSOhigh impedance probe head t.b.d 2 2 2 level measurement with DSO

Control Software and Test Automation N5990A option t.b.d 1 1 1 control softwareLAN hub no Agilent part 1 1 1 remote control instrumentsLAN cable no Agilent part 3 3 4 remote control instrumentsset of 4 SMA cables 15442-61601 1 (2 cables not used) 1 (2 cables not used) 1 (2 cables not used) to connect scopeset of 4 SMA cables 15442-61601 -1 -2 -1 balance unused SMA cables


July, 2008July 3, 2008

Multi Application ParBERT 7 GBit/s System Configuration – Single Lane Shown

LP Clock and Data SystemStart InStart In

clean clockESG 1 ESG 2

clock w SJ

HS Clock System

7GGenerator

7GGenerator

HS Data System

675MGenerator

675MGenerator 7G

Generator7G

Generator

675MGenerator

675MGenerator

internal channel add internal channel add

DelayControl In

1250-1159 Adapter

Lane 1 Lane 3Lane 4Lane 2

Trigger Out

ScopeTrigger

1250-1159 Adapter

10 MHz1250-1744 Adapter

1250-1743 Adapter

Clock In Clock In Clock In

to D-Phy Clock Lane(LP clock generation

not shown)

8120-1839 BNC cable

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

Data Out

11667BPwr Splitter

D-PhyClock or Data Lane

Data OutData OutData Out15432B250ps

TransitionTime

Converter

+ -

15438A2ns

TransitionTim

eC

onverter

81150A opt 002

8493C6dB

8493C6dB

11667BPwr Splitter

11636BPwr Divider

11636BP

wrD

ivider

15432B250ps

TransitionTime

Converter

11636BP

wrD

ivider

15438A2ns

TransitionTim

eC

onverter1250-2015Adapter

NoiseGeneration

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

11636BPwr Divider

81150A opt 002

Random Jitter Generation(4 lanes shown)

1250-2015Adapter

1250-1159 Adapter


July, 2008July 3, 2008

Multi Application 7GBit/s System Summary1 clock,

1 data lane1 clock,

2 data lanes1 clock,

4 data lanes Comments

Signal Generation4x 675MBit/s generators 1x E4832A with 4x E4838A 2 3 5 LP signaling and HS offset7GBit/s generator N4874B 4 6 10 HS signaling250ps transition time converter 15432B 4 6 10 HS transition time2ns transition time converter 15438A 4 6 10 LP transition time, 3rd part productpower splitter 11667B 4 6 10 combine HS and LP signalsadapter 3.5mm(f) to 2.4mm(m) N4911A-002 8 12 202.4mm 50 Ohm termination N4912A 8 12 20 terminate unused outputs of 7G ParBERT3.5mm 50 Ohm termination 1250-2206 4 6 10 terminate unused outputs of 7G ParBERTset of 4 SMA cables 15442-61601 3 5 (2 cables not used) 8 (2 cables not used) signal connect

Other ParBERT Itemsclock module E4809A 2 2 2 HS clockclock module E4805B 1 1 1 LS clockParBERT mainframe 81250A-149 1 1 1IEEE 1394 PC link to VXI 81250A-013 1 1 1ParBERT extender mainframe with IEEE1394 link 81250A-152 0 1 1ParBERT 81250 software license E4875A 1 1 1Laptop including PCMCIA IEEE 1394 card 81250A-015 1 1 1 PC to operate the setup BNC cable 8120-1839 1 1 1 synchronize ESGspower divider 11636B 3 3 3 clock and triggeringESG E4438C, options 1E5, 506, 601 2 2 2 signal generatorsadapter n to 3.5mm (m) 1250-1743 1 1 1 ESG output to power divideradapter n to 3.5mm (f) 1250-1744 1 1 1 ESG output to SMA cableSMA to SMA adapter 1250-1159 1 1 1 combine power splitters for triggeringset of 4 SMA cables 15442-61601 2 (1 cable not used) 2 (1 cable not used) 2 (1 cable not used)

Jitter Generation81150A with two channels 81150A, option 002 1 1 1 noise generatorBNC to SMA adapter 1250-2015 1 2 2 81150 output adapterSMA to SMA adapter 1250-1159 0 0 4 connect power dividerspower divider 11636B 1 2 6 split noise to ParBERT delay linesset of 4 SMA cables 15442-61601 1 (1 cable not used) 2 (2 cables not used) 3 (2 cables not used) 1, 2 or 4 needed to distribute noise

Noise Generation (one lane - use equipment for jitter generation)power divider 11636B 2 0 0 re-use power divider for jitter generation6dB attenuator 8493C 2 2 2SMA to SMA adapter 1250-1159 2 0 0 re-use adapter for jitter generationBNC to SMA adapter 1250-2015 0 0 0 re-use adapter for jitter generationset of 4 SMA cables 15442-61601 0 0 0 re-use cables for jitter generation

Other9GHz or better DSO 90000 Scope options t.b.d 1 1 1differential probe 1169A 2 2 2 timing and level measurement with DSOdifferential probe head 5380A 2 2 2 timing and level measurement with DSOhigh impedance probe head t.b.d 2 2 2 level measurement with DSOControl Software and Test Automation N5990A option t.b.d 1 1 1LAN hub no Agilent part 1 1 1 remote control instrumentsLAN cable no Agilent part 5 5 5 remote control instrumentsset of 4 SMA cables 15442-61601 1 (2 cables not used) 1 (2 cables not used) 1 (2 cables not used) clock to data skew measurement with DSOset of 4 SMA cables 15442-61601 -1 -1 -1 balance unused SMA cables


July, 2008

Combined D-PHY High Speed And Low Power SignalGenerated by ParBERT


July, 2008

Transition Details: High Speed Signaling to Low Power Signaling


July, 2008

Voltage Levels as defined

880mV

550mV

-40mV

460mV

330mV

70mV

1300mV

-50mV

50mV

1100mV

1300mV

880mV

550mV

450mV

200mV

max Differential input high threshold VIDTH = 70mVmin Differential input low threshold VIDTL=-70mV


July, 2008

MIPI D-PHY Application Programming Tool for simple editing of data rate, pattern, timing and levels


July, 2008

How Does D-Phy Compliance Test Work…

BaseSpecification

defines

ComplianceTest

Specification(CTS)

defines

subcontractCTS is based onmain specification

loan equipmentfor CTS developement

workwith

industryleaders

Methodof

Implementation(MOI)

owner

MOI is based onCTS

generictestdescription

how to dotest withspecificinstrument

defines

MIPI Standard Workgroup(key industry players, including

Agilent, lead the effort)

University of New Hampshire

Interoperability Lab (UNH-IOL)

Agilent(LPT, DVD, HSDT)

Protocoltester

Scopes BERTs


July, 2008July 3, 2008

N5990A Test Automation Software and MIPI Frame Generator

One button Rx and Txcompliance tests and characterization

• MIPI D-PHY Editor• Pre-canned test pattern• Calibrated test cases• Easy post processing• SQL data base interface• Interaction with legacy

code

Enabling MIPI D-PHY Physical Layer TestCharacterization at your fingertips

Next Level of Performance and Convenience through Test Automation


July, 2008

ParBERTClock System

ParBERTHS Data System

ParBERTLP Data System

ESG 1 ESG 2Clock (clean) Clock (SJ)

Trigger OutStart InStart In

10 MHz

• 1 BNC cable for 10 MHz synchronization• 4 SMA cables for clock distribution + 1 power divider• 5 SMA cables for trigger distribution + 2 power dividers

ParBERT System ConfigurationTiming and Trigger, based on 7 Gb/s data modules

To Scope Trigger


July, 2008

ParBERT System ConfigurationHigh Speed Jitter Distribution, based on 7 GBit/s data modules

ParBERTClock System

ParBERTHS Data System

ParBERTLP Data System

ARB

To Delay Control Inputs

Power Divider

• 1 BNC-to-SMA adapter• 7 SMA cables• 3 power dividers


July, 2008


Enabling MIPI D-PHY Physical Layer TestHigh Speed Test and Characterization with Agilent 81250A ParBERTAgilent 81150A Pulse Function Arbitrary Noise GeneratorAgilent N5990A Test Automation Platform

3 Reasons to go with 81250A:

1.Full coverage of stimulussignal with flexible & modular signal & stress generation

2.Easy-to-use MIPI D-PhyEditor and Test Automation including pre-canned test pattern

3.Depending on device design, full BER analysis possible

81150A Noise Source -


July, 2008

Agilent Restricted

July 3, 2008

MIPI Test SoftwareN5990A Test Automation and

MIPI Frame Generator

• Features and Pattern


July, 2008July 3, 2008

OverviewMIPI Frame Generator N5990A-362

Manual Test Tool for MIPI Receiver Testing using the 81250A as a generic MIPI Stimulus


July, 2008July 3, 2008

Features

Included:• Automatically setting up the 81200A for generating MIPI

conformance signals and pattern• Modify HS and LP pattern• Modify Data Rates of HS and LP transmission• Modify Timing between LP and HS data transfer switching• Modify Voltage Levels• Adding Jitter to HS data

Not included:• Measure and analyze bit error ratio• Generate complete video frames for testing displays• Switching between Receiver and Transmitter mode • PPI capability for DUT control


July, 2008July 3, 2008

Pattern Capabilites

(beta)= already available in beta version end of March(final)= will be part of the final version

Pure LP pattern transmission (beta)Pure HS pattern transmission (beta)Predefined pattern (high transition density, low transition

density, lonely 0/1 bit, PRBS) (beta)Integrated protocol layer for LP-HS-LP transmission with

variable timing (beta)LP Triggers (Table 8 MIPI Spec): Low-Power Data

Transmission, Ultra-Low Power State, Reset-Trigger (final)Programmable Escape Mode State Machine (final)User-defined pattern for LP and HS data separately

(transmission switch protocol will be automatically added by the software)

Integrated 8/9 bit coding


July, 2008July 3, 2008

OverviewN5990A Test Automation Software

• Full test automation (Rx, Tx, Rx test system calibration)• Generic, common N5990A user interface• On- button compliance tests and expert mode for characterization,

debugging and margin test• Open, modular software platform• N5990A-010, -160, -260, -361 (-001 and -500 recommended)


July, 2008

ParBERT 81250A System ConfigurationJitter Injection Capabilities (1)Economic solution (based on 3.4 Gb/s generator)• 500 ps delay line, 200 MHz bandwidth• All jitter types as available from 81150A (RJ, SJ, custom)

Multi – application solution (based on 7 Gb/s generator)• 200 ps delay line + SJ from ESG• Delay line can create any jitter type as available from 81150A


July, 2008

Generated Pattern

All measurements done into 50 Ohms

Low-power = 10MHz, high-speed = 1GHz


July, 2008

D-Phy Timing

MIN: 50ns

MAX: 35ns+4*UI

MIN: 40nsMAX: 55ns+4*UI

MIN: max{n*8*UI, 60ns+n*4*UI}

MIN: 100ns

MAX: 105ns+n*12*UI

n=1 forward direction HS moden=4 backward direction HS modeUI: 1GB/s = 1ns

MIN: 40ns+4*UIMAX: 85ns+6*UI

MIN: 145ns+10*UI-THS-Prepare

MAX: 35ns

1GB/s: UI=1nsHS-PREPARE:

MIN: 44nsMAX: 91ns

HS-ZERO:MIN: 64ns = 145ns+10*1ns-91ns

• Wide range of flexibility


July, 2008

THS-Prepare


July, 2008

THS-Zero


July, 2008

THS-Trail


July, 2008

Voltage Levels

880mV

550mV

-40mV

460mV

330mV

70mV

1300mV

-50mV

50mV

1100mV

1300mV

880mV

550mV

450mV

200mV

max Differential input high threshold VIDTH = 70mVmin Differential input low threshold VIDTL=-70mV


July, 2008

VOH-Max >1.2V with 3dB Attenuators


July, 2008

High Speed Offset Example 1: 47mV


July, 2008

High Speed Offset Example 2: 198mV


July, 2008

Transition Details: Low Power Signaling to High Speed Signaling


July, 2008

Transition Details: High Speed Signaling to Low Power Signaling


July, 2008

High Speed Signal Details


July, 2008

Spikes During Low Power Mode

MIN: 2*50ns

MIN: 20nsMAX: 300

V*ps

MIN: 880mV

MAX: 550mV

300V*ps: 0.9V 333ps1V 300ps1.5V 200ps2V 150ps

• Do complete low speed pattern including spikes with high-speed generator• Max spike level: 1.8V (single ended)• Spike and low speed data at same amplitude


July, 2008

Signal With Spikes


July, 2008

1.8V „1“-Spike


July, 2008

1.8V „0“-Spike

Enabling MIPI Physical Layer Test - Keysight · LTE WiMAX Wireless Domain Digital ... • SQL data...

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