EMI Reduction on an Automotive Microcontroller

Design Automation Conference, July 26th-31st, 2009

Patrice JOUBERT DORIOL1, Yamarita VILLAVICENCIO2, Cristiano FORZAN1, Mario ROTIGNI1,

Giovanni GRAZIOSI1, and Davide PANDINI1

1STMicroelectronics, Agrate Brianza, Italy2Politecnico di Torino, Torino, Italy

2

Outline

• Design for EMC: motivation

• EMC-aware design on an automotive microcontroller

• EMI simulation framework: characterization and modeling

• Conducted and radiated emissions: simulations vs. measurements

• Conclusions

3

EMC for Automotive

Control units

Interfere with local bus 100MHz

Interfere with local bus 100MHz

Interfere with Mobile

0.9,1.8,1.9GHz

Interfere with Computer

2.5Ghz

More complex systems

4

Electronics in Automotive is Everywhere

Cluster / Body

GPS

Engine Mngt

Car RadioEntertainment

Suspensions - ABS

(safety in general)Airbag

Transmission - Gear

5

Electronics in Automotive is Increasing

Increase of complexity

Increase of quantity

Increase of EMI

Moredevices

More buscommunication

Morefunctions

Moremountinglocations

6

EMC Automotive System OverviewProject D

evelopment Phase

While in the past EMC was addressed mostly atvehicle level nowadays it has to be improved at all levels

7

IC/Component Selection for EMC

source victimcoupling path

Cost

EMC problems solved at the source cause the lowest costs and the most effective solutions!EMC problem solving at the coupling path or load is

expensive, ineffective and sometimes simply not possible!

Optimization capabilities

8

EMC Handled at the End of the Design Cycle

DESIGNDESIGN

Done

FABRICATIONFABRICATION

Version n°Version n°

EMC MeasurementsCompliance?

EMC MeasurementsCompliance?

YESNO

FloorplanSynthesis

Place&RouteVerification

FloorplanSynthesis

Place&RouteVerification

Architectural Design

Architectural Design

+ n months

+ $$$$$$$$+ n months

+ $$$$$$$$

9

Our Vision: EMC-aware Design

DESIGNDESIGN

FABRICATIONFABRICATION

EMC compliantEMC compliant

EMC DesignGuidelines

EMC DesignGuidelines

EMC ToolsEMC Tools EMC TrainingEMC TrainingArchitectural

DesignArchitectural

Design

FloorplanSynthesis and Place&Route

Verification

FloorplanSynthesis and Place&Route

Verification

EMC SimulationsCompliance?

EMC SimulationsCompliance?

YESYES

NONO

EMC Models

10

Low-EMI Design

• To reduced power rail noise on-chip decaps (i.e., fillercap cells) are used– How many? Where?

• Important to know their frequency behaviour • Important to place them close to the hot spots to maximize their

damping effect on power rail noise• Design methodology for decap insertion is necessary for efficient and

cost-effective low-EMI design• On-chip decaps are usually built with MOS transistors with long and

wide channels to get a sufficiently large capacitance– Standard practice uses these decap cell topologies VDD

GND

Tie-off cell

VDD

GND

VDD

GND

Tie-off cell

VDD

GND

MOS cell

VDD

GND

VDD

GND

MOS cell

11

Fillercap Characterization: Frequency Behavior

110GHz10GHz

2.2GHz

*0.18μm CMOS eNVM

12

Fillercap Frequency Behavior Trend

72.55MHz327.3MHz

143.8GHz

*90nm CMOS eNVM

13

Test Case: STXX

• STXX: typical microcontroller for automotive applications– Technology in 0.18μm eNVM CMOS technology where

the NVM devices are shrunk to 0.13μm– Analog-to-Digital Converter, 128K EEPROM, ROM,

SRAMs, Voltage Regulator, etc.– Different power supply domains

14

Power Supply Waveforms Gate-level Simulations

• Digital power supply I/O PAD waveforms estimated by Apache’s RedHawk (including package model)

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Power Supply Waveforms Gate-level Simulations

• Digital power supply I/O PAD waveforms estimated by Apache’s RedHawk (including package model)

I/O PAD2nd Harmonic

Reduction (dBμV)

2nd Harmonic Reduction (%)

i_vcap -9.9 -10.7

2nd harmonic (@48MHz) Amplitude reduction (dbμV)2nd harmonic (@48MHz) Amplitude reduction (dbμV)

16

System Power Distribution Network Model

• To develop an EMI simulation framework it is necessary to model the complete system power distribution network(PDN)

• A real system PDN consists of chip, package, and board• The combined effects of chip, package, and board must be

considered to accurately analyze both power/ground integrity and EMC

Printed Circuit Board

Package

ChipCapacitor Capacitor

Capacitor

VoltageRegulator

17

System Power Distribution Network Model

• In an EMI simulation framework the system PDN (board+package+chip) must be represented by a SPICE-level compact lumped RLC circuit

• But we also need to consider non-uniform switching, circuit size/frequency and decoupling parasitics

• Hence we need more accurate models to capture all these effects

I(t)

Volt. Reg.+Board+Package Chip

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EMI Simulation Framework

• To develop an efficient and accurate methodology for noise and EMI estimation at IC and PCB level for fast assessment of chip EMC behavior before tape-out

• To enable IC and package designers to achieve chip and IC-package design (co-)optimization for EMI reduction

• To enable board designers to optimize PCBs for EMI reduction andsystem-level power integrity

• An EMI simulation framework is a critical enabler of an EMC-aware design methodology and is based on availability of accurate and compact EMI models for chip, package, and board

• EMI modeling requirements:– Early availability during IC and PCB design– Layout- or netlist-based– High accuracy at low complexity– Capability to include IP macroblocks– Easy integration into chip and board SI/PI simulators– Based on IEC standards– Widely accepted format (i.e., SPICE-like)

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EMI Simulation Framework: Components

Macroblock Characterization

IO Ring Characterization

Characterization

Modeling

Voltage Regulator Model

Package Model

Board Model

Chip Model

Probe/TEM Cell Model

Standard Cell Characterization

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EMI Simulation Framework: Characterization

Standard cell characterization

Macroblock characterization

IO ring characterization

Power rail noise analysis needs a specific characterization to generate the current profile for each macroblock(SRAMs, ROMs, eFLASHs, eEEPROMs, ADCs, etc.)

Noise characterization for the IO subsystem

Apache RedHawk Apache Totem-MMX Apache Sentinel-SSO

Power rail noise analysis needs a specific characterization to generate the current profile for each standard cell

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EMI Simulation Framework: Modeling

Chip modeling Package modeling Board modelingSpice-level RLC netlistrepresenting the package wire bonding, pins, lead frames

SPICE-level RLC netlistrepresenting the board traces and ground planes

Apache CPM with RedHawk

Chip model obtained after power rail noise analysis for all power supply domains (multi-power supply domain supported)

Ansoft Q3D and HFSS

Apache PakSi-E

Sigrity PowerSI and Broadband SPICE

Can extract the SPICE-level netlist for each trace from the PKG to the connector

Can model the whole board

Apache Sentinel-PIIC-PKG-PCB co-analysis

platform for system-level power integrity

Compact model representing the entire chip (core, macros, IOs, decaps) in terms of passive elements and current sources

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Apache’s Compact Power Model (CPM)

• Apache’s CPM (obtained with RedHawk) models the chip PDN by means of an equivalent admittance connected to a current generator

I(t)

Chip

Y

p1

p2

p1

0

p2

Chip PDN equivalent admittance representation

Icursig1 p1 p2 pwl(+ 0.00ps 0.00066+ 100.00ps 0.00263+ 200.00ps 0.00399+ 300.00ps 0.00534...+)

Piecewise linearswitching currentrepresentation

CPM extracted from STXX

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CPM: Validation

• Apache’s RedHawk vs. CPM w/o and w/- on-chip decaps• Good accuracy of CPM (ELDO transistor-level simulations) against

RedHawk (gate-level analysis) resultsW/o decaps W/- decaps

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Chip, Package, and Board System

VoltageRegulator

Model

BoardModel

PackageModel

ChipModel

Compact SPICE Model

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Voltage Regulator Modeling

• The output impedance of the voltage regulator (VR) was obtained with the linear model proposed by Crovetti and Fiori* considering the average current required by the STXX design (10mA**) over the current full range (0-50mA**)

* P. Crovetti and F. Fiori, “A Linear Voltage Regulator Model for EMC Analisys,” IEEE Transactions on Power Electronics, vol. 22, pp. 2282-2292, Nov. 2007

** STXX Design Objective Specification, System to Silicon, S2SDL01110 Rev. 3.0, Mar. 2007

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Board Modeling

• A PCB compact SPICE model was obtained using the Sigrity’s SPEEDXP toolsuite– PowerSI - frequency-domain electrical analysis of IC packages and

PCBs– Broadband SPICE - conversion of N-port network parameters to

SPICE circuits

STXX PCB used for EMC measurements

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Probe/TEM Cell Modeling

LTEM1 10nHLTEM2 10nHRM 50ΩRIN 50ΩK1 0.03K2 0.03CTEM 8pFCM 100fF

Radiated emission measurements

Conducted emission measurements

Spectrum analyzer50Ω adapted system

6.8nF

50Ω

51Ω

120Ω

Impedance matching network

TEM Cell50Ω adapted system CTEM

CM

LTEM1 LTEM2

K2K1

RM RIN

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Conducted Emissions at PCB J3 Test Pin

J3

BOARD

STXX TQFP80

5V

IO5 VDD

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J3 Test Pin SMA Waveform Simulation

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J3 Test Pin SMA Waveform Simulation

PCB Test Pin2nd Harmonic

Reduction (dBμV)

2nd Harmonic Reduction (%)

J3 -9.0 -9.7

2nd harmonic (@48MHz) Amplitude reduction (dbμV)2nd harmonic (@48MHz) Amplitude reduction (dbμV)

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J3 Test Pin Spectrum: Simulation vs. MeasurementJ3

Vol

tage

[dBμV

]

Frequency [Hz]

J3 V

olta

ge [d

BμV

]

Frequency [Hz]

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System Model for Radiated Emission Simulations

CPM model

TEM cell model

PKG model

PCB model

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Radiated Emission Measured Vo

ltage

[dBμV

]

Frequency [Hz]

Volta

ge [d

BμV

]

Frequency [Hz]

34

Radiated Emission Measured vs. SimulatedVo

ltage

[dBμV

]

Frequency [Hz]

Volta

ge [d

BμV

]

Frequency [Hz]

Volta

ge [d

BμV

]

Frequency [Hz]

Max Radiated Emission:measured vs. simulated

difference: 0.4 dBμV

Max Radiated Emission:measured vs. simulated

difference: 0.4 dBμV

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Conclusions• We proposed an EMC-aware design methodology

– A significant on-chip EMI reduction was achieved!

• This methodology was successfully exploited for the tape-out of a microcontroller for automotive applications

• An EMI simulation framework accounting for both the conducted and radiated emissions of the IC-PKG-PCB system was developed

• The simulated emissions of the entire system were compared with the available measurements

• The comparison of simulations vs. measurements demonstrated the effectiveness and the accuracy of the EMI simulation framework

• The proposed simulation framework is a competitive solution for accurate EMI evaluation and minimization before tape-out and allows to predict the true post-silicon EMC behavior vs. increasingly aggressive EMC targets dictated by marketing, customers, and international standards