Elonics E4000 - Low Power CMOS Multi-Band Tunner - Hardware Design Guide

7/31/2019 Elonics E4000 - Low Power CMOS Multi-Band Tunner - Hardware Design Guide

1/39Elonics E4000 Hardware Design Guide Rev 1v4 Copyright 2010 Elonics Ltd

Hardware Design Guide

CONFIDENTIAL

Elonics LtdAlba CentreLivingstonEH54 7EG

Tel: +44 1506 402 360Fax: +44 1506 402 361Web:www.elonics.com

Filename Hardware Design Guide 1v3

Document NumberVersion 1v4

Modified Date June 2010
http://www.elonics.com/http://www.elonics.com/http://www.elonics.com/http://www.elonics.com/



TOP TIPS TO GET BEST PERFORMANCE

1. Use low noise LDO for tuner

2. Keep RF input track short

3. Use recommended externalcomponents for the tuner

4. Do not route tuner clock sourceclose to noisy signals and do notroute reference clock tracks close tosensitive areas of the PCB, e,g, RFinput, LNAGND and LNAVDD

5. Connect pins LNAGND, LNAGND2and RFSHIELD to separate low noiseground plane



E4000 KEY DESIGN CONSIDERASTIONS

This hardware design guide is intended to assist in the layout of products using the ElonicsE4000 RF tuner IC and to maximise system performance. Key layout considerations arelisted below. More details relating to these may be found throughout the remainder of thehardware guide.

1. POWER SUPPLIES

a. The E4000 1V5 supply must be low noise, >60dB PSRR. The supply should be

generated using a low noise LDO regulator, not

a DC/DC convertor.

2. RF INPUT TRACK AND PLACEMENT

a. The RF track from the antenna connector to the tuner input should be kept

as short as possible. This track should be designed as a 50 or 75R

impedance line (to match the antenna). This track must run above a solid

ground plane

.

b. The RF signal ground return path should be as low inductance as

possible. E4000 pins 4, 6, 7 should connect to a solid ground plane that

runs below the RF track. If there are multiple planes on different layers, these

should be tied together using ground stitching vias particularly around the RF

tracks and RF connector.

c. In some applications such as a mobile phone there may be strong blocking

signals present. The user may wish to add a filter before the tuner to eliminate

the effect of these.

3. EXTERNAL COMPONENTS

a. The E4000 should have 100nH inductors connected to AVDD, DVDD, DGND,

PLL_VDD, and PLL_GND pins and placed as close as possible to the pin.

These isolate tuner VDD domains from the sensitive analogue domains

preventing noise degrading sensitivity performance.

b. TUN_DVDD and AVDD pins should have a 100pF decoupling capacitor placed

to ground close to the E4000 pins. 100pF is effective in decoupling signals in

the VHF and UHF frequency ranges. It is recommended that the Tuner

Analogue Ground and LNA domains have an additional 100nF capacitor which

will also filter lower frequency noise. Decoupling capacitors should be placed on

the tuner side of any inductors.



4. TUNER AND DEMODULATOR CLOCKS

a. Do not route E4000 1V5 supply directly above the clock track and vias.

This minimises coupling between the supply and reference clock in order to

prevent pickup on the supply line of clock tones. In some applications, it maybe possible for the E4000 tuner to share a clock with the demodulator. In this

case, additional care must be taken with the routing of the clock track. Any

noise that is coupled to the clock will pass to the tuners local oscillator and will

degrade performance. The clock track is one of the most sensitive nets on the

PCB. Any noise that gets onto this line will be amplified in the tuner and will

make the local oscillator signal inside the tuner noisy (thus degrading

sensitivity). Track should be routed so that it is shielded from any noisy signals.

b. The E4000 may be used in a system that will power down the tuner when it is

not used (e.g. a mobile phone). It is recommended that the tuner is shut down

by the dedicated hardware input, NOT by disabling the 1V5 regulator to thetuner. This eliminates the possibility of phantom powering effects which may

damage the tuner.

USB DONGLE DESIGN (FURTHER CONSIDERATIONS)

1. In a USB dongle, care must be taken with the design of the USB tracks. These are

digital lines running at 480Mb/s so any imperfections in layout may result in noise from

these lines coupling to the tuner and degrading sensitivity performance. The USB lines

should be routed as a 90 Ohm differential impedance pair.

These should be routed

above a solid ground plane providing the return current path. Grounds should containstitching vias around the USB tracks and connector.

2. USB tracks should have constant width and separation. Tracks should be routed

as differential lines with the same track width and track separation so that 90 Ohm

differential impedance is maintained. Track width = 250um. Separation from edge of one

track to other = 150um

3. Some noisy PCs may inject noise through the USB lines. It is recommended that a

common mode filter is placed in the USB tracks to prevent this noise coupling onto the

dongle. This filter should be placed at the USB connector end of the lines.

4. Some PCs may isolate the USB connector chassis and electrical ground. The USBelectrical ground pin must be connected to the dongle ground plane. It is recommended

that chassis ground is not connected on the dongle as noise may be coupled to the USB

dongle.



SET TOP BOX DESIGN (FURTHER CONSIDERATIONS

1. Use a series termination resistor of 33 Ohms for all MPEG data lines. The MPEG data

lines are high speed digital lines. The series termination resistors combined with thecapacitance of the connected IC input will provide an RC filter that will slow edges

removing very high frequency harmonics and prevent these from coupling to the tuner

and acting as noise.

2. In a set top box where there is an HDMI connection, the HDMI clock rate is typically

148MHz. Care must be taken to ensure that HDMI noise (148MHz or harmonics of this)

do not couple to the tuner via supply or ground domains. It is recommended that the

HDMI chip is physically separated from the tuner.

3. If a mobile phone or other RF device is used near the antenna of the E4000 (such as

with an indoor aerial, it may pickup spurious GSM or other RF interferers affecting

device performance. In such circumstances, it may be appropriate to use a filter thatwill pass all the UHF frequencies whilst attenuating GSM phone signals. Please contact

Elonics for design suggestions.



E4000 PIN INFORMATION

Top view

AGND

VBG

REXT

RFSHIELD

RFIN

LNAGND

LNAGND2

LNAVDD

QVOUTP

CKOUTN

GAIN0

STBYB

IVOUTP

GAIN1

IVOUTN

CKOUTP

IFGND

A0

IFVDD

QVOUTN

PLL_

VDD

XTAL

PLL_

GND

SCLK

SDAT

PDNB

A1

AVDD

CLOCKIN

TUN_

DGN

D1

TUN_

DGN

D0

TUN_

DVDD

ElonicsE4000

QFN325x5mm



PIN DESCRIPTION

Pin Name Type Description

1 AGND Ground 0V. Connect to Tuner analogue ground

2 VBGAnalogueOutput

Band gap voltage. A 10nF decoupling capacitor should beplaced between this pin and 0V. The capacitor should beplaced close to this pin.

3 REXTAnalogueOutput

Reference current generation. A 10k, 1%, resistor shouldbe placed between this pin and 0V.

4 RFSHIELD Ground RF Shield, connect to LNAGND

5 RFIN Analogue Input RF input. 50R impedance.

6 LNAGND Ground 0V

7 LNAGND2 Ground 0V, connect to LNAGND

8 LNAVDD Supply 1.5V

9 IFVDD Supply 1.5V

10 IFGND Ground 0V11 A0 Digital Input Tuner I

2C device address control (bit 0). (3.3V tolerant).

12 A1 Digital Input Tuner I2C device address control (bit 1). (3.3V tolerant).

13 STBYB Digital InputNormal operation = 1.5V (3.3V tolerant). Standby = 0V. Ifunused, connect AVDD

14 PDNB Digital InputNormal operation = 1.5V (3.3V tolerant). Power down = 0V.If unused, connect AVDD

15 SDAT Digital I / OI C data. Pull up to 1.5V (3.3V tolerant). Pull up resistor >4.5k

16 SCLK Digital Input I2C clock input. (3V3 tolerant).

17 QVOUTNAnalogueOutput

Q Channel Output -ve

18 QVOUTPAnalogue

OutputQ Channel Output +ve

19 IVOUTNAnalogueOutput

I Channel Output -ve

20 IVOUTPAnalogueOutput

I Channel Output +ve

21 GAIN0 Digital/PWMGain control input. Either digital IF or IF PWM input (3V3tolerant).

22 GAIN1 Digital/PWMGain control input. Either digital IF or RF PWM input (3V3tolerant).

23 CKOUTNLVDS or CMOSoutput

Clock Output ve. If unused, should be left as no connect.

24 CKOUTPLVDS or CMOSoutput

Clock Output +ve. If unused, should be left as no connect.

25 TUN_DVDD Supply 1.5V

26 TUN_DGND0

Ground 0V

27TUN_DGND1

Ground 0V

28 CLOCKIN OscillatorConnect to crystal OR Clock input from external source(1.5V logic levels).

29 XTAL OscillatorConnect to crystal. If unused, should be left as noconnect.

30 PLL_GND Ground 0V. Do not connect directly to LNAGND

31 PLL_VDD Supply 1.5V

32 AVDD Supply 1.5V



REFERENCE SCHEMATIC

E4000

CLOCKIN

RFIN_1

RF

INPUT

C4

100pF

GAIN0

GAIN1

AGC

CONTROL

INPUTS

A0

A1

I2C

ADDRESS

SELECT

STBYB

5

RFIN_1

21

22

GAN0

GAN1

11

12

13STBYB

A0

A1

TUNER AVDD (+1.5V)

28

29XTAL

CLOCKIN

26

27

25

TUN_DGND0

TUN_DGND1

TUN_DVDD

2

3

VBG

REXT

IVOUTP

IVOUTN

IF

OUTPUTS

C9

C8100nF

100nF

20

19

IVOUTP

IVOUTN

QVOUTP

QVOUTN

C7

C6100nF

100nF

18

17

QVOUTP

QVOUTN

AGND0

LNAGND2

LNAGND

IFGND

PLL_GND

1

7

6

30

10

FIT OPTION

LNAVDD8

IFVDD

PLL_VDD9

31

L2

100nH

TUNER DVDD (+1.5V)

L6

100nH

L3

100nH

C10

100pF

C1

10nF

R1

10k

C3

100pF

AVDD32

IMPORTANT NOTES1. E4000 metal paddle (bottom of package) should be connected to TUNER GROUND

2. Pins 4, 6, 7 should be connected to a common LNAGND plane, separate from the tuner ground plane

3. C6,7,8,9 Optional dependent on ability to match output common mode voltage to input common modevoltage of baseband demodulator input

C12

100pF

C2

100nF

SDAT

SCLK

MICROCONTROL

I/F

15

16

SDAT

SCLK

PDNB14

PDNBHARDWARE

CONTROL

I/F

CKOUTP24

CKOUTP

CKOUTN23

CKOUTN

RFSH ELD 4

C5

100pF

C11

100pF

L5100nH

L1

100nH

CONNECT

TO LNAGND

Tuner

Ground

TunerGround

Tuner

Ground

L4100nH


9/39

nics E4000 Hardware Design Guide Rev 1v4 Copyright 2010 Elonics Ltd

w.elonics.com 9

REFERENCE CIRCUIT
http://www.elonics.com/http://www.elonics.com/


10/39


w.elonics.com 10

REFERENCE CIRCUIT SELECTION OF KEY COMPONENTS

Function Type Value Quantity Size Spec Notes Schematic Reference

RF Tuner Elonics E4000 1 QFN32 Elonics E4000 Tuner (Please refer tuner spec U1

ESD Protection Diode ESD0P8RFL or

BAV99

1 Back to back diode. Low noise, < 2 pF < 2nH ESD Optional ESD protectionfor RF input

D1

Crystal Baseband Clock

(Optional)

28.8MHz 1 HC-49SM DIP (Load

Capacitance


11/39

RF LAYOUT CONSIDERATIONS

RF INPUT SIGNAL

The layout of the RF input track structure is particularly important in ensuring that the tunerdesign will work as desired (RF connector to E4000 RFIN pin 5). At RF frequencies, thedimensions of PCB traces may be such that they approach or are greater than the electricalwavelength of the transmitted signal. Thus track lengths may be long enough that reflections dueto mismatch may support varying magnitude and phase of voltages and currents along the lengthof the track. It is therefore desirable that the PCB designer aims to keep the RF input track asshort as is possible.

Also, in order that voltage reflections are small and that such a standing wave is not generated,the source impedance should match the transmission line impedance which should match theload impedance. In the case of a TV receiver this means that the antenna, transmission line andTV tuner IC should all be designed to have equal impedances, typically 50 or 75Ohms.

In practical terms, the E4000 has been implemented so that impedance is around 65Ohms. Thismeans that the magnitude of Reflection, (S11 or Return loss), is low in a 50Ohm or 75Ohmsystem. Either a 50Ohm or a 75Ohm impedance antenna can be used and the transmission lineimpedance should be designed to match the chosen value.

Note: A device with return loss, (S11), of lower than -10dB is generally considered to be wellmatched to the source impedance.

E4000 Return loss

-50

-40

-30

-20

-10

0

100 300 500 700 900

Frequency (MHz)

S11(dB) 50R source

impedance75R source

impedance


12/39

RF INPUT CONNECTOR

The guideline is that the distance between the input connector and the RF input pin (pin5) should

be kept as small as possible. This is to ensure track losses are kept to a minimum and reduce thepossibility of signal reflections occurring.


13/39

RF INPUT AC COUPLING CAPACITOR

The E4000 input should be AC coupled, if connected to anything other than a passive antenna.For a DVB-T application covering 174 858MHz, the recommended capacitor is a 100pF 0402size capacitor. The capacitor value is chosen such that it is large enough to permit low frequencysignals to be passed. The self resonance of this capacitor should be greater than the highestoperating frequency otherwise a resonance may be introduced somewhere in the wantedfrequency band. Care should be taken to ensure the ESR (effective series resistance) of thecapacitor remains low for the entire band of operation. The chart below shows a typical responsefor a 100pF 0402capacitor.

Self resonanfrequency


14/39

RF INPUT TRACK

RF input tracks need to be referenced to LNAGND. LNAGND should be a plane below and adjacent toRF track. An example is shown below of a typical configuration.

Tuner GND LNAGND (next to & below RF input track) Ground stitching vias

The inductance of the LNAGND plane should be very low as RF ground return currents will flow in thisdomain. If possible, there should be ground stitching vias running alongside the RF track to tie planeson different layers together.

The ground of the input connector should be connected to LNAGND.


15/39

DESIGN OF AN IMPEDANCE CONTROLLED TRANSMISSION LINE

The most common design of an impedance controlled line uses a microstrip structure. Theimpedance of the transmission line is determined by the inductance of the transmission line andby the capacitance between the transmission line and the ground plane below. These in turn willbe determined by the width of the transmission line, the thickness of the dielectric layer betweenthe transmission line and the ground plane and the dielectric constant of the PCB material.Transmission line impedance can be calculated using free tools such as Agilent Appcad.However, as a general rule, for a 50Ohm transmission line, track width needs to be around 2 xdielectric thickness when using FR4 PCB material.

It is critical that the RF input track has a ground reference. If a microstrip structure is used, thisshould be a solid plane below the RF input track.

Gnd plane

PCB Dielectric

Transmission line

Note: At the time of writing, Appcad could be downloaded fromhttp://www.hp.woodshot.com/

H

W
http://www.hp.woodshot.com/http://www.hp.woodshot.com/http://www.hp.woodshot.com/http://www.hp.woodshot.com/


16/39

TRANSMISSION LINE STUBS

Any components in the transmission line should be placed so that these do not create stubs. Astub may introduce a point where a reflection can occur, potentially resulting in frequency lossdue to interference between the original signal and any reflected, (time delayed), signal.

GOOD LAYOUT

Signal fromantenna

Signal to RFTuner

AC couplingcapacitor

ESD diode

Good layout. ESD diode pad is part of the transmission line, minimising any stubs andreflections. All signal reaches RF tuner at the same time.

POOR LAYOUT

Signal fromantenna

Signal to RFTuner


Poor layout. ESD diode pad is located away from the transmission line. A stub is introduced allowing someof the RF signal to flow down this branch of the transmission line. The signal may be reflected from the

diode back to the tuner. Since this may reach the tuner at a different time from the signal transmitted straightthrough the AC coupling cap. Constructive or destructive interference of the time delayed signals may be

cause ripple in the frequency response

Signal path1

Signal path2


17/39

GROUND RETURN PATH

The RF signal will flow from the antenna to the TV tuner along the microstrip transmission line.The return current will flow from the TV tuner back to the antenna through the ground

connections. Care must be taken to ensure that the ground connections between the TV tunerLNA and the PCB ground connection minimise inductance as otherwise high frequency signalsmay be attenuated. The PCB designer should ensure that there is a solid ground plane from theTV tuner to the RF connector. The E4000 LNAGND pins should connect to this plane as close tothe IC as is possible. The RF connector grounds should have vias to the ground plane as close tothe connector as is possible.

GROUND STITCHING VIAS

Ideally, the E4000 LNAGND pins should also connect directly to the RF connector on the top sideof the board also reducing ground return inductance. If this is done then the PCB designershould add ground stitching vias connecting the top ground plane to the ground plane below.These vias will tie the two ground planes to the same voltage level at the point where the viaconnects. Stitching vias should be placed close together so as to prevent high frequency voltagewaves from being supported between via connections.

Solid GND plane beneathRF track

GND Vias should beplaced close to E4000 IC

GND vias should beplaced close to the RFconnector gnd pins


18/39

SUPPLY AND GROUND CONSIDERATIONS

1.5V SUPPLY GENERATION

It is important to note that a DVB-T TV tuner is expected to have a sensitivity of around -97.5dBm(QPSK ). In a 50 Ohm impedance system, this equates to a voltage level of only 3uV (RMSpeak) for the signal. It is essential that the tuner supply and ground noise must be very low toenable a signal of this small amplitude to be detected.

In a typical application, the main system voltage will be 3.3V or higher. It is recommended thatthe tuner 1V5 supply is generated using a low noise LDO. The use of an LDO for the tuner willalso isolate the tuner from noisy digital ICs providing some immunity to the noise generated bythese.

A DC-DC regulator is not recommended to supply the E4000 directly unless the user is confidentthat it will not generate supply noise. A DC-DC regulator typically generates large amounts ofswitching noise that can increase the system noise and degrade sensitivity performance.

A designer may wish to use a DC-DC convertor further back in the system, for example to gofrom 5V to 3.3V. Careful attention should be paid to the design of this circuit to minimise thenoise generated. While the subsequent LDO will provide some rejection of noise, if the level ofnoise is very high, some of this may still get through the LDO to the tuner.


19/39

E4000 SUPPLY AND GROUND DOMAINS

The E4000 has separate supply and ground domains on-chip. This isolates the very sensitivecircuits from noisier digital circuits. Care should be taken when routing these domains on the

PCB such that isolation between domains is maintained. The different domains are highlighted inthe table below.

IMPORTANT NOTES

THE VERY SENSITIVE CIRCUITRY SHOULD OPERATE FROM THE LNAVDD ANDLNAGND DOMAIN.

NOISIER CIRCUITS OPERATE FROM THE TUN_DVDD, TUN_DGND0/1, PLL_VDD ANDPLL_GND DOMAINS.


1 AGND TUNER_GND 0V

4 RFSHIELD LNAGND 0V

6 LNAGND LNAGND 0V

7 LNAGND2 LNAGND 0V

8 LNAVDD LNAVDD 1.5V

9 IFVDD 1V5 1.5V

10 IFGND TUNERGND 0V

25 TUN_DVDD DVDD 1.5V

26 TUN_DGND0 DGND 0V

27 TUN_DGND1 DGND 0V

30 PLL_GND RFGND 0V31 PLL_VDD RFVDD 1.5V

32 AVDD 1V5 1.5V

The recommended implementation of supply and ground filtering and decoupling such thatisolation of domains is achieved are described below.


20/39

LNAVDD DOMAIN


4 RFSHIELD LNAGND 0V

6 LNAGND LNAGND 0V7 LNAGND2 LNAGND 0V

8 LNAVDD LNAVDD 1.5V

100pF

1.5V

Tuner GND

6 LNAGND

8 LNAVDD

7 LNAGND2

100nH

100nF 4 RFSHIELD

The E4000 Low noise amplifier is powered from the LNA VDD and GND domain. It is critical thatnoise is not present on this domain. Any nose pickup will be amplified through the tunerdegrading sensitivity performance. The inductor that is present in the LNAGND domain isintended to filter noise, presenting this from coupling onto this domain.

There should NOT be an inductor placed in the LNAVDD line. The LNAs high frequency currentsare sourced from this line. An inductor would limit the frequency response causing loss at highfrequency.

The LNAVDD and LNAGND domains are decoupled using a 100pF and 100nF pair. The twocapacitors will decouple a wide range of frequencies of noise.

Note: The RF input connector ground MUST

connect to the LNAGND domain. Signal currents willflow from the RF connector to the E4000 IC. Ground return currents will flow from the E4000back to the RF connector.


21/39

DVDD DOMAIN


25 TUN_DVDD DVDD 1.5V

26 TUN_DGND0 DGND 0V27 TUN_DGND1 DGND 0V

100pF

1V5

TunerGND

TUN_DGND0

TUN_DGND1

TUN_DVDD

100nH

100nH

The E4000 digital circuit operates from the DVDD and DGND domain. The fast edge speeds ofdigital clocks may generate harmonics of the reference clock frequency. This may act as noiseand should be isolated from the LNA domain. The inductors in DVDD and DGND domains areintended to filter noise going out of the chip and propagating to other domains.

PLL_VDD and PLL_GND DOMAIN


30 PLL_GND PLL GND 0V

31 PLL_VDD PLL VDD 1.5V

100pF

100nH

TunerGND

31 PLL_VDD

30 PLL_GND

100nH

1.5V

The E4000 frequency synthesizer is powered from the PLLVDD and PLLGND domain. Again,inductors should be added in supply and ground lines to prevent any noise that is generated bythese circuits from coupling to the LNA domain.


22/39

IFVDD


9 IFVDD 1V5 1.5V

10 IFGND TUNERGND 0V

100pF

Tuner GND

9 IFVDD

10 IFGND

1V5

AVDD


1 AGND TUNER_GND 0V

32 AVDD 1V5 1.5V

100pF

100nH

1 AGND

32 AVDD

GND Pad

Tuner

GND

The ground paddle of the E4000 tuner (metal pad under package) should be connected toAGND.

Note 1: Decoupling caps should be placed on the top side of the PCB as close as ispossible to the E4000 IC

Note 2: For applications where there is a demodulator present, it is recommended that thisground is isolated from the tuner ground using an inductor. This prevents digital noisefrom the demodulator reaching the tuner and degrading performance.

Note 3: For some applications such as a canned tuner, the RF connector ground is part ofthe connector ground. In this case it may not be possible to separate tuner and LNAgrounds as the shield will connect these together. If this is the case ,it is recommendedthat the inductor between LNAGND and Tuner GND domains is removed and these planesalso connected together on the PCB.


23/39

RF LAYOUT CONSIDERATIONS

RF INPUT SIGNAL

The layout of the RF input track structure is particularly important in ensuring that the tunerdesign will work as desired (RF connector to E4000 RFIN pin 5). At RF frequencies, thedimensions of PCB traces may be such that they approach or are greater than the electricalwavelength of the transmitted signal. Thus track lengths may be long enough that reflections dueto mismatch may support varying magnitude and phase of voltages and currents along the lengthof the track. It is therefore desirable that the PCB designer aims to keep the RF input track asshort as is possible.

Also, in order that voltage reflections are small and that such a standing wave is not generated,the source impedance should match the transmission line impedance which should match theload impedance. In the case of a TV receiver this means that the antenna, transmission line andTV tuner IC should all be designed to have equal impedances.

In practical terms, the E4000 has been implemented so that impedance is around 65Ohms. Thismeans that the magnitude of Reflection, (S11 or Return loss), is low in a 50Ohm or 75Ohmsystem. Either a 50Ohm or a 75Ohm impedance antenna can be used and the transmission lineimpedance should be designed to match the chosen value.

Note: A device with return loss, (S11), of lower than -10dB is generally considered to be wellmatched to the source impedance.

E4000 Return loss

-50

-40

-30

-20

-10

0

100 300 500 700 900

Frequency (MHz)

S11(dB) 50R source

impedance75R source

impedance


24/39

RF INPUT CONNECTOR

The guideline is that the distance between the input connector and the RF input pin (pin5) should

be kept as small as possible. This is to ensure track losses are kept to a minimum and reduce thepossibility of signal reflections occurring.


25/39

RF INPUT AC COUPLING CAPACITOR

The E4000 input should be AC coupled, if connected to anything other than a passive antenna.For a DVB-T application covering 174 858MHz, the recommended capacitor is a 100pF 0402size capacitor. The capacitor value is chosen such that it is large enough to permit low frequencysignals to be passed. The self resonance of this capacitor should be greater than the highestoperating frequency otherwise a resonance may be introduced somewhere in the wantedfrequency band. Care should be taken to ensure the ESR (effective series resistance) of thecapacitor remains low for the entire band of operation. The chart below shows a typical responsefor a 100pF 0402capacitor.

Self resonanfrequency


26/39

RF INPUT TRACK

RF input tracks need to be referenced to LNAGND. LNAGND should be a plane below and adjacent toRF track. An example is shown below of a typical configuration.

Tuner GND LNAGND (next to & below RF input track) Ground stitching vias

The inductance of the LNAGND plane should be very low as RF ground return currents will flow in thisdomain. If possible, there should be ground stitching vias running alongside the RF track to tie planeson different layers together.

The ground of the input connector should be connected to LNAGND.


27/39

DESIGN OF AN IMPEDANCE CONTROLLED TRANSMISSION LINE

The most common design of an impedance controlled line uses a microstrip structure. Theimpedance of the transmission line is determined by the inductance of the transmission line andby the capacitance between the transmission line and the ground plane below. These in turn willbe determined by the width of the transmission line, the thickness of the dielectric layer betweenthe transmission line and the ground plane and the dielectric constant of the PCB material.Transmission line impedance can be calculated using free tools such as Agilent Appcad.However, as a general rule, for a 50Ohm transmission line, track width needs to be around 2 xdielectric thickness when using FR4 PCB material.

It is critical that the RF input track has a ground reference. If a microstrip structure is used, thisshould be a solid plane below the RF input track.

Gnd plane

PCB Dielectric

Transmission line

Note: At the time of writing, Appcad could be downloaded fromhttp://www.hp.woodshot.com/

H

W
http://www.hp.woodshot.com/http://www.hp.woodshot.com/http://www.hp.woodshot.com/http://www.hp.woodshot.com/


28/39

TRANSMISSION LINE STUBS

Any components in the transmission line should be placed so that these do not create stubs. Astub may introduce a point where a reflection can occur, potentially resulting in frequency lossdue to interference between the original signal and any reflected, (time delayed), signal.

GOOD LAYOUT

Signal fromantenna

Signal to RFTuner


ESD diode

Good layout. ESD diode pad is part of the transmission line, minimising any stubs andreflections. All signal reaches RF tuner at the same time.

POOR LAYOUT

Signal fromantenna

Signal to RFTuner


Poor layout. ESD diode pad is located away from the transmission line. A stub is introduced allowing someof the RF signal to flow down this branch of the transmission line. The signal may be reflected from the

diode back to the tuner. Since this may reach the tuner at a different time from the signal transmitted straightthrough the AC coupling cap. Constructive or destructive interference of the time delayed signals may be

cause ripple in the frequency response

Signal path1

Signal path2


29/39

GROUND RETURN PATH

The RF signal will flow from the antenna to the TV tuner along the microstrip transmission line.The return current will flow from the TV tuner back to the antenna through the ground

connections. Care must be taken to ensure that the ground connections between the TV tunerLNA and the PCB ground connection minimise inductance as otherwise high frequency signalsmay be attenuated. The PCB designer should ensure that there is a solid ground plane from theTV tuner to the RF connector. The E4000 LNAGND pins should connect to this plane as close tothe IC as is possible. The RF connector grounds should have vias to the ground plane as close tothe connector as is possible.

GROUND STITCHING VIAS

Ideally, the E4000 LNAGND pins should also connect directly to the RF connector on the top sideof the board also reducing ground return inductance. If this is done then the PCB designershould add ground stitching vias connecting the top ground plane to the ground plane below.These vias will tie the two ground planes to the same voltage level at the point where the viaconnects. Stitching vias should be placed close together so as to prevent high frequency voltagewaves from being supported between via connections.

Solid GND plane beneathRF track

GND Vias should beplaced close to E4000 IC

GND vias should beplaced close to the RFconnector gnd pins


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PCB STACKUP (4 LAYER BOARD)

The diagram above illustrates the four layers of the PCB board. Each layer has been partitionedinto a specific requirement.

Layer 1, the top layer is used for placement of the E4000 tuner and if applicable, thedemodulator. This layer may also be used for routing of the high speed signal tracks. It isrecommended that this layer is not flooded with ground around the tuner so that noise does notunintentionally couple from signal lines to ground planes or vice versa. The exception to this isthat the LNAGND between the RF connector and the E4000 Gnd pins should be connected onthe top side so as to minimise ground return path inductance.

Layer 2 should be a ground plane this provides the ground reference for any impedancecontrolled tracks.

Layer 3 may be used as a power plane.

Layer 4 may be used for components and routing of low speed signals.

Note: Where a 2 layer construction is used, layer 3 and 4 may be omitted, with powerbeing routed on layer 1 or 2. Care must be taken to make sure that high frequency signalground return paths run continuously over a ground plane and do not cross over tracking.

Where there are multiple layers of ground plane, these should be stitched together using vias.This will minimise inductance between ground planes and will tie different planes to the samepotential level. Vias should be placed close together so as to prevent standing waves being setup within the ground plane area between two vias, (high frequency ground bounce).


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PACKAGE DRAWING

2x

aaa C2x

B

E

Top View

Nx

Edge View

A

aaa C

ccc C

0.08 C

A

D

A3

C

e

Bottom View

D2D1

E1

E2

pin 1

Detail A

3

4

Detail B

Detail B

0.2

7

typ

0.165 typDetail A

L

Nxk

T

R

L1

7

6

BNx b

C AMbbb

QFN: 32 PIN QFN PLASTIC PACKAGE 5 x 5 x 0.9 BODY, 0.50 mm LEAD PITCH

EXPOSED PAD

A1

0.4

0.4

Symbol Minimum Nominal Maximum

A 0.85 0.90 1.0

A1 0 0.02 0.05

A3 0.20 ref

D 4.90 5.0 5.1D1 3.5

D2 3.2 3.3 3.4

E 4.90 5.0 5.1

E1 3.5

E2 3.20 3.30 3.40

L 0.35 0.40 0.45

L1 0.1

b 0.18 0.23 0.30

N 32

e 0.50

k 0.20

R b min/2

T 0.15

Common Dimensions Notes1. JEDEC ref MO-2202. All dimensions are in millimeters3. Pin 1 orientation identified by chamfer on corner of exposed diepad4. Datum C and the seating plane are defined by the flat surface of

the metallised terminal5. Dimension e represents the terminal pitch6. Dimension b applies to metallised terminal and is measured 0.25to 0.30mm from terminal tip7. Dimension L1 represents terminal pull back from package edge.Where terminal pull back exists, only upper half of lead is vis ble onpackage edge due to half etching of leadframe8. Package surface shall be matt finish, Ra 1.6 2.29. Leadframe material is copper A19410. Coplanarity applies to the exposed pad as well as the terminals

Symbol

Tolerances for

Form & Position Notes

aaa 0.15

bbb 0.10ccc 0.10


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LOOPBACK CIRCUIT


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EXAMPLE LAYOUT (4 LAYERS) Component Placement

Short RF input track toE4000

Tuner Crystal (Clock

Source)

IF Output AC CouplingCapacitors

E4000 (metal bottompaddle) connected toAGND


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w.elonics.com 34

EXAMPLE LAYOUT (4 LAYERS) Layer 1 Signals and Key Connections

Short RF input track toE4000

RF Input AC CouplingCapacitor

IF Outputs, AC Coupled


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EXAMPLE LAYOUT (4 LAYERS) Layer 2, LNAGND and Tuner GND Layer

LNAGND plane underinput track. Groundstitching vias to otherground planes

Bottom pad of the E4000connected to Tuner GNDplane


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EXAMPLE LAYOUT (4 LAYERS) Layer 3, 1.5V Supply


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EXAMPLE LAYOUT (4 LAYERS) Layer 3, Tuner GND Layer


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Elonics E4000 Hardware Design Guide Rev 1v4 Copyright 2010 Elonics Ltd

www.elonics.com 38

LEGAL NOTICES

Product information is current as of publication date. Elonics Ltd (Elonics) products andservices are sold subject to Elonics terms and conditions of sale, delivery and payment suppliedat the time of order acknowledgement.

Elonics warrants performance of its products to the specifications in effect at the date ofshipment. Elonics reserves the right to make changes to its products and specifications or todiscontinue any product or service without notice. Customers should therefore obtain the latestversion of relevant information from Elonics to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Elonics deems necessaryto support its warranty. Specific testing of all parameters of each device is not necessarilyperformed unless required by law or regulation. In order to minimise risks associated withcustomer applications, the customer must use adequate design and operating safeguards tominimise inherent or procedural hazards. Elonics is not liable for applications assistance orcustomer product design. The customer is solely responsible for its selection and use of Elonicsproducts. Elonics is not liable for such selection or use nor for use of any circuitry other than

circuitry entirely embodied in an Elonics product. Elonics products are not intended for use inlife support systems, appliances, nuclear systems or systems where malfunction can reasonablybe expected to result in personal injury, death or severe property or environmental damage.Any use of products by the customer for such purposes is at the customers own risk.

Elonics does not grant any licence (express or implied) under any patent right, copyright, maskwork right or other intellectual property right of Elonics covering or relating to any combination,machine, or process in which its products or services might be or are used. Any provision orpublication of any third partys products or services does not constitute Elonics approval,licence, warranty or endorsement thereof. Any third party trademarks contained in thisdocument belong to the respective third party owner.

Reproduction of information from Elonics datasheets is permissible only if reproduction iswithout alteration and is accompanied by all associated copyright, proprietary and other notices(including this notice) and conditions. Elonics is not liable for any unauthorised alteration of suchinformation or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person whichdiffers from those contained in this datasheet or in Elonics standard terms and conditions ofsale, delivery and payment are made, given and/or accepted at that persons own risk. Elonicsis not liable for any such representations, warranties or liabilities or for any reliance placedthereon by any person.


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REVISION HISTORY

Revision Date Description of changes

1v0 January 2010 Initial Release1v2 March 2010 Major revision of all sections

1v3 April 2010 Minor revision to all sections1v4 June 2010 Updated pin names

Elonics E4000 - Low Power CMOS Multi-Band Tunner - Hardware Design Guide

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