ELEN 624 Signal IntegrityELEN 624, Fall 2006 W1, 09/18/2006 -1 ELEN 624 Signal Integrity Lecture 1...

ELEN 624, Fall 2006 W1, 09/18/2006 - 1

ELEN 624 Signal Integrity

Lecture 1Lecture 1

Instructor:Instructor: Jin ZhaoJin Zhao

408408--580580--7043, 7043, [email protected]@ieee.org

ELEN 624, Fall 2006 W1, 09/18/2006 - 2

Agenda

•• IntroductionIntroduction

•• Packaging and PackagesPackaging and Packages

•• Course SyllabusCourse Syllabus

•• MiscellaneousMiscellaneous

•• A Quick SurveyA Quick Survey

ELEN 624, Fall 2006 W1, 09/18/2006 - 3

Packaging and Packages

Introduction and Overview ofIntroduction and Overview of

Microelectronic PackagingMicroelectronic Packaging

An An electronic packageelectronic package is defined as that portion of an electronic structure is defined as that portion of an electronic structure that serves to protect an electronic/electrical element from itsthat serves to protect an electronic/electrical element from its environment environment

and the environment from the electronic/electrical element.and the environment from the electronic/electrical element.

In addition to providing encapsulation for environmental protectIn addition to providing encapsulation for environmental protection, a ion, a package must also allow for complete testing of the packaged devpackage must also allow for complete testing of the packaged device and ice and

a higha high--yield method of assembly to the next level of integration.yield method of assembly to the next level of integration.

ELEN 624, Fall 2006 W1, 09/18/2006 - 4

Introduction and Overview of

Microelectronic Packaging

•• Functions of an electronic packageFunctions of an electronic package

•• Packaging hierarchyPackaging hierarchy

•• Brief history of electronic packaging technologyBrief history of electronic packaging technology

•• ChallengesChallenges

•• Electrical design, one of the driven forces on packaging Electrical design, one of the driven forces on packaging technologytechnology

ELEN 624, Fall 2006 W1, 09/18/2006 - 5

Functions of an Electronic Package

•• Restrict the definition of an electronic package to the housing Restrict the definition of an electronic package to the housing and interconnection of and interconnection of

integrated circuits (ICs, silicon chips, chips, or die) to form integrated circuits (ICs, silicon chips, chips, or die) to form an electronic system.an electronic system.

•• Functions that a package must provide:Functions that a package must provide:

•• A structure to physically support the chipA structure to physically support the chip

•• A physical housing to protect the chip from the environmentA physical housing to protect the chip from the environment

•• An adequate means of removing heat generated by the chips or An adequate means of removing heat generated by the chips or systemsystem

•• Electrical connections to allow signal and power access to and fElectrical connections to allow signal and power access to and from rom the chip.the chip.

•• A wiring structure to provide interconnection between the chips A wiring structure to provide interconnection between the chips of an of an electronic system.electronic system.

ELEN 624, Fall 2006 W1, 09/18/2006 - 6

Functions of an Electronic Package

•• Four basic requirements:Four basic requirements:

•• Circuit support and protectionCircuit support and protection

•• Signal distributionSignal distribution

•• Heat dissipationHeat dissipation

•• Power distributionPower distribution

•• Additional functions:Additional functions:

•• It should function at its designed performance levelIt should function at its designed performance level

•• With high quality, reliable, serviceable and economicalWith high quality, reliable, serviceable and economical

•• Rearrangement or addition of functional features…Rearrangement or addition of functional features…

ELEN 624, Fall 2006 W1, 09/18/2006 - 7

Flip Chip BGA Package

Resin, or plastic encapsulant

Silicon Chip

(Bare Chip) High-density Multilayer

Wiring Board

• Signal and power distribution are accomplished through leads and wire bonds, etc.

• Heat dissipation is accomplished through leads and chip support

• Support and protection are accomplished through the Wiring Board/substrate, or external

package, and Resin, or plastic encapsulant.

Chip and package connection may

through bonding wire or c4 bumps

PCB and package connection may

through solder balls or lead frame.

ELEN 624, Fall 2006 W1, 09/18/2006 - 8

Package Example: FCBGA

C4 bump µ-

solder ball

Silicon Chip

(Bare Chip)

High-density

Multilayer

Wiring Board

Resin

External Terminal (Solder Ball)

• Signal and power distribution are accomplished through solder balls or c4 bumps.

• Heat dissipation is accomplished through leads and chip support

• Support and protection are accomplished through the Wiring Board/substrate, or external

package, and Resin, or plastic encapsulant.

ELEN 624, Fall 2006 W1, 09/18/2006 - 9

Functions of Packages

•• Protecting from the external Protecting from the external environmentenvironment

•• Enabling electrical Enabling electrical connectivityconnectivity

•• Heat radiationHeat radiation

•• Improving packagingImproving packaging

ELEN 624, Fall 2006 W1, 09/18/2006 - 10








ELEN 624, Fall 2006 W1, 09/18/2006 - 11

Hierarchical Electronic Packaging

capacitor capacitorchip chip

signal traces

vias

Printed Circuit Board

power ground planes

Typical electronic systems

are made up of several

levels of packaging, and

each level of packaging has

distinctive types of

interconnection devices

associated with it.

Level 0: Gate-to-gate interconnections on a monolithic silicon chip

Level 1: Packaging of silicon chips into dual-in-line packages (DIPs), small outline integrated circuit (SOICs),

chip carriers, multichip packages, and so on, and the chip-level interconnects that join the chip to the

lead frames.

Level 2: Printed wiring board (PWB), also referred to as printed circuit board (PCB), level of interconnections.

Printed conductor paths connect the device leads of components to PWBs and to the electrical edge

connnectors for off-the-board interconnection.

Level 3: Connections between PWBs, including PWB-to-PWB interconnections or card-to-motherboard

interconnections.

Level 4: Connections between two subassemblies. For example, a rack or frame may hold several shelves of

subassemblies that must be connected together to make up a complete system.

Level 5: Connections between physically separate systems such as host computer to terminals, computer to

printer, and so on.

ELEN 624, Fall 2006 W1, 09/18/2006 - 12


Level 2: Printed wiring board (PWB), also referred to as printed circuit board (PCB), level of interconnections. Printed conductor

paths connect the device leads of components to PWBs and to the electrical edge connnectors for off-the-board

interconnection.

Level 3: Connections between PWBs, including PWB-to-PWB interconnections or card-to-motherboard interconnections.

Level 4: Connections between two subassemblies. For example, a rack or frame may hold several shelves of subassemblies that

must be connected together to make up a complete system.

Level 5: Connections between physically separate systems such as host computer to terminals, computer to printer, and so on.

ELEN 624, Fall 2006 W1, 09/18/2006 - 13


Level 0: Gate-to-gate interconnections are formed during IC fabrication.

Level 3~5 are not pertinent to IC packaging, so we will not discuss them either.

Level 0: Gate-to-gate interconnections on a monolithic silicon chip

Level 1: Packaging of silicon chips into dual-in-line packages (DIPs), small outline

integrated circuit (SOICs), chip carriers, multichip packages, and so on, and

the chip-level interconnects that join the chip to the lead frames.

Level 2: Printed wiring board (PWB), also referred to as printed circuit board (PCB),

level of interconnections. Printed conductor paths connect the device leads

of components to PWBs and to the electrical edge connnectors for off-the-

board interconnection.Level 3: Connections between PWBs, including PWB-to-PWB interconnections or card-to-motherboard interconnections.

Level 4: Connections between two subassemblies. For example, a rack or frame may hold several shelves of subassemblies that

must be connected together to make up a complete system.

Level 5: Connections between physically separate systems such as host computer to terminals, computer to printer, and so on.

ELEN 624, Fall 2006 W1, 09/18/2006 - 14

First Level Interconnection

First level packaging ( or interconnection) refers to the technology required to get electrical

signals into and out of a single transistor or IC; in other words, the connections required

between the bonding pads on the IC and the pins of the package.

This is generally accomplished by wire bonding, flip-chip bonding, or Tape-Automated Bonding.

ELEN 624, Fall 2006 W1, 09/18/2006 - 15


Wire Bonding

The oldest method, but is still the dominant method used today, particularly for chips with a

moderate number of inputs/outputs(I/O)(~200).

This technique involves connecting gold or aluminum wires between the chip bonding pads,

located around the periphery of the chip, and the contact points on the package.

This process has been automated for many years, but it is still time consuming because each

wire requires two bonding operations, and must be attached individually.

Other limitations of wire bonding include the requirement for minimum spacing between

adjacent bonding sites to provide sufficient room for the bonding tool, the number of bonding

pads that can be located around the periphery of the chip, signal delay, and crosstalk between

adjacent wires.

ELEN 624, Fall 2006 W1, 09/18/2006 - 16


Flip-Chip Bonding

The chip is mounted upside down onto a carrier, module, or PWB. Electrical connection is made

via solder bumps. The solder bumps are located over the surface of the chip in a somewhat

random pattern or an array so that periphery limitation, such as that encountered in wire

bonding, does not limit the I/O capability. The I/O density is primarily limited by the minimum

distance between adjacent bonding pads on the chip and the amount of chip area that can be

dedicated to interconnection. Additionally, the interconnect distance between chip and package

is minimized since bumps can essentially be located anywhere on the chip.

Although this technique is attractive for use in multichip packaging technology because chips

can be located very close together, fatigue of solder joints due to thermal expansion mismatch of

the chip-bond-substrate, heat removal from the back of the chip, and difficulty inspecting the

solder joints after the chip has been attached to the substrate offer special challenges to the

packaging specialist.

ELEN 624, Fall 2006 W1, 09/18/2006 - 17


ELEN 624, Fall 2006 W1, 09/18/2006 - 18

Second Level Interconnection

Level 2 interconnection refers to the electrical connection of an IC to a circuit board, the most

common one being a conventional PWB. Following level 1 interconnection, single IC chips

normally undergo encapsulation in either plastic or ceramic based packages prior to connection

to a PWB.

ELEN 624, Fall 2006 W1, 09/18/2006 - 19

Variations of Packages

•• PackagePackage--toto--Board attachmentBoard attachment

•• PinPin--ThroughThrough--Hole (PTH), Surface Mount Technology (SMT)Hole (PTH), Surface Mount Technology (SMT)

•• ChipChip--toto--Package interconnectionPackage interconnection

•• WirebondWirebond, TAB, Flip Chip, TAB, Flip Chip

•• I/O locationsI/O locations

•• Peripheral, Area ArrayPeripheral, Area Array

•• Package materialsPackage materials

•• Plastic, Ceramic, Thin FilmPlastic, Ceramic, Thin Film

ELEN 624, Fall 2006 W1, 09/18/2006 - 20

Package-to-Board Attachment

•• Insertion (PTH) typeInsertion (PTH) type

•• DIP (Dual In Line Package)DIP (Dual In Line Package)

•• SIP (Single In Line Package)SIP (Single In Line Package)

•• PGA (Pin Grid Array Package)PGA (Pin Grid Array Package)

•• Surface Mounting typeSurface Mounting type

•• SOP (Small Outline Package)SOP (Small Outline Package)

•• QFP (Quad Flat Package)QFP (Quad Flat Package)

•• BGA (Ball Grid Array Package)BGA (Ball Grid Array Package)

DIP

SOP

QFP

ELEN 624, Fall 2006 W1, 09/18/2006 - 21








ELEN 624, Fall 2006 W1, 09/18/2006 - 22

Peripheral Packages

•• Dual In Line Package Dual In Line Package

•• 8 8 –– 48 pins48 pins

•• Early 1960s (Bryant Rogers)Early 1960s (Bryant Rogers)

•• Small Outline PackageSmall Outline Package

•• 24 24 –– 48 pins48 pins

•• TSOP (< 1mm in thickness)TSOP (< 1mm in thickness)

•• Quad Flat PackageQuad Flat Package

•• 48 48 –– 128 pins, up to 384 pins128 pins, up to 384 pins

•• TQFPTQFP

ELEN 624, Fall 2006 W1, 09/18/2006 - 23

Area Array Packages

I/O Pitch

0.5mm pitch

I/O = 160 I/O = 1600

ELEN 624, Fall 2006 W1, 09/18/2006 - 24

Chip to Package Interconnection

•• Flip Chip Package Flip Chip Package vsvs WirebondWirebond PackagePackage

Of all of the chip-to-package interconnection types, the

electrical performance of wire-bonds is the lowest.

ELEN 624, Fall 2006 W1, 09/18/2006 - 25








ELEN 624, Fall 2006 W1, 09/18/2006 - 26

Challenges

• There always has been and will continue to be motivation to pack more electronic

functionality and higher speed performance into a smaller volume of space.Packaging of ICs is one area that offers attractive benefits for reducing size and improving

performance by either eliminating the package or reducing the size to the point where it

takes up very little more space than the IC.

• For many years the electronics industry had been concentrating on increasing the

performance of ICs (more circuitry/silicon area operating at higher speeds) with little

consideration of the fact that ICs in an electronic system must communicate with

each other through the packages that contain them. As a result of the trend toward higher circuit densities and operating speeds on a chip, following effects became important

considerations for packaging engineers:

• I/O requirements increased sharply.

• Signal transition time between chips became a factor limiting system speed.

• Signal integrity between silicon chips degraded.

• Power requirements per chip increased.

• A problem with heat dissipation was created.

• All of these factors forced electronic packaging technology into the spotlight, resulting in a

reconsideration of how ICs were being packaged.

ELEN 624, Fall 2006 W1, 09/18/2006 - 27

IC Packaging Challenges

•• The package is the bottleneck to the system performanceThe package is the bottleneck to the system performance

Packaged Chip

Bare Chip

Time (Years)

Maximum

Operating

Frequency

ELEN 624, Fall 2006 W1, 09/18/2006 - 28

Multichip Module (MCM)

A Motorola 68040

microprocessor and

four dual-port SRAMs

in one package

Source:

Univ. of Arkansas Dept. of Electrical Engineering / HiDEC

MCM:

a single electronic package

containing more than one IC.

The ICs are interconnected

through a substrate.

ELEN 624, Fall 2006 W1, 09/18/2006 - 29

3D Stacking

Three-Dimensional Stacking:

Chips are stacked together.

One of the first commercial efforts to stack chips within

a single package mated flash memory with static

random-access memory (SRAM).

The industry desire to reduce product size, weight, and

cost while providing extra performance (shorter

interconnects that lower capacitance and inductance,

reducing crosstalk, and lower power consumption) and

increasing functionality, has driven 3D packaging of

both chips and packages.

ELEN 624, Fall 2006 W1, 09/18/2006 - 30

WLP, WSP and WLS

•• WaferWafer--level packaging (WLP)level packaging (WLP)

•• The die and package are manufactured and tested on the wafer priThe die and package are manufactured and tested on the wafer prior to separation of the or to separation of the

packaged devices by dicing in the flippackaged devices by dicing in the flip--chip fashion.chip fashion.

•• Packages are really chip size as opposed to chip scale, which isPackages are really chip size as opposed to chip scale, which is also named as waferalso named as wafer--

scale/chipscale/chip--scale scale packages(WSpackages(WS--CSP) or waferCSP) or wafer--level/chiplevel/chip--scale scale packaging(WLpackaging(WL--CSP)CSP)

•• The motivation for WLP(WSP) is that peripherally designed die caThe motivation for WLP(WSP) is that peripherally designed die can be transformed, using a n be transformed, using a

thinthin--film technology, into a standard bump or ball footprint that is film technology, into a standard bump or ball footprint that is compatible with current compatible with current

PCB layout rules, device test practices, and assembly practice. PCB layout rules, device test practices, and assembly practice. Originally, waferOriginally, wafer--level level

redistribution was intended to physically redistribute perimeterredistribution was intended to physically redistribute perimeter bonding pads to an area array bonding pads to an area array

for flip chip technology.for flip chip technology.

•• WLP offers lowest cost per I/O, since all interconnections are fWLP offers lowest cost per I/O, since all interconnections are formed at the wafer level at the ormed at the wafer level at the

same time, lowest testing cost since it can be done at the wafersame time, lowest testing cost since it can be done at the wafer level, lowest burnlevel, lowest burn--in cost in cost

because it is done at the wafer level, elimination of underfillibecause it is done at the wafer level, elimination of underfilling, and enhanced electrical ng, and enhanced electrical

performance because of the short interconnections.performance because of the short interconnections.

•• WaferWafer--level stacking (WLS)level stacking (WLS)

•• To yield stacked die that are packaged at the wafer level.To yield stacked die that are packaged at the wafer level.

•• Wafers containing ICs are interconnected using a thinly polishedWafers containing ICs are interconnected using a thinly polished wafer (a few tens of microns wafer (a few tens of microns

thick) containing throughthick) containing through--wafer wafer viasvias..

ELEN 624, Fall 2006 W1, 09/18/2006 - 31

The Future

•• There appears to be little doubt that the impact of packaging onThere appears to be little doubt that the impact of packaging on future electronic future electronic

systems will continue to increase with time.systems will continue to increase with time.

•• The trend will continue to be toward a more integrated approach The trend will continue to be toward a more integrated approach to semiconductor to semiconductor

packaging and system design.packaging and system design.

•• Consequently, the boundary between semiconductor fabrication andConsequently, the boundary between semiconductor fabrication and packaging with packaging with

blur, and packaging will, by necessity, become an integral part blur, and packaging will, by necessity, become an integral part of system design.of system design.

•• As packaging technology progresses, there are many problems thatAs packaging technology progresses, there are many problems that must be must be

addressed.addressed.

•• Moisture absorptionMoisture absorption

•• Dielectric loss, lower loss dielectrics are critically importantDielectric loss, lower loss dielectrics are critically important to higher frequency system to higher frequency system

operationoperation

•• For new materials, reliability issues must also be addressed.For new materials, reliability issues must also be addressed.

•• As minimum chip geometries continue to shrink into the nanometerAs minimum chip geometries continue to shrink into the nanometer range, higher pin range, higher pin

count, higher wiring density, and passive device integration wilcount, higher wiring density, and passive device integration will provide significant l provide significant

challenges to packaging technology.challenges to packaging technology.

•• If these challenges can be and are met, then thermal management If these challenges can be and are met, then thermal management will continue to will continue to

provide challenges for the researcher.provide challenges for the researcher.

ELEN 624, Fall 2006 W1, 09/18/2006 - 32








ELEN 624, Fall 2006 W1, 09/18/2006 - 33

Electrical design

•• The onThe on--chip switching speeds of ICs are continuously increasing.chip switching speeds of ICs are continuously increasing.

•• Noise margins are generally decreasing at the same time.Noise margins are generally decreasing at the same time.

•• Chip I/O count and interconnection speed have not kept pace so tChip I/O count and interconnection speed have not kept pace so that packaging hat packaging

interconnects now play a dominant and limiting role in determiniinterconnects now play a dominant and limiting role in determining overall system ng overall system

performance.performance.

•• Each lead from the chip to the package and each package lead to Each lead from the chip to the package and each package lead to the outside world the outside world

has some parasitic capacitance, resistance, and inductance that has some parasitic capacitance, resistance, and inductance that limits switching limits switching

speed, distorts the shape of signals passing through it, and serspeed, distorts the shape of signals passing through it, and serves as a source of ves as a source of

electrical noise.electrical noise.

•• These leads are also a source of reliability problems.These leads are also a source of reliability problems.

•• The pattern of metal and dielectric that forms the circuitry betThe pattern of metal and dielectric that forms the circuitry between chips and from ween chips and from

chips to the outside world of an MCP contribute to the degradatichips to the outside world of an MCP contribute to the degradation of electrical on of electrical

performance.performance.

•• Some electrical design factors must be considered include signalSome electrical design factors must be considered include signal lead length (short lead length (short

parallel runs to minimize mutual inductance and crosstalk, and sparallel runs to minimize mutual inductance and crosstalk, and short runs near hort runs near

ground planes to minimize capacitive loading), use of matched imground planes to minimize capacitive loading), use of matched impedances to avoid pedances to avoid

signal reflection, low ground resistance for minimum power supplsignal reflection, low ground resistance for minimum power supply voltage drop, and y voltage drop, and

power supply spiking caused by signal lines switching simultaneopower supply spiking caused by signal lines switching simultaneously.usly.

•• All of these factors are functions of geometries and materials.All of these factors are functions of geometries and materials.

ELEN 624, Fall 2006 W1, 09/18/2006 - 34

A Package

Bonding wire layer Layer 1 Layer 2

Layer 3 Layer 4

ELEN 624, Fall 2006 W1, 09/18/2006 - 35

Package Electrical Requirements

•• Signal IntegritySignal Integrity

•• Timing, distortion (overshoot undershoot)Timing, distortion (overshoot undershoot)

•• Crosstalk noiseCrosstalk noise

•• Power IntegrityPower Integrity

•• Power supply fluctuation (“Ground Bounce”)Power supply fluctuation (“Ground Bounce”)

•• Simultaneous Switching Noise (SSN) Simultaneous Switching Noise (SSN)

•• Electromagnetic Interference (EMI)Electromagnetic Interference (EMI)

•• Harmonics interfere with common Harmonics interfere with common communication bands of TV, FM, PCScommunication bands of TV, FM, PCS

ELEN 624, Fall 2006 W1, 09/18/2006 - 36

You Will Learn ……

•• Understand the signal and power integrity issues Understand the signal and power integrity issues in the package (and board) designin the package (and board) design

•• Fundamentals of lumped and distributed circuit Fundamentals of lumped and distributed circuit network analysis network analysis

•• Build models to evaluate and analyze the Build models to evaluate and analyze the package electrical performancepackage electrical performance

•• Identify appropriate EDA software to assess the Identify appropriate EDA software to assess the signal and power integrity signal and power integrity

•• The ability of analyzing the simulation results and The ability of analyzing the simulation results and making legitimate decisionmaking legitimate decision

ELEN 624, Fall 2006 W1, 09/18/2006 - 37

The System

Top Signal LayerGND Plane LayerInner Signal Layer1

Inner Signal Layer2PWR Plane LayerBottom Signal Layer

PCB

Package

Chip/Die

P/G supplySignal

C4 layer

Solder Ball layer

Decap

s

Other

Packages

and ChipsConnector

Daughter Cards

System

Power

Supply

A system

Signal transmission system, deliver the signal

Power delivery system, to make sure the device will work properly

Interaction/coupling within the system, between two systems

ELEN 624, Fall 2006 W1, 09/18/2006 - 38

Tentative Schedule

ELEN 624, Fall 2006 W1, 09/18/2006 - 39

Tentative Schedule

ELEN 624, Fall 2006 W1, 09/18/2006 - 40

Miscellaneous

ELEN 624, Fall 2006 W1, 09/18/2006 - 41

Useful References

•• Fundamental circuit analysisFundamental circuit analysis

•• James W. Nilsson, James W. Nilsson, Electric CircuitsElectric Circuits, Addison, Addison--Wesley Publishing Wesley Publishing

Company, 1986Company, 1986

•• ElectromagneticsElectromagnetics

•• David K. Cheng, David K. Cheng, Field and Wave ElectromagneticsField and Wave Electromagnetics, Addison, Addison--Wesley Wesley

Publishing Company, 1989Publishing Company, 1989

•• (Digital and Analogue) Integrated Circuits(Digital and Analogue) Integrated Circuits

•• Adel S. Adel S. SedraSedra, Kenneth C. Smith, , Kenneth C. Smith, Microelectronic CircuitsMicroelectronic Circuits, Oxford , Oxford

University Press, 1998University Press, 1998

•• Reference Books on Signal IntegrityReference Books on Signal Integrity

•• Brian Young, Brian Young, Digital Signal Integrity Digital Signal Integrity –– Modeling and Simulation with Modeling and Simulation with

Interconnects and PackagesInterconnects and Packages, Prentice, Prentice-- Hall PTR 2001Hall PTR 2001

•• Tom Tom GranbergGranberg, , Handbook of Digital Techniques for HighHandbook of Digital Techniques for High--Speed Speed

DesignDesign, Prentice Hall PTR, 2004 (very industry oriented) , Prentice Hall PTR, 2004 (very industry oriented)

ELEN 624, Fall 2006 W1, 09/18/2006 - 42

A Quick Survey

ELEN 624 Signal IntegrityELEN 624, Fall 2006 W1, 09/18/2006 -1 ELEN 624 Signal Integrity Lecture 1...

Documents

Transcript of ELEN 624 Signal IntegrityELEN 624, Fall 2006 W1, 09/18/2006 -1 ELEN 624 Signal Integrity Lecture 1...