Csaba Andras-Moritz ECE 668 3D IC Technology and Emerging 3D Processors.
Electroplating aspects in 3D IC...
Transcript of Electroplating aspects in 3D IC...
Atotech @ Sematech Workshop San Diego/Ca 2008-09-26
Electroplating aspects in 3D IC Technology
Dr. A. Uhlig Atotech Deutschland GmbHSemiconductor R&D
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Packaging stacking (PoP, PiP) Die stacking (SiP) (wire bonding & FC)
Miniaturization in size and weight
Integration of heterogeneous technologies and complex multi-chip systems
Short vertical interconnects
Reduced power consumption and parasitics
Increased performance and functionality
3D integration with TSVs(W2W, C2W, C2C)
3D Advanced Packaging
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3D Chip stacking
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Proposed Applications
IBM ECTC 2008
IME ECTC 2008
SFT ECTC 2008
Application determines TSV size; type of interconnection, handling sequence, …
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TSVConductive paste printing 50 < d < 100µm Copper plating 1 < d < 70 µmCVD W, poly Si 0,1 < d < 1µm
BumpingCu-RDL/Screen printed solder paste 150 µ < pitch < 400µmCopper pillar/E-plated bumbs 30 µm < pitch < 100 µmE-plated microbumps 10 µm < pitch < 30 µm Metal to Metal pitch < 20 µmConductive adhesiveSputtering (also C4NP) 10 µm < pitch < 100 µm
RDLAl PVDCopper electroplating plating
TSV seed layerSputtered Cu, W, …; CVD; ALDE’graftingE’less copper
3D plating applications & Outline
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• conformal/ bottom up plating• status
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Copper TSV
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TSV plating principles
„bottom up“„conformal“
Drilling/ etching
Barrier/ Seedlayer
Copper plating/CMP
Wafer thinning
Drilling/ etching
Barrier
Attach to conductiveSupport wafer
Copper Plating
CMP/detach
both TSV plating technologies will be applied?
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Galvanic plating principles
„Panel-plating“
Galvanic deposition
Barrier & plating base deposition
conformal TSV; DD
Photo-resist coating & structuring
Galvanic deposition
„Through-mask-plating“
bottom up TSV; RDL; Pillar
Not one plating solution for both technologies
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Copper Sulphate35 – 50 g/l
Sulphuric Acid170-100 g/l
Chloride30-100 g/l
Brightener• adsorbs on Copper• disables Cu-deposition
Carrier• desorbs Brightener• enables Cu-deposition
Leveller• adsorbs on copper• surpress Cu-deposition
Copper Electrolyte Composition
Microscopic level Macroscopic level
Additives determine deposition quality
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Bottom Up TSV electroplating: Status
Dimensions20 x 500 µm
200 x 450 µm
Done in collaboration
deposition speed not jet optimized
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Copper Pillar: Spherolyte Leveller UF
Profile 4,4 % 4,4 % 6,3 %uniformity
1 µm/min 2 µm/min 2.5 µm/min
Profile uniformity
80 µm array bump
- Pillar plating know how to be adopted to very high A/R- TSV related targets?
- dimensions, deposition speed (CoO); profile homogenity, ..
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• Plating targets1 void free filling2 fast 3 low overburden 4 low dimple5 low stress5 low additive consumption
• Main impacting factors• Electrolyte/ Additives • Current profile
• Flow (equipment)
• Via shape• Seed layer resistivity
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1
TSV Copper plating targets & main impact factors
Risk of „pinch off“
Avoiding pinch off enables faster void free filling
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Copper electrolyte• Leveller: - strong Copper plating inhibitor
- diffusion controlled enrichment
δN
TSV
Electrolyte
Leveler
Leveler inhibits copper deposition at via aperture preventing pinch offNot one recipe for all TSV dimensions
Role of Additives for pinch off: Leveler
Concentration Spherolyte Leveller AT = 10 ml/l
Concentration Spherolyte Leveller AT = 20 ml/l
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Pulse reverse prevents pinch off & reduce overburdenRoughness impact for CMP?
Role of Current schema: DC versus AC
Same Electrolyte/ plating time
DC AC TS
V
time
current
1
2
1 Cu2+ + 2e- → Cu2 Cu → Cu2+ + 2e-
Reverse Pulse
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Conformal TSV electroplating: Status
A/R: wide range fillable Speed: 10 x 65 µm in 45 min @ Semitool CFD3
Diameter [µm]
Asp
ect R
atio
40 µm
2
20 µm
5
10 µm
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Electrolytic copper filling of through silicon vias in different aspect ratio
Investigated on different seed layer types
∑ TSV: initial target (void free ; < 1h) √; target reinforcement required
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Bottom of TSV: Cu+ + e- → Cu
Top of TSV: Cu+ + e- → CuFe3+ + e- → Fe2+
2Fe3+ + 2Cu → 2Fe2++Cu2+
Distance xδNx = 0
c(Mez+)
Elec
trode Electrolyte
c0(Fe3+)
x *= 0
cS(Fe3+)
Atotech’s Fe 2/3+ system
- Fe3+ : reduces overburden - Hardware & electrolyte modification required
- Does a shorter CMP time justify this?
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Bumping
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Adhesive
Electroplated10 < d < 100µm
Printed100 < d <400µm
Evaporated5 < d < 20µm
Solder Metal-to-Metal
Microbumping• Sn on copper• SnAu• CoSn• Pillar• ....
Bumping• SnAg• SnAgAu• Sn • SnPb• ..
Assembly for 3D
Various suggestions but already consensus?
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Tin (10 µm/min)on < 5 µm TSV ⇒ to large grain size
Micro bumbs - Grain size
Pure Tin/ SnAg3% grain size comparison
Tin
221°C
After deposition (40 µm pads) After reflow235°C
SnAg3%
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2,5 µm
Micro bumps - Assembly
5 µm
reflow
Impact of Wafer bow ?
5 µm
5 µmreflow Risk of Electrical shorts
Geometrical aspects
micro bumbs ≠ W2W ?
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Microbumps - Reliability
Source: Eric Beyne IMEC
Solder joint reliability for fine pitch
• IMC consumes solder• (CuSnCu): EM might lead to spalling• Sn-Oxid → Microvoids
Source: Kim ECTC 2008Source: Kim ECTC 2008
200h @ 150°C 200h @ 150°C; 5x104 A/cm2
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Electromigration: reduce local current density
Alternatives: Pillar/ RDL
CopperTin
500 µm
Pillar
Redistribution
Source: Lai (ASE) ECTC 2008
(Cu, Ni, Pd)6Sn5
Ni(P)
Source: Atotech Peaks 2008
Galvanic Ni/Pd UBM E‘less Ni/Pd UBM
Kirkendahl voids: Under Bump Metallisation
+ printed solder
+ e-plated solder
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Copper Pillar• Status• galvanic UBM/ Tin
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Copper/Tin Pillar
Cu(Ni-P)Sn Pillar
30µm Cu
2µm Ni-P
10µm Sn
Cross section of Cu/Ni/Sn PillarSource: Atotech
50x80 µm copper pillar/ 20 µm Sn; 80 µm pitch Source: IME Singapore using Atotech chemistry
• Reliability data for Cu/(Ni-P)/Sn microbumps?• Thickness, P-content etc
• Target costs?• process time ?• Plating through photo resist?
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• Status RDL• e’less UBM
• Ni/Pd solder & bond reliability• Equipment solutions
Copper RDL + solder paste
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Cu-RDL: Spherolyte Leveller UF
Deposition rate…..
0.4 µm/min 0.6 µm/min 0.8 µm/min 1.0 µm/min
Within dye uniformity
Roughness < 7 nm
Matured process with high within wafer thickness homogenity
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E’less UBM for solderingNi(P)/Pd process flow
Ni Pd
Etch Activator PostdipCu pad:
Process on Cu (d >50 µm) pads industrialized E’less = mask less process ⇒ cost advantage
E‘less Metal dep.Sur. PretreatmentMetal Pad
Metal Pad PR process PR stripMetal dep.PVD
E’less versus PVD
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E’less Ni/Pd UBM: Soldering
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Shear strength: multiple reflow test Solder Mechanism: IMC Ni/Pd
0
10
20
30
40
50
60
70
80
1 5 10
3um Ni/0,1umPd/30nm Au
3um Ni/0,1umPd
Number of Reflow Cycle
Lot’s of experience available (Flip chip)Solder Shear fore: 10x RF; 1000h HAST passed
Sol
derB
all S
hear
Forc
e [g
](Cu, Ni, Pd)6Sn5
Ni(P)
(Cu, Ni,Pd)6Sn5
Ni(P) ( Ni, Cu)3Sn4
1x RF
10x RF Required minimum strength 3 g/mil2
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E’less Ni/Pd UBM: Wire Bonding Bond mechanism
Ni
Au
Pd
300nm
SEM EDS after 1000h @ 150°C
Shear strength: HAST
0,0
5,0
10,0
15,0
20,0
25,0
30,0
35,0
40,0
45,0
50,0
55,0
0 hr 250 hrs 500 hrs 1000 hrs
0.3 umPd / 3 umNi
Time @ 150C
Au
Bal
l She
arFo
rce
[g]
Required minimum strength
Shear force within spec
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Semitool “Raider” “Cintillio”
Single wafer tool • Batch tool10 Wafer/h • 100 Wafer/hCommercialized • α-Tool @ Atotech/ Germany
Single wafer immersion & Batch spray tool
Tools available for • low/ high through put
• front side/ front & back side deposition
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• conformal plating• through mask plating
Galvanic plating principles
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Galvanic plating principles
„Panel-plating“
Galvanic deposition
Barrier & plating base deposition
conformal TSV; DD
Photo-resist coating & structuring
Galvanic deposition
„Through-mask-plating“
RDL; Pillar; bottom up TSV
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Atotech Additive conformal bottom up
10 x 60 µm
Spherolyte • Brightener• Leveller B• Leveller AT
Copper Electrolyte Composition
60 x 70 µm
Electrolyte TSV ≠ TSV/Pillar = RDL
Spherolyte• Brightener • Leveller UF
40 x 50 µm
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Copper Electrolyte Composition
Copper plating of TSV and RDL will require different Chemistrynot at the same plater
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TSV Seed layer• Requirements• e’less deposition
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Seed layer for TSV
Effect of inhomogene seed layer Effect of inhomogene seed layerTSV diameter µm]
++
+
Cu
f illi n
gde
pth
[ µm
]
• Seed layer target• on wafer: d > 200 nm for good within wafer homogenity• inside TSV
• continuous• thickness target tbd (plating speed: the thicker the faster)• wettable• adhesion to barrier layer
PVD/ CVD show steep learning curve
IZM/Atotech ECTC 2008
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35 x 100 µm
Electroless copper on SiON
40/40um
Electroless copper on Photoresist (+ galvanic copper)
Electroless copper seed layer
• Feasibility of barrier/ seed layer • long way to go
• Is there really a PVD limitation?• Relevant TSV dimensions?• Road map harmonisation appreciated!
E’less in Barrier materials: very early stage results
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Summary• Atotech fully supports TSV
• direct collaboration with semiconductor industry• 200/300 mm plater for e‘less & galvanic processes in Berlin/ Germany• “plating for semiconductor” dedicated R&D team
• participation in related academic/ industrial consortia• understand needs; performance feed back
• Copper TSV• initial target (void free ; < 1h) √• target reinforcement required
• e.g. within wafer distribution, overburden, stress, < 30 min, CTE, CoO…• high quality/quantity TSV wafer supply is a must• discussion about Atotech’s Fe2/3+ process to reduce Cu-overburden
• Bumping• matured technology pieces available, but need to define 3D technology chain
• 3D stacking dedicated performance to be investigated • reliability: academic consortia; cost target: industry
• e’less seed/ barrier• infant status
• required: target definition, wafer supply, how to evaluate, …• SC industry: road map
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Thank you for your attention