3D-IC Designs require 3D tools

Tools and Methodologies for 3D-IC Design

AJ IncorvaiaVice President, Silicon Package Board GroupMay, 2012

2 © 2012 Cadence Design Systems, Inc. All rights reserved.

Where we are today – Industry View Paradigm Shift from 2D SoCs 3D stacks

Moving to vertical stacking using TSVs providesReuse of older process node (IP reuse/ heterogeneous int.)

Higher performanceLow Power

Reduced Cost


Short, medium and long term path to 3D-ICEDA work starts at least 3-4 years earlier

Si Partitioning with TSV

Interposer

• Market : FPGA

• Xilinx in 2010•Altera in 2012

• 2011-2012

Memory Cube with TSVs

• MARKET : Server & Computing

• IBM & Micron testchip

• 2012-2013

Logic + memory w/ 2.5D TSV Interposer

• MARKET : GPU, Gaming Console

• ST testchip in 2010

• 2013-2014

Wide IO + Logic with TSVs

•MARKET : Mobile, Tablet, gaming

processors

• ST-E /LETI WIOMING in 2011

• 2013-2014

High performance

computing

• MARKET : CPU, MCMs etc

•ST-E /LETI WIOMING in 2011

• ~ 2015

SHORT MEDIUM LONG

Standards, Ecosystem, Cost


So what changes with 3DIC in EDA world? Revamped EDA requirements

New Layout Rules (e.g. alignments)

New Layout Layer (e.g. Back Side RDL)

Thermal & mechanical constraints

New Models, Rules

New Layout & Electrical Feature (e.g. TSV)

New Floorplanning & Blockage Rules (TSV)

Courtesy : Qualcomm


3DIC Design Flow Challenges

5

3D Floorplan – Optimized powerPlan and TSV/Bump locations

System Level Exploration

Ne

w 3

DIC

De

sig

n F

low

Ch

alle

ng

es ImplementationPlacement, Optimization and Routing

Extraction and AnalysisManage Power, Thermal and SI

DFT for 3DIC Stack& Diagnostics

Silicon Package Co-Design


Die to Die Co-Design FlowOpen access enables interaction between analog and digital

3D Stack Die Editor

3D Floorplan – Optimized powerPlan and TSV/Bump locations

TSV /Bump RDL Routing

Silicon Interposer

Custom Editing

3D IR Drop Analysis

3D Thermal Maps

Silicon Interposer

IC-Package Co design flowBack-side Bump Management

Typical 3D-IC Design Flow


Designers: Analysis Driven Design &

Stacking Methodology

System House: Multi-Die

Integrated Package Prototyping

Foundry & IDM : Rules, Stacking

Layers & Modeling

Everyone : DFM/Yield/Reliability

And Redundancy

Partnering with the Ecosystem


Collaboration with Foundry Partners


Custom, Digital & Package solutions need to understand 3D constructs

Modeling and database infrastructure to support TSVs, Micro bumps, backside metals

Seamless Digital, Custom and Package co-designComprehensive solutions needed to span all aspects of IC design, including

digital design, analog and custom design and packaging co-design

Ecosystem partnershipsEcosystem is still developing, so partnerships are needed to develop

methodologies and proof points between the various stakeholders

Foundation required to enable 3D-IC

10 © 2012 Cadence Design Systems, Inc. All rights reserved.10 © 2011 Cadence Design Systems, Inc. All Rights Reserved

Industry Example: 2.5D Using Silicon InterposerSource: RTI 3D conference 2010 proceedings


Industry Example: 3D IC Stack with WideIO


• Cadence is the technology leader providing complete and integrated 3D-IC solution– Plan->implement->test->verify– 1st to market wide I/O memory controller

• Developed in close partner-collaboration for 5+ years with leading foundries and customers

• Multiple 3D-IC tapeouts– Multiple testchip experience: Memory over

logic (28 nm), logic over analog, logic over Logic, 3-stack dies

– Production design tapeouts

Summary: Cadence silicon-proven 3D-IC solutionPlan Implement Test Verify

3D-IC Designs require 3D tools

Technology

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